From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0631EB64DC for ; Wed, 21 Jun 2023 03:16:26 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1D97086343; Wed, 21 Jun 2023 05:16:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SW8HZ9uY"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8DF8E86308; Wed, 21 Jun 2023 05:16:23 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2B4CE861F5 for ; Wed, 21 Jun 2023 05:16:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687317380; x=1718853380; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=WwzSdZSXRzcBGgs38oyq65HCe2XX/owxfVS+pU1IJ4o=; b=SW8HZ9uYXBQb8bQ9XReVbGyix3rA6up2Hw69wLxZr80dEsxZoHfu68/4 5uNERXgK23G2+v4vZsONS8BLkeTjG8Jg33ra8my9Ldaln31vuEkBjKG8g aKiDRwdqkpGZ2NDalYOhYCKSZNDCED37W8tdiFb4cbkgceZ3UAth0axfS qIEpl1FbRaWVH9kspR29cu7YziORJXFKws0c1ZehjOzEKvxO3s78dC3kK komjPIpS2+ZCxfafwRYVbYWg2uM4dBZLcic51UJIAk5m1UTCaEYdSnH85 zinPuz1w72UVs5xd1jGwC7ldAU2e56gtkGWIOBGa1Jf4ehX9BLKe2TBs7 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="360059690" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="360059690" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2023 20:16:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="664479847" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="664479847" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga003.jf.intel.com with ESMTP; 20 Jun 2023 20:16:14 -0700 Received: from localhost (pgli0121.png.intel.com [10.221.240.84]) by pglmail07.png.intel.com (Postfix) with ESMTP id 632C4482D; Wed, 21 Jun 2023 11:16:13 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 315EA2950; Wed, 21 Jun 2023 11:16:13 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH v1 00/17] Agilex5 Platform Enablement Date: Wed, 21 Jun 2023 11:15:53 +0800 Message-Id: <20230621031610.28401-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Intel Agilex5 is a midrange FPGAs optimized for applications requiring high performance, lower power, and smaller form factors and lower logic densities. U-Boot is one of the bootloader to boot along with ARM trusted Firmware to boot the board up. *** BLURB HERE *** Jit Loon Lim (16): arch: arm: update kconfig for new platform agilex5 arch: arm: dts: add dts and dtsi for new platform agilex5 arch: arm: mach-socfpga: add new platform agilex5 mach-socfpga enablement arch: arm: mach-socfpga: include: mach: add new platform agilex5 mach-socfpga enablement board: intel: add new platform agilex5 socdk configs: add new platform agilex5 defconfig doc: device-tree-bindings: misc: add secreg text file for agilex5 drivers: ddr: altera: add ddr support for agilex5 drivers: clk: altera: add clock support for agilex5 drivers: misc: update driver misc for agilex5 drivers: mmc: add mmc/cadence driver for agilex5 drivers: phy: add combo phy driver for agilex5 drivers: reset: add reset driver for agilex5 drivers: sysreset: add system driver for agilex5 drivers: watchdog: update watchdog driver for agilex5 includes: add and update configuration for agilex5 Sieu Mun Tang (1): tools: binman: update binman tool for agilex5 arch/arm/Kconfig | 5 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 459 ++++++++++ arch/arm/dts/socfpga_agilex5.dtsi | 634 +++++++++++++ .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 131 +++ arch/arm/dts/socfpga_agilex5_socdk.dts | 165 ++++ arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 38 +- arch/arm/dts/socfpga_soc64_u-boot.dtsi | 120 +++ arch/arm/dts/socfpga_stratix10.dtsi | 0 .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 0 arch/arm/dts/socfpga_stratix10_socdk.dts | 0 arch/arm/mach-socfpga/Kconfig | 92 ++ arch/arm/mach-socfpga/Makefile | 69 +- arch/arm/mach-socfpga/board.c | 65 +- arch/arm/mach-socfpga/clock_manager_agilex5.c | 82 ++ arch/arm/mach-socfpga/firewall.c | 107 --- .../include/mach/base_addr_soc64.h | 43 +- .../mach-socfpga/include/mach/clock_manager.h | 5 +- .../include/mach/clock_manager_agilex5.h | 12 + arch/arm/mach-socfpga/include/mach/firewall.h | 42 +- .../mach-socfpga/include/mach/handoff_soc64.h | 25 +- .../mach-socfpga/include/mach/mailbox_s10.h | 32 +- .../include/mach/reset_manager_soc64.h | 33 +- .../mach-socfpga/include/mach/smmu_agilex5.h | 30 + arch/arm/mach-socfpga/include/mach/smmu_s10.h | 73 ++ .../include/mach/system_manager_soc64.h | 126 ++- arch/arm/mach-socfpga/include/mach/timer.h | 30 + arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 61 ++ arch/arm/mach-socfpga/lowlevel_init_soc64.S | 167 +++- arch/arm/mach-socfpga/mailbox_s10.c | 21 + arch/arm/mach-socfpga/misc.c | 19 +- arch/arm/mach-socfpga/misc_soc64.c | 33 +- arch/arm/mach-socfpga/mmu-arm64_s10.c | 43 +- arch/arm/mach-socfpga/reset_manager_s10.c | 271 +++++- arch/arm/mach-socfpga/secure_reg_helper.c | 4 +- arch/arm/mach-socfpga/smmu_agilex5.c | 34 + arch/arm/mach-socfpga/smmu_s10.c | 126 +++ arch/arm/mach-socfpga/spl_agilex5.c | 180 ++++ arch/arm/mach-socfpga/spl_soc64.c | 188 +++- arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 93 ++ arch/arm/mach-socfpga/wrap_handoff_soc64.c | 7 +- board/intel/agilex5-socdk/MAINTAINERS | 8 + board/intel/agilex5-socdk/Makefile | 7 + board/intel/agilex5-socdk/socfpga.c | 7 + configs/socfpga_agilex5_defconfig | 125 +++ configs/socfpga_agilex5_legacy_defconfig | 87 ++ .../misc/socfpga_secreg.txt | 397 ++++++++ drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex5.c | 736 +++++++++++++++ drivers/clk/altera/clk-agilex5.h | 263 ++++++ drivers/ddr/altera/Makefile | 5 +- drivers/ddr/altera/iossm_mailbox.c | 786 ++++++++++++++++ drivers/ddr/altera/iossm_mailbox.h | 141 +++ drivers/ddr/altera/sdram_agilex5.c | 329 +++++++ drivers/ddr/altera/sdram_soc64.c | 78 +- drivers/ddr/altera/sdram_soc64.h | 17 +- drivers/misc/Kconfig | 9 + drivers/misc/Makefile | 1 + drivers/misc/socfpga_secreg.c | 116 +++ drivers/mmc/mmc.c | 27 +- drivers/mmc/sdhci-cadence.c | 164 +++- drivers/phy/cadence/Kconfig | 9 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-combophy.c | 855 ++++++++++++++++++ drivers/reset/reset-socfpga.c | 28 +- drivers/sysreset/Kconfig | 7 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_socfpga_agilex5.c | 44 + drivers/watchdog/Kconfig | 2 +- include/configs/socfpga_agilex5_socdk.h | 12 + include/configs/socfpga_soc64_common.h | 214 ++++- include/dt-bindings/clock/agilex5-clock.h | 71 ++ include/dt-bindings/reset/altr,rst-mgr-agx5.h | 82 ++ tools/binman/control.py | 8 +- 74 files changed, 8019 insertions(+), 285 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c delete mode 100644 arch/arm/mach-socfpga/firewall.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h create mode 100644 arch/arm/mach-socfpga/include/mach/smmu_agilex5.h create mode 100644 arch/arm/mach-socfpga/include/mach/smmu_s10.h create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S create mode 100644 arch/arm/mach-socfpga/smmu_agilex5.c create mode 100644 arch/arm/mach-socfpga/smmu_s10.c create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds create mode 100644 board/intel/agilex5-socdk/MAINTAINERS create mode 100644 board/intel/agilex5-socdk/Makefile create mode 100644 board/intel/agilex5-socdk/socfpga.c create mode 100644 configs/socfpga_agilex5_defconfig create mode 100644 configs/socfpga_agilex5_legacy_defconfig create mode 100644 doc/device-tree-bindings/misc/socfpga_secreg.txt create mode 100644 drivers/clk/altera/clk-agilex5.c create mode 100644 drivers/clk/altera/clk-agilex5.h create mode 100644 drivers/ddr/altera/iossm_mailbox.c create mode 100644 drivers/ddr/altera/iossm_mailbox.h create mode 100644 drivers/ddr/altera/sdram_agilex5.c create mode 100644 drivers/misc/socfpga_secreg.c create mode 100644 drivers/phy/cadence/phy-cadence-combophy.c create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c create mode 100644 include/configs/socfpga_agilex5_socdk.h create mode 100644 include/dt-bindings/clock/agilex5-clock.h create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h -- 2.26.2