[PATCH v1 10/17] drivers: misc: update driver misc for agilex5

[Jit Loon Lim <jit.loon.lim@intel.com>]

This is for new platform enablement for agilex5.
Update secure registers, Kconfig and makefile for new platform.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 drivers/misc/Kconfig          |   9 +++
 drivers/misc/Makefile         |   1 +
 drivers/misc/socfpga_secreg.c | 116 ++++++++++++++++++++++++++++++++++
 3 files changed, 126 insertions(+)
 create mode 100644 drivers/misc/socfpga_secreg.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 04460f1acb..3b6f5314ff 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -666,4 +666,13 @@ config SL28CPLD
 	  the base driver which provides common access methods for the
 	  sub-drivers.
 
+config SPL_SOCFPGA_SEC_REG
+	bool "Enable register setting from device tree in SPL"
+	depends on SPL
+	help
+	  Enable register setting from device tree in SPL, which require
+	  high privilege access like firewall registers. This also
+	  provides user a clean interface and all register settings are
+	  centralized in one place, device tree.
+
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 52aed09602..441c03509f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -88,3 +88,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o
 obj-$(CONFIG_ESM_K3) += k3_esm.o
 obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
 obj-$(CONFIG_SL28CPLD) += sl28cpld.o
+obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_secreg.o
diff --git a/drivers/misc/socfpga_secreg.c b/drivers/misc/socfpga_secreg.c
new file mode 100644
index 0000000000..3f3ba8b0c1
--- /dev/null
+++ b/drivers/misc/socfpga_secreg.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021-2023 Intel Corporation <www.intel.com>
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/sizes.h>
+
+#define NUMBER_OF_ELEMENTS 3
+
+static int socfpga_secreg_probe(struct udevice *dev)
+{
+	const fdt32_t *list;
+	fdt_addr_t offset, base;
+	fdt_val_t val, read_val, mask, set_mask;
+	int size, i;
+	u32 blk_sz, reg;
+	ofnode node;
+	const char *name = NULL;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	if (!dev_has_ofnode(dev))
+		return 0;
+
+	dev_for_each_subnode(node, dev) {
+		name = ofnode_get_name(node);
+		if (!name)
+			return -EINVAL;
+
+		if (ofnode_read_u32_index(node, "reg", 1, &blk_sz))
+			return -EINVAL;
+
+		base = ofnode_get_addr(node);
+		if (base == FDT_ADDR_T_NONE)
+			return -EINVAL;
+
+		debug("%s(node_offset 0x%lx node_name %s ", __func__,
+		      node.of_offset, name);
+		debug("node addr 0x%llx blk sz 0x%x)\n", base, blk_sz);
+
+		list = ofnode_read_prop(node, "intel,offset-settings", &size);
+		if (!list)
+			return -EINVAL;
+
+		debug("%s(intel,offset-settings property size=%x)\n", __func__,
+		      size);
+		size /= sizeof(*list) * NUMBER_OF_ELEMENTS;
+
+		/*
+		 * First element: offset
+		 * Second element: val
+		 * Third element: mask
+		 */
+		for (i = 0; i < size; i++) {
+			offset = fdt32_to_cpu(*list++);
+			val = fdt32_to_cpu(*list++);
+
+			/* Reads the masking bit value from the list */
+			mask = fdt32_to_cpu(*list++);
+
+			/*
+			 * Reads out the offsets, value and masking bits
+			 * Ex: <0x00000000 0x00000230 0xffffffff>
+			 */
+			debug("%s(intel,offset-settings 0x%llx : 0x%llx : 0x%llx)\n",
+			      __func__, offset, val, mask);
+
+			if (blk_sz < offset + SZ_4) {
+				printf("%s: Overflow as offset 0x%llx or reg",
+				       __func__, offset);
+				printf(" write is more than block size 0x%x\n",
+				       blk_sz);
+				return -EINVAL;
+			}
+
+			if (mask != 0) {
+				if (mask == 0xffffffff) {
+					reg = base + offset;
+					writel(val, (uintptr_t)reg);
+				} else {
+					/* Mask the value with the masking bits */
+					set_mask = val & mask;
+
+					reg = base + offset;
+
+					/* Clears and sets specific bits in the register */
+					clrsetbits_le32((uintptr_t)reg, mask, set_mask);
+				}
+			}
+
+			read_val = readl((uintptr_t)reg);
+
+			/* Reads out the register, masked value and the read value */
+			debug("%s(reg 0x%x = wr : 0x%llx  rd : 0x%llx)\n",
+			      __func__, reg, set_mask, read_val);
+		}
+	}
+
+	return 0;
+};
+
+static const struct udevice_id socfpga_secreg_ids[] = {
+	{.compatible = "intel,socfpga-secreg"},
+	{ }
+};
+
+U_BOOT_DRIVER(socfpga_secreg) = {
+	.name		= "socfpga-secreg",
+	.id		= UCLASS_NOP,
+	.of_match	= socfpga_secreg_ids,
+	.probe		= socfpga_secreg_probe,
+};
-- 
2.26.2