From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51939EB64D7 for ; Wed, 21 Jun 2023 03:18:11 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2600E8636A; Wed, 21 Jun 2023 05:17:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Dw+MQhY2"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9CC0986442; Wed, 21 Jun 2023 05:16:51 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BB50A8636A for ; Wed, 21 Jun 2023 05:16:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687317386; x=1718853386; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aPx17nK0rECOZNOh5+m55rfLvv5IrMX3n4ievoK2Lv4=; b=Dw+MQhY2ambuGtTUlSIM7q73dUgazEyu+fYI0RseBcGDZq2Y1TLvXUcd H5zzrKtgIIHMkUXHetNejEnd8abweJH0Zlhh/SIDjQPAMd7Q1bH8AZqve wshRXIfuni05qQSkxX0afJPZZlN2YpGqJ7xfuqmMy+KYnWjnTJSjVCDqp PkWkrk/I9ONBlixkn4V7U9allVguJFjdZAl63y4hMQG7d92b5xFVhkFha tnLrUiziel3kLup5wbGDzFxHZjf+7fqFWtNFnmJ2tND3rbqOKrKlDRH1d Yd7esRTVXZis6WClXEf6Lo1WFHc1ukagBJweaOgtMxfQqFRnJKbNZHJpF Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="360059758" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="360059758" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2023 20:16:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="664479890" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="664479890" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga003.jf.intel.com with ESMTP; 20 Jun 2023 20:16:21 -0700 Received: from localhost (pgli0121.png.intel.com [10.221.240.84]) by pglmail07.png.intel.com (Postfix) with ESMTP id 0DC572B6B; Wed, 21 Jun 2023 11:16:21 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 0BEC52950; Wed, 21 Jun 2023 11:16:21 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH v1 10/17] drivers: misc: update driver misc for agilex5 Date: Wed, 21 Jun 2023 11:16:03 +0800 Message-Id: <20230621031610.28401-11-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230621031610.28401-1-jit.loon.lim@intel.com> References: <20230621031610.28401-1-jit.loon.lim@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This is for new platform enablement for agilex5. Update secure registers, Kconfig and makefile for new platform. Signed-off-by: Jit Loon Lim --- drivers/misc/Kconfig | 9 +++ drivers/misc/Makefile | 1 + drivers/misc/socfpga_secreg.c | 116 ++++++++++++++++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 drivers/misc/socfpga_secreg.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 04460f1acb..3b6f5314ff 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -666,4 +666,13 @@ config SL28CPLD the base driver which provides common access methods for the sub-drivers. +config SPL_SOCFPGA_SEC_REG + bool "Enable register setting from device tree in SPL" + depends on SPL + help + Enable register setting from device tree in SPL, which require + high privilege access like firewall registers. This also + provides user a clean interface and all register settings are + centralized in one place, device tree. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 52aed09602..441c03509f 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -88,3 +88,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o +obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_secreg.o diff --git a/drivers/misc/socfpga_secreg.c b/drivers/misc/socfpga_secreg.c new file mode 100644 index 0000000000..3f3ba8b0c1 --- /dev/null +++ b/drivers/misc/socfpga_secreg.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2023 Intel Corporation + */ + +#include +#include +#include +#include +#include + +#define NUMBER_OF_ELEMENTS 3 + +static int socfpga_secreg_probe(struct udevice *dev) +{ + const fdt32_t *list; + fdt_addr_t offset, base; + fdt_val_t val, read_val, mask, set_mask; + int size, i; + u32 blk_sz, reg; + ofnode node; + const char *name = NULL; + + debug("%s(dev=%p)\n", __func__, dev); + + if (!dev_has_ofnode(dev)) + return 0; + + dev_for_each_subnode(node, dev) { + name = ofnode_get_name(node); + if (!name) + return -EINVAL; + + if (ofnode_read_u32_index(node, "reg", 1, &blk_sz)) + return -EINVAL; + + base = ofnode_get_addr(node); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + debug("%s(node_offset 0x%lx node_name %s ", __func__, + node.of_offset, name); + debug("node addr 0x%llx blk sz 0x%x)\n", base, blk_sz); + + list = ofnode_read_prop(node, "intel,offset-settings", &size); + if (!list) + return -EINVAL; + + debug("%s(intel,offset-settings property size=%x)\n", __func__, + size); + size /= sizeof(*list) * NUMBER_OF_ELEMENTS; + + /* + * First element: offset + * Second element: val + * Third element: mask + */ + for (i = 0; i < size; i++) { + offset = fdt32_to_cpu(*list++); + val = fdt32_to_cpu(*list++); + + /* Reads the masking bit value from the list */ + mask = fdt32_to_cpu(*list++); + + /* + * Reads out the offsets, value and masking bits + * Ex: <0x00000000 0x00000230 0xffffffff> + */ + debug("%s(intel,offset-settings 0x%llx : 0x%llx : 0x%llx)\n", + __func__, offset, val, mask); + + if (blk_sz < offset + SZ_4) { + printf("%s: Overflow as offset 0x%llx or reg", + __func__, offset); + printf(" write is more than block size 0x%x\n", + blk_sz); + return -EINVAL; + } + + if (mask != 0) { + if (mask == 0xffffffff) { + reg = base + offset; + writel(val, (uintptr_t)reg); + } else { + /* Mask the value with the masking bits */ + set_mask = val & mask; + + reg = base + offset; + + /* Clears and sets specific bits in the register */ + clrsetbits_le32((uintptr_t)reg, mask, set_mask); + } + } + + read_val = readl((uintptr_t)reg); + + /* Reads out the register, masked value and the read value */ + debug("%s(reg 0x%x = wr : 0x%llx rd : 0x%llx)\n", + __func__, reg, set_mask, read_val); + } + } + + return 0; +}; + +static const struct udevice_id socfpga_secreg_ids[] = { + {.compatible = "intel,socfpga-secreg"}, + { } +}; + +U_BOOT_DRIVER(socfpga_secreg) = { + .name = "socfpga-secreg", + .id = UCLASS_NOP, + .of_match = socfpga_secreg_ids, + .probe = socfpga_secreg_probe, +}; -- 2.26.2