From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3731AEB64D7 for ; Wed, 21 Jun 2023 03:18:56 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1A16E861F5; Wed, 21 Jun 2023 05:17:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XZz120vM"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 30A9786309; Wed, 21 Jun 2023 05:17:00 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0280C8637F for ; Wed, 21 Jun 2023 05:16:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687317388; x=1718853388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sTVs92fU9iGok+ceZgV2RtiPPMST+Z6HplR6jo42/HU=; b=XZz120vM/tnfcjkkW7lV7+BZVu9K8jf4aBnJmhBuvJaEDm4g7pnEdLec Ff1xL/frnn0pLOJ5B0Y8V2PqpnN+OgGp3rFIAGj/MJfp+fJEOn3hi0LfU c1dG5fagbCzzbH/q/r+c8rjjHV3PAbAq+tSropIWzOb0tDSXR5RkPn4l2 OeNti21TkSZuOPC+DHP6kTh5+McnEZUDR574YxmEOAR63guTNliI7FUtE 89WZI+1QwPb8fxTbfr1GNnkZBuf/6rvKqJd3Fz5FmCyyzpCD00136FNmE /zvG883XXyRY2mb1uCx7z2suPL15SQCBraFh8t9ojwdMjG45GDvVTwxTr Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="360059782" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="360059782" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2023 20:16:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="664479899" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="664479899" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga003.jf.intel.com with ESMTP; 20 Jun 2023 20:16:23 -0700 Received: from localhost (pgli0121.png.intel.com [10.221.240.84]) by pglmail07.png.intel.com (Postfix) with ESMTP id BEE112B93; Wed, 21 Jun 2023 11:16:22 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id BD1212950; Wed, 21 Jun 2023 11:16:22 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH v1 13/17] drivers: reset: add reset driver for agilex5 Date: Wed, 21 Jun 2023 11:16:06 +0800 Message-Id: <20230621031610.28401-14-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230621031610.28401-1-jit.loon.lim@intel.com> References: <20230621031610.28401-1-jit.loon.lim@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This is for new platform enablement for agilex5. Add reset driver for new platform. Signed-off-by: Jit Loon Lim --- drivers/reset/reset-socfpga.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 6e3f03e248..8b35f0685d 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -24,9 +24,18 @@ #include #include #include - -#define BANK_INCREMENT 4 -#define NR_BANKS 8 +#include + +#define BANK_INCREMENT 4 +#define NR_BANKS 8 +#define RSTMGR_PER0MODRST_USB31 BIT(4) +#define RSTMGR_PER0MODRST_NAND BIT(5) +#define RSTMGR_PER0MODRST_DMA BIT(16) +#define RSTMGR_PER0MODRST_DMAIF GENMASK(31, 24) +#define RSTMGR_PER0MODRST_USB31_NAND_DMA_DEASSERT RSTMGR_PER0MODRST_USB31 \ + | RSTMGR_PER0MODRST_NAND \ + | RSTMGR_PER0MODRST_DMA \ + | RSTMGR_PER0MODRST_DMAIF struct socfpga_reset_data { void __iomem *modrst_base; @@ -112,9 +121,22 @@ static int socfpga_reset_remove(struct udevice *dev) { struct socfpga_reset_data *data = dev_get_priv(dev); +/* + * TODO: This is temporary solution for NAND/DMA/USB3.1 deaasert. + * When NAND/DMA/USB3.1 driver is ready, the deassert shall be done + * from NAND/DMA/USB3.1 driver. + */ +#if defined(CONFIG_TARGET_SOCFPGA_AGILEX5) + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST, + RSTMGR_PER0MODRST_USB31_NAND_DMA_DEASSERT); +#endif + if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + writel(0, data->modrst_base + 8); +#endif } return 0; -- 2.26.2