From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DD55EB64D8 for ; Wed, 21 Jun 2023 03:19:07 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9860F86362; Wed, 21 Jun 2023 05:17:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jq5EjzKJ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B018A862FD; Wed, 21 Jun 2023 05:17:06 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E51F486386 for ; Wed, 21 Jun 2023 05:16:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687317389; x=1718853389; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vYdfVuaLzIRxwLxk5fT0FrAK8ec9WhMAvXREOSnIK+A=; b=jq5EjzKJsvcFDkwMOQ1RC5KR9kd6NaMdgxsYCU2T3JzW6I10wDeBj7dX PEkGuNyYDOQKbX2FpsOuNtEB1hfc4t5BRqHi4lV2n9BUmMGtXamBhkxbS 0g/trbOy4w32gQ3YwRwwx75GkQTd2ELhEKyNkcYMKAeneurG2+lzNoMIt ZvMQbhhh8K4i5bRdAavIF2eMUrWjqF3zmDaHKbRK0FLPbZyUSx8cxY3fr wMymUqQZCmW6AOmgNHKmOde3MDzMAlkYiFevQxkONfnn1Q3BVOC3WzRc6 VVrwctddDbzgpOzRA5WqKg8rJmRC9LP4g0QHRp2EaHkBNoxFOqUEyUlIl A==; X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="360059793" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="360059793" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2023 20:16:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="664479903" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="664479903" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga003.jf.intel.com with ESMTP; 20 Jun 2023 20:16:23 -0700 Received: from localhost (pgli0121.png.intel.com [10.221.240.84]) by pglmail07.png.intel.com (Postfix) with ESMTP id 49CCA2B94; Wed, 21 Jun 2023 11:16:23 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 481B42950; Wed, 21 Jun 2023 11:16:23 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH v1 14/17] drivers: sysreset: add system driver for agilex5 Date: Wed, 21 Jun 2023 11:16:07 +0800 Message-Id: <20230621031610.28401-15-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230621031610.28401-1-jit.loon.lim@intel.com> References: <20230621031610.28401-1-jit.loon.lim@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This is for new platform enablement for agilex5. Add cold, warm reset logic for new platform. Signed-off-by: Jit Loon Lim --- drivers/sysreset/Kconfig | 7 ++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_socfpga_agilex5.c | 44 +++++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 03f7fdd597..850191eeed 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -137,6 +137,13 @@ config SYSRESET_SOCFPGA_SOC64 This enables the system reset driver support for Intel SOCFPGA SoC64 SoCs. +config SYSRESET_SOCFPGA_AGILEX5 + bool "Enable support for Intel SOCFPGA AGILEX5 device" + depends on ARCH_SOCFPGA && TARGET_SOCFPGA_AGILEX5 + help + This enables the system reset driver support for Intel SOCFPGA + AGILEX5 device. + config SYSRESET_TI_SCI bool "TI System Control Interface (TI SCI) system reset driver" depends on TI_SCI_PROTOCOL diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 40c876764a..6631a71db6 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o +obj-$(CONFIG_SYSRESET_SOCFPGA_AGILEX5) += sysreset_socfpga_agilex5.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o diff --git a/drivers/sysreset/sysreset_socfpga_agilex5.c b/drivers/sysreset/sysreset_socfpga_agilex5.c new file mode 100644 index 0000000000..7b05ffd269 --- /dev/null +++ b/drivers/sysreset/sysreset_socfpga_agilex5.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Intel Corporation + * + */ + +#include +#include +#include +#include +#include +#include +#include + +static int socfpga_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + const char *reset = env_get("reset"); + + if (reset && !strcmp(reset, "warm")) { + /* request a warm reset */ + puts("Do warm reset now...\n"); + + /* doing architecture system reset */ + psci_system_reset2(0, 0); + } else { + puts("Issuing cold reset REBOOT_HPS\n"); + psci_system_reset(); + } +#endif + + return -EINPROGRESS; +} + +static struct sysreset_ops socfpga_sysreset = { + .request = socfpga_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_socfpga) = { + .id = UCLASS_SYSRESET, + .name = "socfpga_sysreset", + .ops = &socfpga_sysreset, +}; -- 2.26.2