From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E4E0EB64D8 for ; Wed, 21 Jun 2023 14:01:43 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D76B98637B; Wed, 21 Jun 2023 16:01:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="j//iOZBe"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 847898638A; Wed, 21 Jun 2023 16:01:34 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D0D7686372 for ; Wed, 21 Jun 2023 16:01:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687356090; x=1718892090; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=7zQqv3jsDla7eCjonSxKpSCdg+6533hMcXM1KiKzyO4=; b=j//iOZBe3pxnS2tS7bnnIX/y80IDYkqbbWQtVdih1tpcLkBtGT56VY5B WIvZJeJdI9DWd2nFEd3ZzFlwV5xV6M5SNSQ13xwIrHd+UE29Q4K7M8VZs nukFEMaKfjXsDXzxbdE7GiNkI1BEF6JsVCpIayjFG/0wPbUM1sAKyKap3 A4H9OI0U5bzZhSnP5+DUYukLpU7xkAFjyynrSInW4kSaqI3pueZHDoS38 BmBOVL/J+ODxOG51bFrXHYoSrq/atGmKP0V6yf8ewaO+m1IDZzyOGgEog d7F6AHMKaW1YbX2ZtsouwclP9vdVDX8UuXqXUy8n0TjzPsXHw99UfNhVw A==; X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="360193988" X-IronPort-AV: E=Sophos;i="6.00,260,1681196400"; d="scan'208";a="360193988" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2023 07:01:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="961203550" X-IronPort-AV: E=Sophos;i="6.00,260,1681196400"; d="scan'208";a="961203550" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga006.fm.intel.com with ESMTP; 21 Jun 2023 07:00:58 -0700 Received: from localhost (pgli0121.png.intel.com [10.221.240.84]) by pglmail07.png.intel.com (Postfix) with ESMTP id 2DB82482D; Wed, 21 Jun 2023 22:00:58 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 27E613E08; Wed, 21 Jun 2023 22:00:58 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Marek , Simon , Tien Fong , Kok Kiang , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Sin Hui Kho Subject: [PATCH v1] arm: socfpga: agilex5: Define MMU mapping region for FPGA Date: Wed, 21 Jun 2023 22:00:57 +0800 Message-Id: <20230621140057.8787-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Sin Hui Kho Add MMU mapping region for FPGA including 512 MB LW HPS2FPGA and 1GB HPS2FPGA. Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/mmu-arm64_s10.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index 0951233cad..c88f0e8632 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -36,6 +36,14 @@ static struct mm_region socfpga_agilex5_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN, }, { + /* FPGA 1.5GB */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x60000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + },{ /* MEM 2GB */ .virt = 0x80000000UL, .phys = 0x80000000UL, -- 2.26.2