From: Jit Loon Lim <jit.loon.lim@intel.com>
To: u-boot@lists.denx.de
Cc: Jagan Teki <jagan@amarulasolutions.com>, Marek <marex@denx.de>,
Simon <simon.k.r.goldschmidt@gmail.com>,
Tien Fong <tien.fong.chee@intel.com>,
Kok Kiang <kok.kiang.hea@intel.com>,
Raaj <raaj.lokanathan@intel.com>,
Dinesh <dinesh.maniyam@intel.com>,
Boon Khai <boon.khai.ng@intel.com>,
Alif <alif.zakuan.yuslaimi@intel.com>,
Teik Heng <teik.heng.chong@intel.com>,
Hazim <muhammad.hazim.izzat.zamri@intel.com>,
Jit Loon Lim <jit.loon.lim@intel.com>,
Sieu Mun Tang <sieu.mun.tang@intel.com>,
Ying-Chun Liu <paul.liu@linaro.org>,
Marc Zyngier <maz@kernel.org>,
Kah Jing Lee <kah.jing.lee@intel.com>
Subject: [PATCH v1] cache_v8: agilex5: Disable Dcache in the SPL
Date: Wed, 21 Jun 2023 22:06:51 +0800 [thread overview]
Message-ID: <20230621140651.12756-1-jit.loon.lim@intel.com> (raw)
From: Kah Jing Lee <kah.jing.lee@intel.com>
Dcache feature is not enabled in SPL and enable it will cause ISR
exception. Since the Dcache is not supported in SPL, new
CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache
in SPL.
Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com>
---
arch/arm/cpu/armv8/cache_v8.c | 20 +++++++++++---------
common/spl/Kconfig | 7 +++++++
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index cb1131a048..7f25d3a6ce 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -534,29 +534,31 @@ inline void flush_dcache_all(void)
#endif
}
-#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
-/*
- * Invalidates range in all levels of D-cache/unified cache
- */
+#if CONFIG_IS_ENABLED(SYS_DISABLE_DCACHE_OPS) || \
+ CONFIG_IS_ENABLED(SPL_SYS_DISABLE_DCACHE_OPS) && \
+ CONFIG_IS_ENABLED(SPL_BUILD)
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
- __asm_invalidate_dcache_range(start, stop);
}
-/*
- * Flush range(clean & invalidate) from all levels of D-cache/unified cache
- */
void flush_dcache_range(unsigned long start, unsigned long stop)
{
- __asm_flush_dcache_range(start, stop);
}
#else
+/*
+ * Invalidates range in all levels of D-cache/unified cache
+ */
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
+ __asm_invalidate_dcache_range(start, stop);
}
+/*
+ * Flush range(clean & invalidate) from all levels of D-cache/unified cache
+ */
void flush_dcache_range(unsigned long start, unsigned long stop)
{
+ __asm_flush_dcache_range(start, stop);
}
#endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 2c042ad306..7e458503df 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -19,6 +19,13 @@ config SPL
menu "SPL configuration options"
depends on SPL
+config SPL_SYS_DISABLE_DCACHE_OPS
+ bool "Do not enable dcache operation in SPL"
+ depends on SPL
+ help
+ Do not enable data cache operation in SPL. This will turn off the
+ Dcache support and have the empty dcache declaration.
+
config SPL_FRAMEWORK
bool "Support SPL based upon the common SPL framework"
default y
--
2.26.2
next reply other threads:[~2023-06-21 14:07 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-21 14:06 Jit Loon Lim [this message]
2023-06-21 14:15 ` [PATCH v1] cache_v8: agilex5: Disable Dcache in the SPL Marc Zyngier
2023-06-21 14:19 ` Marek Vasut
2023-06-26 9:00 ` Lim, Jit Loon
2023-06-26 9:32 ` Marc Zyngier
2023-06-21 14:19 ` Marek Vasut
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