[PATCH v2 0/5] imx8mn-var-som: fix ethernet for Variscite symphony board and imx8m nano SOM

[PATCH v2 0/5] imx8mn-var-som: fix ethernet for Variscite symphony board and imx8m nano SOM

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Hello,
This patch series fixes bugs and add missing features related to the ethernet
PHY on Variscite symphony carrier board with an imx8m nano SOM
(P/N VAR-SOM-MX8M-NANO).

Ethernet functionality is currently broken for the VAR-SOM-MX8M-NANO.

Variscite imx8m nano SOM comes in multiple hardware configuration options.
One of this hardware configuration option is called EC:
    EC: Ethernet Controller PHY assembled on SOM

For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.

For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.

Patch 1 add code to read and display the SOM configuration stored in the SOM
EEPROM. Part of this patch was submitted and accepted to the Linux kernel
(section that adds the EEPROM to the device tree), so that it will be easier to
sync the DT between kernel and U-Boot.

Patch 2 fixes bugs with the PHY reset properties.

Patch 3 fixes a bug with a missing PHY reset deassert delay (also submitted and
accepted to kernel).

Patch 4 enables automatic read of PHY MAC address from the SOM EEPROM.

Patch 5 is used for auto-detecting at runtime the SOM hardware configuration
option related to the PHY (EC), and dynamically adjust the device tree to
support both SOM PHY options.

I have succesfully tested the changes on a Variscite symphony carrier board with
a VAR-SOM-MX8M-NANO having the EC configuration option.

Unfortunately, I do not have a VAR-SOM-MX8M-NANO with a non-EC configuration
option so I couldn't test it on real hardware, altough I simulated it and
confirmed that the device tree fixing seems to be correct by using debug/print
statements.

Thank you.

Link: [v1] https://lore.kernel.org/u-boot/20230501200121.3137519-1-hugo@hugovil.com/

Changes for V2:
- Resend since I received 0 answers/comments after almost 4 weeks and I have a
  few minor updates to add:
  - Update defconfig using savedefconfig
  - Remove requirement about required patch (now in master)
  - Update status of patches also sent to the Linux kernel

Hugo Villeneuve (5):
  imx8mn-var-som: read and print SoM infos from eeprom on startup
  imx8mn-var-som: fix non-applied PHY reset-gpios properties
  arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert
    delay
  imx8mn-var-som: read eth MAC address from EEPROM
  imx8mn-var-som: adjust PHY reset gpios according to hardware
    configuration

 .../dts/imx8mn-var-som-symphony-u-boot.dtsi   |  17 ++
 arch/arm/dts/imx8mn-var-som-symphony.dts      |   4 -
 arch/arm/dts/imx8mn-var-som.dtsi              |  18 +-
 arch/arm/mach-imx/imx8m/Kconfig               |   4 +
 .../variscite/imx8mn_var_som/imx8mn_var_som.c | 214 ++++++++++++++++++
 configs/imx8mn_var_som_defconfig              |   4 +
 6 files changed, 256 insertions(+), 5 deletions(-)


base-commit: 62df7a39442902a71259568c13a4d496d5a514f4
-- 
2.30.2

[PATCH v2 1/5] imx8mn-var-som: read and print SoM infos from eeprom on startup

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Enable support to read and display configuration/manufacturing infos
from 4Kbit EEPROM located on SOM board.

Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 .../dts/imx8mn-var-som-symphony-u-boot.dtsi   |   4 +
 arch/arm/dts/imx8mn-var-som.dtsi              |  10 ++
 arch/arm/mach-imx/imx8m/Kconfig               |   2 +
 .../variscite/imx8mn_var_som/imx8mn_var_som.c | 134 ++++++++++++++++++
 configs/imx8mn_var_som_defconfig              |   1 +
 5 files changed, 151 insertions(+)

diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index af80aaea0b..7272fc2b4c 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -68,3 +68,7 @@
 &usdhc3 {
 	bootph-pre-ram;
 };
+
+&eeprom_som {
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index 87b5e23c76..dea9eff3f0 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -11,6 +11,10 @@
 	model = "Variscite VAR-SOM-MX8MN module";
 	compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
 
+	aliases {
+		eeprom-som = &eeprom_som;
+	};
+
 	chosen {
 		stdout-path = &uart4;
 	};
@@ -222,6 +226,12 @@
 			};
 		};
 	};
+
+	eeprom_som: eeprom@52 {
+		compatible = "atmel,24c04";
+		reg = <0x52>;
+		pagesize = <16>;
+	};
 };
 
 &i2c3 {
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 7639439bdc..3450399d6f 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -245,6 +245,8 @@ config TARGET_IMX8MN_VAR_SOM
 	select IMX8MN
 	select SUPPORT_SPL
 	select IMX8M_DDR4
+	select MISC
+	select I2C_EEPROM
 
 config TARGET_KONTRON_PITX_IMX8M
 	bool "Support Kontron pITX-imx8m"
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index d40f4d0176..a89457e8f5 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -1,11 +1,49 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2021 Collabora Ltd.
+ * Copyright 2018-2020 Variscite Ltd.
+ * Copyright 2023 DimOnOff Inc.
  */
 
 #include <common.h>
+#include <dm.h>
 #include <env.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <i2c_eeprom.h>
+#include <malloc.h>
 #include <asm/io.h>
+#include <asm/global_data.h>
+#include <linux/libfdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Optional SOM features flags. */
+#define VAR_EEPROM_F_WIFI		BIT(0)
+#define VAR_EEPROM_F_ETH		BIT(1) /* Ethernet PHY on SOM. */
+#define VAR_EEPROM_F_AUDIO		BIT(2)
+#define VAR_EEPROM_F_MX8M_LVDS		BIT(3) /* i.MX8MM, i.MX8MN, i.MX8MQ only */
+#define VAR_EEPROM_F_MX8Q_SOC_ID	BIT(3) /* 0 = i.MX8QM, 1 = i.MX8QP */
+#define VAR_EEPROM_F_NAND		BIT(4)
+
+#define VAR_IMX8_EEPROM_MAGIC	0x384D /* "8M" */
+
+/* Number of DRAM adjustment tables. */
+#define DRAM_TABLES_NUM 7
+
+struct var_imx8_eeprom_info {
+	u16 magic;
+	u8 partnumber[3];         /* Part number */
+	u8 assembly[10];          /* Assembly number */
+	u8 date[9];               /* Build date */
+	u8 mac[6];                /* MAC address */
+	u8 somrev;
+	u8 eeprom_version;
+	u8 features;              /* SOM features */
+	u8 dramsize;              /* DRAM size */
+	u8 off[DRAM_TABLES_NUM + 1]; /* DRAM table offsets */
+	u8 partnumber2[5];        /* Part number 2 */
+} __packed;
 
 static void setup_fec(void)
 {
@@ -28,3 +66,99 @@ int board_mmc_get_env_dev(int devno)
 {
 	return devno;
 }
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+
+static void display_som_infos(struct var_imx8_eeprom_info *info)
+{
+	char partnumber[sizeof(info->partnumber) +
+			sizeof(info->partnumber2) + 1];
+	char assembly[sizeof(info->assembly) + 1];
+	char date[sizeof(info->date) + 1];
+
+	/* Read first part of P/N. */
+	memcpy(partnumber, info->partnumber, sizeof(info->partnumber));
+
+	/* Read second part of P/N. */
+	if (info->eeprom_version >= 3)
+		memcpy(partnumber + sizeof(info->partnumber), info->partnumber2,
+		       sizeof(info->partnumber2));
+
+	memcpy(assembly, info->assembly, sizeof(info->assembly));
+	memcpy(date, info->date, sizeof(info->date));
+
+	/* Make sure strings are null terminated. */
+	partnumber[sizeof(partnumber) - 1] = '\0';
+	assembly[sizeof(assembly) - 1] = '\0';
+	date[sizeof(date) - 1] = '\0';
+
+	printf("SOM board: P/N: %s, Assy: %s, Date: %s\n"
+	       "           Wifi: %s, EthPhy: %s, Rev: %d\n",
+	       partnumber, assembly, date,
+	       info->features & VAR_EEPROM_F_WIFI ? "yes" : "no",
+	       info->features & VAR_EEPROM_F_ETH ? "yes" : "no",
+	       info->somrev);
+}
+
+static int var_read_som_eeprom(struct var_imx8_eeprom_info *info)
+{
+	const char *path = "eeprom-som";
+	struct udevice *dev;
+	int ret, off;
+
+	off = fdt_path_offset(gd->fdt_blob, path);
+	if (off < 0) {
+		pr_err("%s: fdt_path_offset() failed: %d\n", __func__, off);
+		return off;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+	if (ret) {
+		pr_err("%s: uclass_get_device_by_of_offset() failed: %d\n",
+		       __func__, ret);
+		return ret;
+	}
+
+	ret = i2c_eeprom_read(dev, 0, (uint8_t *)info,
+			      sizeof(struct var_imx8_eeprom_info));
+	if (ret) {
+		pr_err("%s: i2c_eeprom_read() failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	if (htons(info->magic) != VAR_IMX8_EEPROM_MAGIC) {
+		/* Do not fail if the content is invalid */
+		pr_err("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n",
+		       htons(info->magic), VAR_IMX8_EEPROM_MAGIC);
+	}
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	int rc;
+	struct var_imx8_eeprom_info *info;
+
+	info = malloc(sizeof(struct var_imx8_eeprom_info));
+	if (!info)
+		return -ENOMEM;
+
+	rc = var_read_som_eeprom(info);
+	if (rc)
+		return rc;
+
+	display_som_infos(info);
+
+#if defined(CONFIG_BOARD_TYPES)
+	gd->board_type = info->features;
+#endif /* CONFIG_BOARD_TYPES */
+
+	return 0;
+}
+
+#endif /* CONFIG_DISPLAY_BOARDINFO */
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index 1b4f94c124..f8bbdb6935 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -29,6 +29,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb"
+CONFIG_BOARD_TYPES=y
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-- 
2.30.2

[PATCH v2 2/5] imx8mn-var-som: fix non-applied PHY reset-gpios properties

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Select DM_ETH_PHY so that the reset-gpios property of the ethphy node
can be used.

Also select DM_PCA953X, which is needed for resetting the
ethernet PHY on the carrier board via the PCA9534 I/O expander.

Commit 4e5114daf9eb ("imx8mn: synchronise device tree with linux") did
synchronise device tree with linux, which in effect removed obsolete
PHY reset properties and replaced them with new mdio DM
properties. But the commit didn't activate DM_ETH_PHY or DM_PCA953X.

Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux")

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 arch/arm/mach-imx/imx8m/Kconfig  | 1 +
 configs/imx8mn_var_som_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 3450399d6f..a940d8a950 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -247,6 +247,7 @@ config TARGET_IMX8MN_VAR_SOM
 	select IMX8M_DDR4
 	select MISC
 	select I2C_EEPROM
+	select DM_ETH_PHY
 
 config TARGET_KONTRON_PITX_IMX8M
 	bool "Support Kontron pITX-imx8m"
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index f8bbdb6935..f0e232081f 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -77,6 +77,7 @@ CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_UUU_SUPPORT=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=2
 CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
-- 
2.30.2

[PATCH v2 3/5] arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

While testing the ethernet interface on a Variscite symphony carrier
board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware
configuration), the ethernet PHY is not detected.

The ADIN1300 datasheet indicate that the "Management interface
active (t4)" state is reached at most 5ms after the reset signal is
deasserted.

The device tree in Variscite custom git repository uses the following
property:

    phy-reset-post-delay = <20>;

Add a new MDIO property 'reset-deassert-us' of 20ms to have the same
delay inside the ethphy node. Adding this property fixes the problem
with the PHY detection.

Note that this SOM can also have an Atheros AR8033 PHY. In this case,
a 1ms deassert delay is sufficient. Add a comment to that effect.

Fixes: c4c1ed68c1e8 ("imx8mn_var_som: Add support for Variscite
VAR-SOM-MX8M-NANO board")

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 arch/arm/dts/imx8mn-var-som.dtsi | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index dea9eff3f0..4eb578a03f 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -102,11 +102,17 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethphy: ethernet-phy@4 {
+		ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <4>;
 			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <10000>;
+			/*
+			 * Deassert delay:
+			 * ADIN1300 requires 5ms.
+			 * AR8033   requires 1ms.
+			 */
+			reset-deassert-us = <20000>;
 		};
 	};
 };
-- 
2.30.2

[PATCH v2 4/5] imx8mn-var-som: read eth MAC address from EEPROM

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Read ethernet MAC address from EEPROM located on the SOM.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 13 +++++++++++++
 arch/arm/mach-imx/imx8m/Kconfig                  |  1 +
 2 files changed, 14 insertions(+)

diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index 7272fc2b4c..e0caf3179e 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -13,6 +13,19 @@
 	bootph-pre-ram;
 };
 
+&eeprom_som {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	eth_mac_address: eth-mac-address@19 {
+		reg = <0x19 0x06>;
+	};
+};
+
+&fec1 {
+	nvmem-cells = <&eth_mac_address>;
+	nvmem-cell-names = "mac-address";
+};
+
 &gpio1 {
 	bootph-pre-ram;
 };
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index a940d8a950..67db3e46ec 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -248,6 +248,7 @@ config TARGET_IMX8MN_VAR_SOM
 	select MISC
 	select I2C_EEPROM
 	select DM_ETH_PHY
+	select NVMEM
 
 config TARGET_KONTRON_PITX_IMX8M
 	bool "Support Kontron pITX-imx8m"
-- 
2.30.2

[PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.

For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.

The hardware configuration (EC) is determined at runtime by
reading from the SOM EEPROM.

To support both hardware configurations (EC and non-EC), adjust/fix
the PHY reset gpios according to the hardware configuration
read at runtime from the SOM EEPROM. This adjustement is done in
U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 arch/arm/dts/imx8mn-var-som-symphony.dts      |  4 -
 .../variscite/imx8mn_var_som/imx8mn_var_som.c | 80 +++++++++++++++++++
 configs/imx8mn_var_som_defconfig              |  2 +
 3 files changed, 82 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts b/arch/arm/dts/imx8mn-var-som-symphony.dts
index 3ed7021a48..5c8e4e8175 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony.dts
+++ b/arch/arm/dts/imx8mn-var-som-symphony.dts
@@ -56,10 +56,6 @@
 	};
 };
 
-&ethphy {
-	reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
-};
-
 &i2c2 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index a89457e8f5..61b9455a8f 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -14,6 +14,7 @@
 #include <malloc.h>
 #include <asm/io.h>
 #include <asm/global_data.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <linux/libfdt.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -161,4 +162,83 @@ int checkboard(void)
 
 #endif /* CONFIG_DISPLAY_BOARDINFO */
 
+static int insert_gpios_prop(void *blob, int node, const char *prop,
+			     unsigned int phandle, u32 gpio, u32 flags)
+{
+	fdt32_t val[3] = { cpu_to_fdt32(phandle), cpu_to_fdt32(gpio),
+			   cpu_to_fdt32(flags) };
+	return fdt_setprop(blob, node, prop, &val, sizeof(val));
+}
+
+static int configure_phy_reset_gpios(void *blob)
+{
+	int node;
+	int phynode;
+	int ret;
+	u32 handle;
+	u32 gpio;
+	u32 flags;
+	char path[1024];
+	const char *eth_alias = "ethernet0";
+
+	snprintf(path, sizeof(path), "%s/mdio/ethernet-phy@4",
+		 fdt_get_alias(blob, eth_alias));
+
+	phynode = fdt_path_offset(blob, path);
+	if (phynode < 0) {
+		pr_err("%s(): unable to locate PHY node: %s\n", __func__, path);
+		return 0;
+	}
+
+	if (gd_board_type() & VAR_EEPROM_F_ETH) {
+		snprintf(path, sizeof(path), "%s",
+			 fdt_get_alias(blob, "gpio0")); /* Alias to gpio1 */
+		gpio = 9;
+		flags = GPIO_ACTIVE_LOW;
+	} else {
+		snprintf(path, sizeof(path), "%s/gpio@20",
+			 fdt_get_alias(blob, "i2c1")); /* Alias to i2c2 */
+		gpio = 5;
+		flags = GPIO_ACTIVE_HIGH;
+	}
+
+	node = fdt_path_offset(blob, path);
+	if (node < 0) {
+		pr_err("%s(): unable to locate GPIO node: %s\n", __func__,
+		       path);
+		return 0;
+	}
+
+	handle = fdt_get_phandle(blob, node);
+	if (handle < 0) {
+		pr_err("%s(): unable to locate GPIO controller handle: %s\n",
+		       __func__, path);
+	}
+
+	ret = insert_gpios_prop(blob, phynode, "reset-gpios",
+				handle, gpio, flags);
+	if (ret < 0) {
+		pr_err("%s(): failed to set reset-gpios property\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+	/* Fix U-Boot device tree: */
+	return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_FIXUP */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/* Fix kernel device tree: */
+	return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
 #endif /* CONFIG_SPL_BUILD */
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index f0e232081f..d8a442d623 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -22,10 +22,12 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
 CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb"
-- 
2.30.2

[PATCH v2 3/5] arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay

[sbabic]

> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> While testing the ethernet interface on a Variscite symphony carrier
> board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware
> configuration), the ethernet PHY is not detected.
> The ADIN1300 datasheet indicate that the "Management interface
> active (t4)" state is reached at most 5ms after the reset signal is
> deasserted.
> The device tree in Variscite custom git repository uses the following
> property:
>     phy-reset-post-delay = <20>;
> Add a new MDIO property 'reset-deassert-us' of 20ms to have the same
> delay inside the ethphy node. Adding this property fixes the problem
> with the PHY detection.
> Note that this SOM can also have an Atheros AR8033 PHY. In this case,
> a 1ms deassert delay is sufficient. Add a comment to that effect.
> Fixes: c4c1ed68c1e8 ("imx8mn_var_som: Add support for Variscite
> VAR-SOM-MX8M-NANO board")
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH v2 2/5] imx8mn-var-som: fix non-applied PHY reset-gpios properties

[sbabic]

> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> Select DM_ETH_PHY so that the reset-gpios property of the ethphy node
> can be used.
> Also select DM_PCA953X, which is needed for resetting the
> ethernet PHY on the carrier board via the PCA9534 I/O expander.
> Commit 4e5114daf9eb ("imx8mn: synchronise device tree with linux") did
> synchronise device tree with linux, which in effect removed obsolete
> PHY reset properties and replaced them with new mdio DM
> properties. But the commit didn't activate DM_ETH_PHY or DM_PCA953X.
> Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux")
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH v2 4/5] imx8mn-var-som: read eth MAC address from EEPROM

[sbabic]

> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> Read ethernet MAC address from EEPROM located on the SOM.
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH v2 1/5] imx8mn-var-som: read and print SoM infos from eeprom on startup

[sbabic]

> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> Enable support to read and display configuration/manufacturing infos
> from 4Kbit EEPROM located on SOM board.
> Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch.
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

[sbabic]

> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> For SOM with the EC configuration, the ethernet PHY is located on the
> SOM itself, and connected to the CPU ethernet controller. It has a
> reset line controlled via GPIO1_IO9. In this configuration, the PHY
> located on the carrier board is not connected to anything and is
> therefore not used.
> For SOM without EC configuration, the ethernet PHY on the carrier
> board is connected to the CPU ethernet controller. It has a reset line
> controlled via the GPIO expander PCA9534_IO5.
> The hardware configuration (EC) is determined at runtime by
> reading from the SOM EEPROM.
> To support both hardware configurations (EC and non-EC), adjust/fix
> the PHY reset gpios according to the hardware configuration
> read at runtime from the SOM EEPROM. This adjustement is done in
> U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

[sbabic]

> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> For SOM with the EC configuration, the ethernet PHY is located on the
> SOM itself, and connected to the CPU ethernet controller. It has a
> reset line controlled via GPIO1_IO9. In this configuration, the PHY
> located on the carrier board is not connected to anything and is
> therefore not used.
> For SOM without EC configuration, the ethernet PHY on the carrier
> board is connected to the CPU ethernet controller. It has a reset line
> controlled via the GPIO expander PCA9534_IO5.
> The hardware configuration (EC) is determined at runtime by
> reading from the SOM EEPROM.
> To support both hardware configurations (EC and non-EC), adjust/fix
> the PHY reset gpios according to the hardware configuration
> read at runtime from the SOM EEPROM. This adjustement is done in
> U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================