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Wed, 12 Jul 2023 15:41:14 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.68]) by mail.m-online.net (Postfix) with ESMTP id 4R1JmV0Yt6z1qqlS; Wed, 12 Jul 2023 15:41:14 +0200 (CEST) X-Amavis-Alert: BAD HEADER SECTION, Missing required header field: "Date" Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.68]) (amavis, port 10024) with ESMTP id oZ8OmgggHCnJ; Wed, 12 Jul 2023 15:41:12 +0200 (CEST) Received: from papero (host-88-217-136-221.customer.m-online.net [88.217.136.221]) by mail.mnet-online.de (Postfix) with ESMTP; Wed, 12 Jul 2023 15:41:12 +0200 (CEST) From: sbabic@denx.de X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 1787985 X-Patchwork-Delegate: sbabic@denx.de To: Adam Ford ,u-boot@lists.denx.de Subject: [PATCH 2/2] arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4 In-reply-to: <20230530224558.9340-2-aford173@gmail.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Message-Id: <20230712134117.7BF5886A9D@phobos.denx.de> Date: Wed, 12 Jul 2023 15:41:14 +0200 (CEST) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean > Several changes have been made to the device tree > in the kernel, so update that as well as the > corresponding imx8mp-u-boot.dtsi files to prevent > breaking the booting. > Signed-off-by: Adam Ford > Reviewed-by: Fabio Estevam > diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.d= tsi > index 18d1728e1d..dfb747bb02 100644 > --- a/arch/arm/dts/imx8mp-u-boot.dtsi > +++ b/arch/arm/dts/imx8mp-u-boot.dtsi > @@ -44,6 +44,9 @@ > =20 > &aips3 { > bootph-pre-ram; > + spba-bus@30800000 { > + bootph-pre-ram; > + }; > }; > =20 > &iomuxc { > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi > index bb916a0948..428c60462e 100644 > --- a/arch/arm/dts/imx8mp.dtsi > +++ b/arch/arm/dts/imx8mp.dtsi > @@ -123,6 +123,7 @@ > =20 > A53_L2: l2-cache0 { > compatible =3D "cache"; > + cache-unified; > cache-level =3D <2>; > cache-size =3D <0x80000>; > cache-line-size =3D <64>; > @@ -379,6 +380,8 @@ > compatible =3D "fsl,imx8mp-tmu"; > reg =3D <0x30260000 0x10000>; > clocks =3D <&clk IMX8MP_CLK_TSENSOR_ROOT>; > + nvmem-cells =3D <&tmu_calib>; > + nvmem-cell-names =3D "calib"; > #thermal-sensor-cells =3D <1>; > }; > =20 > @@ -406,12 +409,36 @@ > status =3D "disabled"; > }; > =20 > + gpt1: timer@302d0000 { > + compatible =3D "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; > + reg =3D <0x302d0000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; > + clock-names =3D "ipg", "per"; > + }; > + > + gpt2: timer@302e0000 { > + compatible =3D "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; > + reg =3D <0x302e0000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; > + clock-names =3D "ipg", "per"; > + }; > + > + gpt3: timer@302f0000 { > + compatible =3D "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; > + reg =3D <0x302f0000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; > + clock-names =3D "ipg", "per"; > + }; > + > iomuxc: pinctrl@30330000 { > compatible =3D "fsl,imx8mp-iomuxc"; > reg =3D <0x30330000 0x10000>; > }; > =20 > - gpr: iomuxc-gpr@30340000 { > + gpr: syscon@30340000 { > compatible =3D "fsl,imx8mp-iomuxc-gpr", "syscon"; > reg =3D <0x30340000 0x10000>; > }; > @@ -424,27 +451,44 @@ > #address-cells =3D <1>; > #size-cells =3D <1>; > =20 > - imx8mp_uid: unique-id@420 { > + /* > + * The register address below maps to the MX8M > + * Fusemap Description Table entries this way. > + * Assuming > + * reg =3D ; > + * then > + * Fuse Address =3D (ADDR * 4) + 0x400 > + * Note that if SIZE is greater than 4, then > + * each subsequent fuse is located at offset > + * +0x10 in Fusemap Description Table (e.g. > + * reg =3D <0x8 0x8> describes fuses 0x420 and > + * 0x430). > + */ > + imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ > reg =3D <0x8 0x8>; > }; > =20 > - cpu_speed_grade: speed-grade@10 { > + cpu_speed_grade: speed-grade@10 { /* 0x440 */ > reg =3D <0x10 4>; > }; > =20 > - eth_mac1: mac-address@90 { > + eth_mac1: mac-address@90 { /* 0x640 */ > reg =3D <0x90 6>; > }; > =20 > - eth_mac2: mac-address@96 { > + eth_mac2: mac-address@96 { /* 0x658 */ > reg =3D <0x96 6>; > }; > + > + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ > + reg =3D <0x264 0x10>; > + }; > }; > =20 > - anatop: anatop@30360000 { > - compatible =3D "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", > - "syscon"; > + anatop: clock-controller@30360000 { > + compatible =3D "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; > reg =3D <0x30360000 0x10000>; > + #clock-cells =3D <1>; > }; > =20 > snvs: snvs@30370000 { > @@ -523,6 +567,7 @@ > compatible =3D "fsl,imx8mp-gpc"; > reg =3D <0x303a0000 0x1000>; > interrupt-parent =3D <&gic>; > + interrupts =3D ; > interrupt-controller; > #interrupt-cells =3D <3>; > =20 > @@ -589,7 +634,7 @@ > reg =3D ; > }; > =20 > - pgc_hsiomix: power-domains@17 { > + pgc_hsiomix: power-domain@17 { > #power-domain-cells =3D <0>; > reg =3D ; > clocks =3D <&clk IMX8MP_CLK_HSIO_AXI>, > @@ -631,6 +676,14 @@ > reg =3D ; > clocks =3D <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; > }; > + > + pgc_mlmix: power-domain@24 { > + #power-domain-cells =3D <0>; > + reg =3D ; > + clocks =3D <&clk IMX8MP_CLK_ML_AXI>, > + <&clk IMX8MP_CLK_ML_AHB>, > + <&clk IMX8MP_CLK_NPU_ROOT>; > + }; > }; > }; > }; > @@ -693,6 +746,30 @@ > clocks =3D <&osc_24m>; > clock-names =3D "per"; > }; > + > + gpt6: timer@306e0000 { > + compatible =3D "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; > + reg =3D <0x306e0000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; > + clock-names =3D "ipg", "per"; > + }; > + > + gpt5: timer@306f0000 { > + compatible =3D "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; > + reg =3D <0x306f0000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; > + clock-names =3D "ipg", "per"; > + }; > + > + gpt4: timer@30700000 { > + compatible =3D "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; > + reg =3D <0x30700000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; > + clock-names =3D "ipg", "per"; > + }; > }; > =20 > aips3: bus@30800000 { > @@ -702,112 +779,129 @@ > #size-cells =3D <1>; > ranges; > =20 > - ecspi1: spi@30820000 { > + spba-bus@30800000 { > + compatible =3D "fsl,spba-bus", "simple-bus"; > + reg =3D <0x30800000 0x100000>; > #address-cells =3D <1>; > - #size-cells =3D <0>; > - compatible =3D "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; > - reg =3D <0x30820000 0x10000>; > - interrupts =3D ; > - clocks =3D <&clk IMX8MP_CLK_ECSPI1_ROOT>, > - <&clk IMX8MP_CLK_ECSPI1_ROOT>; > - clock-names =3D "ipg", "per"; > - dmas =3D <&sdma1 0 7 1>, <&sdma1 1 7 2>; > - dma-names =3D "rx", "tx"; > - status =3D "disabled"; > - }; > + #size-cells =3D <1>; > + ranges; > =20 > - ecspi2: spi@30830000 { > - #address-cells =3D <1>; > - #size-cells =3D <0>; > - compatible =3D "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; > - reg =3D <0x30830000 0x10000>; > - interrupts =3D ; > - clocks =3D <&clk IMX8MP_CLK_ECSPI2_ROOT>, > - <&clk IMX8MP_CLK_ECSPI2_ROOT>; > - clock-names =3D "ipg", "per"; > - dmas =3D <&sdma1 2 7 1>, <&sdma1 3 7 2>; > - dma-names =3D "rx", "tx"; > - status =3D "disabled"; > - }; > + ecspi1: spi@30820000 { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + compatible =3D "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; > + reg =3D <0x30820000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_ECSPI1_ROOT>, > + <&clk IMX8MP_CLK_ECSPI1_ROOT>; > + clock-names =3D "ipg", "per"; > + assigned-clock-rates =3D <80000000>; > + assigned-clocks =3D <&clk IMX8MP_CLK_ECSPI1>; > + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_800M>; > + dmas =3D <&sdma1 0 7 1>, <&sdma1 1 7 2>; > + dma-names =3D "rx", "tx"; > + status =3D "disabled"; > + }; > =20 > - ecspi3: spi@30840000 { > - #address-cells =3D <1>; > - #size-cells =3D <0>; > - compatible =3D "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; > - reg =3D <0x30840000 0x10000>; > - interrupts =3D ; > - clocks =3D <&clk IMX8MP_CLK_ECSPI3_ROOT>, > - <&clk IMX8MP_CLK_ECSPI3_ROOT>; > - clock-names =3D "ipg", "per"; > - dmas =3D <&sdma1 4 7 1>, <&sdma1 5 7 2>; > - dma-names =3D "rx", "tx"; > - status =3D "disabled"; > - }; > + ecspi2: spi@30830000 { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + compatible =3D "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; > + reg =3D <0x30830000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_ECSPI2_ROOT>, > + <&clk IMX8MP_CLK_ECSPI2_ROOT>; > + clock-names =3D "ipg", "per"; > + assigned-clock-rates =3D <80000000>; > + assigned-clocks =3D <&clk IMX8MP_CLK_ECSPI2>; > + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_800M>; > + dmas =3D <&sdma1 2 7 1>, <&sdma1 3 7 2>; > + dma-names =3D "rx", "tx"; > + status =3D "disabled"; > + }; > =20 > - uart1: serial@30860000 { > - compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; > - reg =3D <0x30860000 0x10000>; > - interrupts =3D ; > - clocks =3D <&clk IMX8MP_CLK_UART1_ROOT>, > - <&clk IMX8MP_CLK_UART1_ROOT>; > - clock-names =3D "ipg", "per"; > - dmas =3D <&sdma1 22 4 0>, <&sdma1 23 4 0>; > - dma-names =3D "rx", "tx"; > - status =3D "disabled"; > - }; > + ecspi3: spi@30840000 { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + compatible =3D "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; > + reg =3D <0x30840000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_ECSPI3_ROOT>, > + <&clk IMX8MP_CLK_ECSPI3_ROOT>; > + clock-names =3D "ipg", "per"; > + assigned-clock-rates =3D <80000000>; > + assigned-clocks =3D <&clk IMX8MP_CLK_ECSPI3>; > + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_800M>; > + dmas =3D <&sdma1 4 7 1>, <&sdma1 5 7 2>; > + dma-names =3D "rx", "tx"; > + status =3D "disabled"; > + }; > =20 > - uart3: serial@30880000 { > - compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; > - reg =3D <0x30880000 0x10000>; > - interrupts =3D ; > - clocks =3D <&clk IMX8MP_CLK_UART3_ROOT>, > - <&clk IMX8MP_CLK_UART3_ROOT>; > - clock-names =3D "ipg", "per"; > - dmas =3D <&sdma1 26 4 0>, <&sdma1 27 4 0>; > - dma-names =3D "rx", "tx"; > - status =3D "disabled"; > - }; > + uart1: serial@30860000 { > + compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; > + reg =3D <0x30860000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_UART1_ROOT>, > + <&clk IMX8MP_CLK_UART1_ROOT>; > + clock-names =3D "ipg", "per"; > + dmas =3D <&sdma1 22 4 0>, <&sdma1 23 4 0>; > + dma-names =3D "rx", "tx"; > + status =3D "disabled"; > + }; > =20 > - uart2: serial@30890000 { > - compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; > - reg =3D <0x30890000 0x10000>; > - interrupts =3D ; > - clocks =3D <&clk IMX8MP_CLK_UART2_ROOT>, > - <&clk IMX8MP_CLK_UART2_ROOT>; > - clock-names =3D "ipg", "per"; > - dmas =3D <&sdma1 24 4 0>, <&sdma1 25 4 0>; > - dma-names =3D "rx", "tx"; > - status =3D "disabled"; > - }; > + uart3: serial@30880000 { > + compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; > + reg =3D <0x30880000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_UART3_ROOT>, > + <&clk IMX8MP_CLK_UART3_ROOT>; > + clock-names =3D "ipg", "per"; > + dmas =3D <&sdma1 26 4 0>, <&sdma1 27 4 0>; > + dma-names =3D "rx", "tx"; > + status =3D "disabled"; > + }; > =20 > - flexcan1: can@308c0000 { > - compatible =3D "fsl,imx8mp-flexcan"; > - reg =3D <0x308c0000 0x10000>; > - interrupts =3D ; > - clocks =3D <&clk IMX8MP_CLK_IPG_ROOT>, > - <&clk IMX8MP_CLK_CAN1_ROOT>; > - clock-names =3D "ipg", "per"; > - assigned-clocks =3D <&clk IMX8MP_CLK_CAN1>; > - assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_40M>; > - assigned-clock-rates =3D <40000000>; > - fsl,clk-source =3D /bits/ 8 <0>; > - fsl,stop-mode =3D <&gpr 0x10 4>; > - status =3D "disabled"; > - }; > + uart2: serial@30890000 { > + compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; > + reg =3D <0x30890000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_UART2_ROOT>, > + <&clk IMX8MP_CLK_UART2_ROOT>; > + clock-names =3D "ipg", "per"; > + dmas =3D <&sdma1 24 4 0>, <&sdma1 25 4 0>; > + dma-names =3D "rx", "tx"; > + status =3D "disabled"; > + }; > =20 > - flexcan2: can@308d0000 { > - compatible =3D "fsl,imx8mp-flexcan"; > - reg =3D <0x308d0000 0x10000>; > - interrupts =3D ; > - clocks =3D <&clk IMX8MP_CLK_IPG_ROOT>, > - <&clk IMX8MP_CLK_CAN2_ROOT>; > - clock-names =3D "ipg", "per"; > - assigned-clocks =3D <&clk IMX8MP_CLK_CAN2>; > - assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_40M>; > - assigned-clock-rates =3D <40000000>; > - fsl,clk-source =3D /bits/ 8 <0>; > - fsl,stop-mode =3D <&gpr 0x10 5>; > - status =3D "disabled"; > + flexcan1: can@308c0000 { > + compatible =3D "fsl,imx8mp-flexcan"; > + reg =3D <0x308c0000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_IPG_ROOT>, > + <&clk IMX8MP_CLK_CAN1_ROOT>; > + clock-names =3D "ipg", "per"; > + assigned-clocks =3D <&clk IMX8MP_CLK_CAN1>; > + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_40M>; > + assigned-clock-rates =3D <40000000>; > + fsl,clk-source =3D /bits/ 8 <0>; > + fsl,stop-mode =3D <&gpr 0x10 4>; > + status =3D "disabled"; > + }; > + > + flexcan2: can@308d0000 { > + compatible =3D "fsl,imx8mp-flexcan"; > + reg =3D <0x308d0000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_IPG_ROOT>, > + <&clk IMX8MP_CLK_CAN2_ROOT>; > + clock-names =3D "ipg", "per"; > + assigned-clocks =3D <&clk IMX8MP_CLK_CAN2>; > + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_40M>; > + assigned-clock-rates =3D <40000000>; > + fsl,clk-source =3D /bits/ 8 <0>; > + fsl,stop-mode =3D <&gpr 0x10 5>; > + status =3D "disabled"; > + }; > }; > =20 > crypto: crypto@30900000 { > @@ -1063,11 +1157,11 @@ > noc_opp_table: opp-table { > compatible =3D "operating-points-v2"; > =20 > - opp-200M { > + opp-200000000 { > opp-hz =3D /bits/ 64 <200000000>; > }; > =20 > - opp-1000M { > + opp-1000000000 { > opp-hz =3D /bits/ 64 <1000000000>; > }; > }; > @@ -1080,10 +1174,78 @@ > #size-cells =3D <1>; > ranges; > =20 > + mipi_dsi: dsi@32e60000 { > + compatible =3D "fsl,imx8mp-mipi-dsim"; > + reg =3D <0x32e60000 0x400>; > + clocks =3D <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; > + clock-names =3D "bus_clk", "sclk_mipi"; > + assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_APB>, > + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; > + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_800M>, > + <&clk IMX8MP_CLK_24M>; > + assigned-clock-rates =3D <200000000>, <24000000>; > + samsung,pll-clock-frequency =3D <24000000>; > + interrupts =3D ; > + power-domains =3D <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; > + status =3D "disabled"; > + > + ports { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + port@0 { > + reg =3D <0>; > + > + dsim_from_lcdif1: endpoint { > + remote-endpoint =3D <&lcdif1_to_dsim>; > + }; > + }; > + }; > + }; > + > + lcdif1: display-controller@32e80000 { > + compatible =3D "fsl,imx8mp-lcdif"; > + reg =3D <0x32e80000 0x10000>; > + clocks =3D <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; > + clock-names =3D "pix", "axi", "disp_axi"; > + interrupts =3D ; > + power-domains =3D <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; > + status =3D "disabled"; > + > + port { > + lcdif1_to_dsim: endpoint { > + remote-endpoint =3D <&dsim_from_lcdif1>; > + }; > + }; > + }; > + > + lcdif2: display-controller@32e90000 { > + compatible =3D "fsl,imx8mp-lcdif"; > + reg =3D <0x32e90000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; > + clock-names =3D "pix", "axi", "disp_axi"; > + power-domains =3D <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; > + status =3D "disabled"; > + > + port { > + lcdif2_to_ldb: endpoint { > + remote-endpoint =3D <&ldb_from_lcdif2>; > + }; > + }; > + }; > + > media_blk_ctrl: blk-ctrl@32ec0000 { > compatible =3D "fsl,imx8mp-media-blk-ctrl", > "syscon"; > reg =3D <0x32ec0000 0x10000>; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > power-domains =3D <&pgc_mediamix>, > <&pgc_mipi_phy1>, > <&pgc_mipi_phy1>, > @@ -1122,12 +1284,55 @@ > "disp1", "disp2", "isp", "phy"; > =20 > assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_AXI>, > - <&clk IMX8MP_CLK_MEDIA_APB>; > + <&clk IMX8MP_CLK_MEDIA_APB>, > + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, > + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, > + <&clk IMX8MP_VIDEO_PLL1>; > assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL2_1000M>, > - <&clk IMX8MP_SYS_PLL1_800M>; > - assigned-clock-rates =3D <500000000>, <200000000>; > - > + <&clk IMX8MP_SYS_PLL1_800M>, > + <&clk IMX8MP_VIDEO_PLL1_OUT>, > + <&clk IMX8MP_VIDEO_PLL1_OUT>; > + assigned-clock-rates =3D <500000000>, <200000000>, > + <0>, <0>, <1039500000>; > #power-domain-cells =3D <1>; > + > + lvds_bridge: bridge@5c { > + compatible =3D "fsl,imx8mp-ldb"; > + reg =3D <0x5c 0x4>, <0x128 0x4>; > + reg-names =3D "ldb", "lvds"; > + clocks =3D <&clk IMX8MP_CLK_MEDIA_LDB>; > + clock-names =3D "ldb"; > + assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_LDB>; > + assigned-clock-parents =3D <&clk IMX8MP_VIDEO_PLL1_OUT>; > + status =3D "disabled"; > + > + ports { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + port@0 { > + reg =3D <0>; > + > + ldb_from_lcdif2: endpoint { > + remote-endpoint =3D <&lcdif2_to_ldb>; > + }; > + }; > + > + port@1 { > + reg =3D <1>; > + > + ldb_lvds_ch0: endpoint { > + }; > + }; > + > + port@2 { > + reg =3D <2>; > + > + ldb_lvds_ch1: endpoint { > + }; > + }; > + }; > + }; > }; > =20 > pcie_phy: pcie-phy@32f00000 { > @@ -1158,6 +1363,7 @@ > <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; > interconnect-names =3D "noc-pcie", "usb1", "usb2", "pcie"; > #power-domain-cells =3D <1>; > + #clock-cells =3D <0>; > }; > }; > =20 > @@ -1165,6 +1371,13 @@ > compatible =3D "fsl,imx8mp-pcie"; > reg =3D <0x33800000 0x400000>, <0x1ff00000 0x80000>; > reg-names =3D "dbi", "config"; > + clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_HSIO_AXI>, > + <&clk IMX8MP_CLK_PCIE_ROOT>; > + clock-names =3D "pcie", "pcie_bus", "pcie_aux"; > + assigned-clocks =3D <&clk IMX8MP_CLK_PCIE_AUX>; > + assigned-clock-rates =3D <10000000>; > + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL2_50M>; > #address-cells =3D <3>; > #size-cells =3D <2>; > device_type =3D "pci"; > @@ -1192,6 +1405,32 @@ > status =3D "disabled"; > }; > =20 > + pcie_ep: pcie-ep@33800000 { > + compatible =3D "fsl,imx8mp-pcie-ep"; > + reg =3D <0x33800000 0x000400000>, <0x18000000 0x08000000>; > + reg-names =3D "dbi", "addr_space"; > + clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_HSIO_AXI>, > + <&clk IMX8MP_CLK_PCIE_ROOT>; > + clock-names =3D "pcie", "pcie_bus", "pcie_aux"; > + assigned-clocks =3D <&clk IMX8MP_CLK_PCIE_AUX>; > + assigned-clock-rates =3D <10000000>; > + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL2_50M>; > + num-lanes =3D <1>; > + interrupts =3D ; /* eDMA */ > + interrupt-names =3D "dma"; > + fsl,max-link-speed =3D <3>; > + power-domains =3D <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; > + resets =3D <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, > + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; > + reset-names =3D "apps", "turnoff"; > + phys =3D <&pcie_phy>; > + phy-names =3D "pcie-phy"; > + num-ib-windows =3D <4>; > + num-ob-windows =3D <4>; > + status =3D "disabled"; > + }; > + > gpu3d: gpu@38000000 { > compatible =3D "vivante,gc"; > reg =3D <0x38000000 0x8000>; > @@ -1223,6 +1462,28 @@ > power-domains =3D <&pgc_gpu2d>; > }; > =20 > + vpu_g1: video-codec@38300000 { > + compatible =3D "nxp,imx8mm-vpu-g1"; > + reg =3D <0x38300000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_VPU_G1_ROOT>; > + assigned-clocks =3D <&clk IMX8MP_CLK_VPU_G1>; > + assigned-clock-parents =3D <&clk IMX8MP_VPU_PLL_OUT>; > + assigned-clock-rates =3D <600000000>; > + power-domains =3D <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; > + }; > + > + vpu_g2: video-codec@38310000 { > + compatible =3D "nxp,imx8mq-vpu-g2"; > + reg =3D <0x38310000 0x10000>; > + interrupts =3D ; > + clocks =3D <&clk IMX8MP_CLK_VPU_G2_ROOT>; > + assigned-clocks =3D <&clk IMX8MP_CLK_VPU_G2>; > + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL2_1000M>; > + assigned-clock-rates =3D <500000000>; > + power-domains =3D <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; > + }; > + > vpumix_blk_ctrl: blk-ctrl@38330000 { > compatible =3D "fsl,imx8mp-vpu-blk-ctrl", "syscon"; > reg =3D <0x38330000 0x100>; > @@ -1234,6 +1495,9 @@ > <&clk IMX8MP_CLK_VPU_G2_ROOT>, > <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; > clock-names =3D "g1", "g2", "vc8000e"; > + assigned-clocks =3D <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; > + assigned-clock-parents =3D <&clk IMX8MP_VPU_PLL_OUT>; > + assigned-clock-rates =3D <600000000>, <600000000>; > interconnects =3D <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, > <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, > <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; > @@ -1279,7 +1543,7 @@ > reg =3D <0x32f10100 0x8>, > <0x381f0000 0x20>; > clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, > - <&clk IMX8MP_CLK_USB_ROOT>; > + <&clk IMX8MP_CLK_USB_SUSP>; > clock-names =3D "hsio", "suspend"; > interrupts =3D ; > power-domains =3D <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; > @@ -1292,9 +1556,9 @@ > usb_dwc3_0: usb@38100000 { > compatible =3D "snps,dwc3"; > reg =3D <0x38100000 0x10000>; > - clocks =3D <&clk IMX8MP_CLK_HSIO_AXI>, > + clocks =3D <&clk IMX8MP_CLK_USB_ROOT>, > <&clk IMX8MP_CLK_USB_CORE_REF>, > - <&clk IMX8MP_CLK_USB_ROOT>; > + <&clk IMX8MP_CLK_USB_SUSP>; > clock-names =3D "bus_early", "ref", "suspend"; > interrupts =3D ; > phys =3D <&usb3_phy0>, <&usb3_phy0>; > @@ -1321,7 +1585,7 @@ > reg =3D <0x32f10108 0x8>, > <0x382f0000 0x20>; > clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, > - <&clk IMX8MP_CLK_USB_ROOT>; > + <&clk IMX8MP_CLK_USB_SUSP>; > clock-names =3D "hsio", "suspend"; > interrupts =3D ; > power-domains =3D <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; > @@ -1334,9 +1598,9 @@ > usb_dwc3_1: usb@38200000 { > compatible =3D "snps,dwc3"; > reg =3D <0x38200000 0x10000>; > - clocks =3D <&clk IMX8MP_CLK_HSIO_AXI>, > + clocks =3D <&clk IMX8MP_CLK_USB_ROOT>, > <&clk IMX8MP_CLK_USB_CORE_REF>, > - <&clk IMX8MP_CLK_USB_ROOT>; > + <&clk IMX8MP_CLK_USB_SUSP>; > clock-names =3D "bus_early", "ref", "suspend"; > interrupts =3D ; > phys =3D <&usb3_phy1>, <&usb3_phy1>; Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic --=20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D DENX Software Engineering GmbH, Managing Director: Erika Unter =20 HRB 165235 Munich, Office: Kirchenstr.5, 82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D