From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC229EB64DC for ; Mon, 17 Jul 2023 22:15:46 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0A57686684; Tue, 18 Jul 2023 00:15:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="MQJ2R7Fc"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1200D8469C; Tue, 18 Jul 2023 00:15:43 +0200 (CEST) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A86378666F for ; Tue, 18 Jul 2023 00:15:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bb@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 36HMFcY0127817; Mon, 17 Jul 2023 17:15:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1689632138; bh=puvFC85Az1WVTNsJOzD0x8THXMDsyex9JhcWx2McgNQ=; h=From:To:CC:Subject:Date; b=MQJ2R7FcYMepKVs+Ls0m7nwNvL0+mUv9mZyOtoAYSlfvPPdti/R1HRK6cdi9M2JFq 1UWEOXJmrEO5kUHIjZr7giDuVrdlVY/5ZZoNXy+qNcRhlMJQy8NYfciU9et/gkVwqn 3qP/3MeUo4aARh85OY1VSu+gqXXWT0R2O46lJ6DY= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 36HMFc9U021678 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 17 Jul 2023 17:15:38 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 17 Jul 2023 17:15:38 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 17 Jul 2023 17:15:37 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36HMFcEp031059; Mon, 17 Jul 2023 17:15:38 -0500 From: Bryan Brattlof To: Tom Rini CC: Praneeth Bajjuri , Vignesh Raghavendra , Udit Kumar , UBoot Mailing List , Bryan Brattlof Subject: [PATCH] ram: k3-ddrss: do not touch ctrl regs during training Date: Mon, 17 Jul 2023 17:15:26 -0500 Message-ID: <20230717221525.3693897-2-bb@ti.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2052; i=bb@ti.com; h=from:subject; bh=M3iHA8vLYUCBaFX91nQi3mKhbJNazdNdD1GlwQbcAV0=; b=owNCWmg5MUFZJlNZYwtKgwAAZf///vf9t/st69nU/P3Tft+v9/3yblxsncsL91ye9p/p/f6wA RmZo7UAABo0A0AGmmQAD1MgaaaAaBiMJiAAAAMjT1GhoMmgB5T0yRkPUwjaIGhpiAxGhkAaGgaa GmRoyADQGjTQBoaPRqZMGoAGh6mmmCaGmjTI0DBGQyAMITQ9T1D0g2oNPUD1AHqGmIxGgAAAADR oD1NAHqDQAAAAAD0gDQMm1PKIkS8OhFRrr5wdxBSifOFRw7DyfGYmylSAHHdoFKEWYop6+/IatF 4rmK0eQftTGkXBwfE+pRzC1RBWOw7uM2b7wFVlNDbfYPmXZPqxZwkCTvNddIEPGZ6hkJwbTDzia fK6Ry1as2k/Wfcm8XmdTsAPvAbFWiZ5V/wTUUmaY+eGGBeo0JrRd7OmpACjoYLB3z+J5cDuGqax g+b4XoRDNf0MXTlR7nwupse8GYy3+EILfhXDJuExSHXYIY2A03N6CeAWjxzaYaCtcv9cmneD7Bj /1QAx2cI9ONBKcoc+3LgFEEUeEijsws3tx/f4Wit9wYEmHTqaSqXrwRg3AG2C1AIMKXg8TpCI0l WldENU4LZZptiGRzcbhTz43PJn/LtEzL83yP1/y8Jx0fc3aPkAqzQwAzf48Esqu+jBfLOr2FlTE /L0XckU4UJBjC0qDA== X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof --- drivers/ram/k3-ddrss/k3-ddrss.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 7e445d2b737b3..b54557f02cce1 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -138,6 +138,7 @@ struct k3_ddrss_desc { u32 ddr_freq1; u32 ddr_freq2; u32 ddr_fhs_cnt; + u32 dram_class; struct udevice *vtt_supply; u32 instance; lpddr4_obj *driverdt; @@ -243,14 +244,11 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss) static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) { - u32 dram_class; struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance; debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); - dram_class = k3_lpddr4_read_ddr_type(pd); - - switch (dram_class) { + switch (ddrss->dram_class) { case DENALI_CTL_0_DRAM_CLASS_DDR4: break; case DENALI_CTL_0_DRAM_CLASS_LPDDR4: @@ -263,13 +261,12 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss) { - u32 dram_class; int ret; lpddr4_privatedata *pd = &ddrss->pd; - dram_class = k3_lpddr4_read_ddr_type(pd); + ddrss->dram_class = k3_lpddr4_read_ddr_type(pd); - switch (dram_class) { + switch (ddrss->dram_class) { case DENALI_CTL_0_DRAM_CLASS_DDR4: /* Set to ddr_freq1 from DT for DDR4 */ ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); base-commit: 13aa090b87a0fbdfe690011669b9fdb96bb1ccc7 -- 2.41.0