From: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
To: <u-boot@lists.denx.de>
Cc: <michal.simek@amd.com>, <lukma@denx.de>, <seanga2@gmail.com>,
<git@amd.com>, Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Subject: [PATCH] clk: zynqmp: Add set_rate support for gem rx and tsu clks
Date: Wed, 19 Jul 2023 02:49:12 -0600 [thread overview]
Message-ID: <20230719084912.30209-1-ashok.reddy.soma@amd.com> (raw)
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
---
drivers/clk/clk_zynqmp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index be0ee50e0e..27479391e1 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -718,6 +718,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
switch (id) {
case gem0_ref ... gem3_ref:
case gem0_tx ... gem3_tx:
+ case gem0_rx ... gem3_rx:
+ case gem_tsu:
case qspi_ref ... can1_ref:
case usb0_bus_ref ... usb3_dual_ref:
return zynqmp_clk_set_peripheral_rate(priv, id,
--
2.17.1
next reply other threads:[~2023-07-19 8:49 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-19 8:49 Ashok Reddy Soma [this message]
2023-07-21 7:01 ` [PATCH] clk: zynqmp: Add set_rate support for gem rx and tsu clks Michal Simek
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