From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01F37C001B0 for ; Sat, 22 Jul 2023 19:32:25 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C19EE865DA; Sat, 22 Jul 2023 21:32:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="fTYxZ7sp"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5A161865F0; Sat, 22 Jul 2023 21:32:10 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C7B67860AC for ; Sat, 22 Jul 2023 21:32:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rogerq@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6ECBD609AD; Sat, 22 Jul 2023 19:32:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31C31C433C9; Sat, 22 Jul 2023 19:32:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690054325; bh=5GJIk/Y2WivZIzvXwHfAGrkuWUDcpnnf8Iat78i24Ls=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fTYxZ7spnPVom/+Va4gpn4aiqSjGAmDG8dCeKpKq4pOcTKPRxquoaSWlZiJynhgm8 qwfV3oVmYxJuM+H+4ClssI/B7c/bFBSizNDYYmbQaVFBei6RXEV9IgRDkxSOgf/JCN FaY2SE9v4pYhPF0JqvLYvtti+l+mIUETmtvBVGqnh8u80SK/h/K1Vo2K1epdhUO4HA sOf6IHECNEmCQE6lHPdiIEiap0xJUOuiEsecMPscazVhcjSzO8PKez8Ca3BYLVbHmA vRDM7zOQx8gIGsmoAN+sQnrVKeg0Tlzijaxqgb0iwyVTaodKiOKE1Zb7djtizyJb62 oU3/MzrxCuXNA== From: Roger Quadros To: joe.hershberger@ni.com, nm@ti.com Cc: rfried.dev@gmail.com, r-gunasekaran@ti.com, s-vadapalli@ti.com, mripard@kernel.org, sjg@chromium.org, pbrobinson@gmail.com, srk@ti.com, u-boot@lists.denx.de, Roger Quadros Subject: [PATCH v2 2/4] net: ti: am65-cpsw-nuss: Get port mode register from standard "phys" property Date: Sat, 22 Jul 2023 22:31:49 +0300 Message-Id: <20230722193151.117345-3-rogerq@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230722193151.117345-1-rogerq@kernel.org> References: <20230722193151.117345-1-rogerq@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Approved DT binding has the port mode register in the "phys" property. Get it from there instead of the custom "cpsw-phy-sel" property. This will allow us to keep DT in sync with Linux. Signed-off-by: Roger Quadros --- drivers/net/ti/am65-cpsw-nuss.c | 63 +++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 26 deletions(-) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index ee46676ec8..ce52106e52 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -102,7 +102,6 @@ struct am65_cpsw_common { fdt_addr_t cpsw_base; fdt_addr_t mdio_base; fdt_addr_t ale_base; - fdt_addr_t gmii_sel; struct clk fclk; struct power_domain pwrdmn; @@ -232,18 +231,37 @@ out: #define AM65_GMII_SEL_RGMII_IDMODE BIT(4) -static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, - phy_interface_t phy_mode, int slave) +static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, + phy_interface_t phy_mode) { - struct am65_cpsw_common *common = priv->cpsw_common; - fdt_addr_t gmii_sel = common->gmii_sel + AM65_GMII_SEL_PORT_OFFS(slave); - u32 reg; - u32 mode = 0; + struct udevice *dev = priv->dev; + u32 offset, reg, phandle; bool rgmii_id = false; + fdt_addr_t gmii_sel; + u32 mode = 0; + ofnode node; + int ret; + + ret = ofnode_read_u32(dev_ofnode(dev), "phys", &phandle); + if (ret) + return ret; + + ret = ofnode_read_u32_index(dev_ofnode(dev), "phys", 1, &offset); + if (ret) + return ret; + + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) + return -ENODEV; + + gmii_sel = ofnode_get_addr(node); + if (gmii_sel == FDT_ADDR_T_NONE) + return -ENODEV; + gmii_sel += AM65_GMII_SEL_PORT_OFFS(offset); reg = readl(gmii_sel); - dev_dbg(common->dev, "old gmii_sel: %08x\n", reg); + dev_dbg(dev, "old gmii_sel: %08x\n", reg); switch (phy_mode) { case PHY_INTERFACE_MODE_RMII: @@ -262,7 +280,7 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, break; default: - dev_warn(common->dev, + dev_warn(dev, "Unsupported PHY mode: %u. Defaulting to MII.\n", phy_mode); /* fallthrough */ @@ -275,15 +293,19 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, mode |= AM65_GMII_SEL_RGMII_IDMODE; reg = mode; - dev_dbg(common->dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n", + dev_dbg(dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n", phy_mode, reg); writel(reg, gmii_sel); reg = readl(gmii_sel); - if (reg != mode) - dev_err(common->dev, + if (reg != mode) { + dev_err(dev, "gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n", mode, reg); + return 0; + } + + return 0; } static int am65_cpsw_start(struct udevice *dev) @@ -708,7 +730,9 @@ static int am65_cpsw_port_probe(struct udevice *dev) if (ret) goto out; - am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id); + ret = am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface); + if (ret) + goto out; ret = am65_cpsw_mdio_init(dev); if (ret) @@ -803,19 +827,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET; } - node = dev_read_subnode(dev, "cpsw-phy-sel"); - if (!ofnode_valid(node)) { - dev_err(dev, "can't find cpsw-phy-sel\n"); - ret = -ENOENT; - goto out; - } - - cpsw_common->gmii_sel = ofnode_get_addr(node); - if (cpsw_common->gmii_sel == FDT_ADDR_T_NONE) { - dev_err(dev, "failed to get gmii_sel base\n"); - goto out; - } - cpsw_common->bus_freq = dev_read_u32_default(dev, "bus_freq", AM65_CPSW_MDIO_BUS_FREQ_DEF); -- 2.34.1