From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF858EB64DD for ; Tue, 25 Jul 2023 21:25:13 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2232F86698; Tue, 25 Jul 2023 23:25:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=konsulko.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=konsulko.com header.i=@konsulko.com header.b="INobic6J"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1787E86698; Tue, 25 Jul 2023 23:25:11 +0200 (CEST) Received: from mail-vs1-xe33.google.com (mail-vs1-xe33.google.com [IPv6:2607:f8b0:4864:20::e33]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6EA3486682 for ; Tue, 25 Jul 2023 23:25:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=konsulko.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=trini@konsulko.com Received: by mail-vs1-xe33.google.com with SMTP id ada2fe7eead31-4436f2d8bcdso191630137.1 for ; Tue, 25 Jul 2023 14:25:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=konsulko.com; s=google; t=1690320307; x=1690925107; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=h0sA101EBVxi4rIwtyV6UI6navcuGYyetsJDutjfkjM=; b=INobic6J1f5O4HK4OzaIByWXqUgVV6DghuQNpwXZJPhm/j4vWKiSn7Lc3G3CZOWwyj DzKRPVs+DUKR/tGWNc4TKQit7JK1191W77JZVB6GINYhnGW+YFdFDDwbg0bKljktU0Uj vQRcnJDPG2ExEVDGUN8lduzgkOK042zPOYw8o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690320307; x=1690925107; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=h0sA101EBVxi4rIwtyV6UI6navcuGYyetsJDutjfkjM=; b=fYoW3vKMZR7o+/cpKPExvyqqtrupxA6XhxG2Fao/htmyMVB1GRBL/hlBcBJEWRvkuM KQakmXFaurpqucvIWscHkgkrhnu6L2JJMG+2XMW1hOwLdBcbxggFEisSQlu1Hj4GVZrY nbs+JjpkzvR7hXR6BZ/vUP1wiSqR7Hc9Pab9yryGAZ//AjeaJzI+WynUM9UqKWF7ayWk I1/UjvC4orlnfdWdPPipSxvlIP2dfpD0zKWEzGXGkEP7ik98xQ3EGrtKzp7j/jXM5stX qYzgq7IrZKs9iSHyb406OuLdQ2XjwDoYu4p6wYut9Lx51Oaq499llaAoNe+/Z1D5IIkt WAAw== X-Gm-Message-State: ABy/qLZnecl01U22sGVqGOlIhQv4sLGz8o8UhD9VrEq/+j/M4N+8yJG8 gXbq76/33ne8EvWoZa52t5Nv/Q== X-Google-Smtp-Source: APBJJlEcmGqpIWPn+vjs6j7C4N+gJEvi/RUG52pbaILM388Rk3rBR7KjOIMu4hBt/mTlaha45qLhVQ== X-Received: by 2002:a05:6102:3a66:b0:446:ea0e:f8a3 with SMTP id bf6-20020a0561023a6600b00446ea0ef8a3mr1362682vsb.15.1690320307253; Tue, 25 Jul 2023 14:25:07 -0700 (PDT) Received: from bill-the-cat (2603-6081-7b00-6400-b236-e3a5-57be-379d.res6.spectrum.com. [2603:6081:7b00:6400:b236:e3a5:57be:379d]) by smtp.gmail.com with ESMTPSA id n9-20020ab05409000000b0079570a440aesm1190011uaa.9.2023.07.25.14.25.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 14:25:06 -0700 (PDT) Date: Tue, 25 Jul 2023 17:25:04 -0400 From: Tom Rini To: Nishanth Menon Cc: Neha Malcom Francis , Bryan Brattlof , Praneeth Bajjuri , Andrew Davis , Robert Nelson , Vignesh R , u-boot@lists.denx.de Subject: Re: [PATCH 3/6] board: ti: am62x: Add basic initialization for usb voltage, 32k crystal, debounce Message-ID: <20230725212504.GH3630934@bill-the-cat> References: <20230725185253.2123433-1-nm@ti.com> <20230725185253.2123433-4-nm@ti.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="SGspN4osLM0YOuYG" Content-Disposition: inline In-Reply-To: <20230725185253.2123433-4-nm@ti.com> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean --SGspN4osLM0YOuYG Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Jul 25, 2023 at 01:52:50PM -0500, Nishanth Menon wrote: > Do the basic configuration required for setting up the USB core voltage > configuration, setup to configure the 32k clock coming from 32k crystal > and the debounce configurations for the various pins. >=20 > Signed-off-by: Nishanth Menon > --- > board/ti/am62x/evm.c | 46 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) >=20 > diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c > index ad939088402e..87b1fe0a2f44 100644 > --- a/board/ti/am62x/evm.c > +++ b/board/ti/am62x/evm.c > @@ -78,8 +78,54 @@ static int video_setup(void) > return 0; > } > =20 > +#define CTRLMMR_USB0_PHY_CTRL 0x43004008 > +#define CTRLMMR_USB1_PHY_CTRL 0x43004018 > +#define CORE_VOLTAGE 0x80000000 > + > +#define WKUP_CTRLMMR_DBOUNCE_CFG1 0x04504084 > +#define WKUP_CTRLMMR_DBOUNCE_CFG2 0x04504088 > +#define WKUP_CTRLMMR_DBOUNCE_CFG3 0x0450408c > +#define WKUP_CTRLMMR_DBOUNCE_CFG4 0x04504090 > +#define WKUP_CTRLMMR_DBOUNCE_CFG5 0x04504094 > +#define WKUP_CTRLMMR_DBOUNCE_CFG6 0x04504098 > + > void spl_board_init(void) > { > + u32 val; > + > + /* Set USB0 PHY core voltage to 0.85V */ > + val =3D readl(CTRLMMR_USB0_PHY_CTRL); > + val &=3D ~(CORE_VOLTAGE); > + writel(val, CTRLMMR_USB0_PHY_CTRL); > + > + /* Set USB1 PHY core voltage to 0.85V */ > + val =3D readl(CTRLMMR_USB1_PHY_CTRL); > + val &=3D ~(CORE_VOLTAGE); > + writel(val, CTRLMMR_USB1_PHY_CTRL); > + > + /* We have 32k crystal, so lets enable it */ > + val =3D readl(MCU_CTRL_LFXOSC_CTRL); > + val &=3D ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL); > + writel(val, MCU_CTRL_LFXOSC_CTRL); > + /* Add any TRIM needed for the crystal here.. */ > + /* Make sure to mux up to take the SoC 32k from the crystal */ > + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, > + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); > + > + /* Setup debounce conf registers - arbitrary values. Times are approx */ > + /* 1.9ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG1, 0x1); > + /* 5ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG2, 0x5); > + /* 20ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG3, 0x14); > + /* 46ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG4, 0x18); > + /* 100ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG5, 0x1c); > + /* 156ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG6, 0x1f); > + > video_setup(); > enable_caches(); > if (IS_ENABLED(CONFIG_SPL_SPLASH_SCREEN) && IS_ENABLED(CONFIG_SPL_BMP)) Here's a whole lot of seemingly board specific code in a function and file that's supposed to support any am62 platform. Is this really what we need, where we need it? --=20 Tom --SGspN4osLM0YOuYG Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmTAPbAACgkQFHw5/5Y0 tyzCTAv9Hyu/ePmS6oBKBD91vTjyCfbva38lT7O57syFBWCOsl/6tw00G1W4KWqf t4nWd0AzfKR+kEwFuHHzvpflfCEznCZy3S1WhyAaCubkAzFkA6/WEFqpFRw/2Vtr uLD8DssE2gwQWvAUDD3qvNRCnjH+iejxYobcyM5IIfGltmESN8fDalC04vMUSkbJ nJWcleoGJbvhHFqNISzNCV5klxgdduHbzzpDx8cLFkfAom6raU9u013ZyecyEANJ X+boCnCEWkpA1Ot1eMWUX9vuxvlRm1TCfmMIlrIZAVAa5UQrLwpu0LLwmJzdXR9+ g3x3O6S4vVYkVqgQNN5svoMNjdXsC0580UvTSixnCdzwVfnze+rtzNH9llhYmwnB 7i30VNfdXH9RdLgePzBnwskBiZdk61kl7GjtsttH/JEZ0dytb2YkT5tOHaABePZk jScb8iZosgwOJoGJXdoK7u4f/fk98QXBvy0p/mk/9eHP1CMMk6Mt0AhqocF65TSJ BUISEMlW =POuE -----END PGP SIGNATURE----- --SGspN4osLM0YOuYG--