From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BD5BC0015E for ; Tue, 1 Aug 2023 07:29:20 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F14A886B5E; Tue, 1 Aug 2023 09:28:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=collabora.com header.i=@collabora.com header.b="Dz/mV3tw"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C940B86C8C; Tue, 1 Aug 2023 09:28:40 +0200 (CEST) Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BE6B686C25 for ; Tue, 1 Aug 2023 09:28:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=eugen.hristev@collabora.com Received: from eugen-station.. (unknown [82.76.24.202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: ehristev) by madras.collabora.co.uk (Postfix) with ESMTPSA id E451E6607186; Tue, 1 Aug 2023 08:28:34 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690874915; bh=509MGNebSFaWM6REQ9DA6WXhpfwXXM7/lDXsyUC/Qso=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dz/mV3tw0WNSbUb4Podl6HlwmkSmRZtaysmLEPIEzTkXIxDvm0wK/+ng8g8hGQnY/ uzm+/704s7SMVtRwpf1Xdmk3QKZPZbosZqqWNvmQnAO+oYGtY0CBZE+e+6/W2Ks4/m lrp2KV0mC9MkRatjPl9ax2hgYjTP/LhzmCKPQ5BvaSelSr9TzcUCpzlo0e1o+P1hcT kKP9M59vGwBANYh+XhV7rWTxFwb6laqFNMXDdehas/HUzoaiaCTAp1hpbZLnbV/fxG 3S18r6V3uy1gmHSJziOonoGhfmtTIKTo86ZyQqJFINvZyawachm07KT0L60eEobHb5 zKjmxhCx93cqA== From: Eugen Hristev To: kever.yang@rock-chips.com, u-boot@lists.denx.de Cc: marex@denx.de, jonas@kwiboo.se, jagan@edgeble.ai, eugen.hristev@collabora.com, kernel@collabora.com, Venkatesh Yadav Abbarapu Subject: [PATCH v2 04/10] usb: dwc3: core: Only handle soft-reset in DCTL Date: Tue, 1 Aug 2023 10:28:05 +0300 Message-Id: <20230801072811.10354-5-eugen.hristev@collabora.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801072811.10354-1-eugen.hristev@collabora.com> References: <20230801072811.10354-1-eugen.hristev@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Venkatesh Yadav Abbarapu [ Nguyen/Greg: Ported from Linux kernel commit f4fd84ae0765a ("usb: dwc3: core: Only handle soft-reset in DCTL") ] Make sure not to set run_stop bit or link state change request while initiating soft-reset. Register read-modify-write operation may unintentionally start the controller before the initialization completes with its previous DCTL value, which can cause initialization failure. Signed-off-by: Venkatesh Yadav Abbarapu --- Not to be merged, I know Marek does not apply any patches to DWC3. drivers/usb/dwc3/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index bdfe51c3df96..06ca3fc96842 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -72,7 +72,8 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg |= DWC3_DCTL_CSFTRST; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + reg &= ~DWC3_DCTL_RUN_STOP; + dwc3_gadget_dctl_write_safe(dwc, reg); /* Assert USB3 PHY reset */ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); -- 2.34.1