[PATCH v1 0/4] Add VF2 USB host support.

[PATCH v1 0/4] Add VF2 USB host support.

[Minda Chen]

StarFive VF2 VTI usb-host controller connect to pcie0 RC.
Enable pcie0 first the enable USB function.

patch1 is Get the correct ECAM offset in multiple PCIe RC.
patch2 is enable pcie0 dts node.
patch3 is enable SYS_CACHE_LINE_SIZE
patch4 is Add VF2 USB related configuration.

Minda Chen (4):
  pci: plda: Get correct ECAM offset in multiple PCIe RC case
  riscv: dts: starfive: Enable pcie0 dts node
  riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHE_LINE_SIZE
  configs: riscv: starfive: Add VF2 PCIe XHCI config support

 arch/riscv/Kconfig                               | 1 +
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +-
 configs/starfive_visionfive2_defconfig           | 5 +++++
 drivers/pci/pcie_plda_common.c                   | 5 +++--
 4 files changed, 10 insertions(+), 3 deletions(-)

base-commit: 38dedebc547f795efc3daad17f7c013c515e1285
-- 
2.17.1

[PATCH v1 1/4] pci: plda: Get correct ECAM offset in multiple PCIe RC case

[Minda Chen]

Get the correct ECAM offset and record the secondary bus
number in Multiple RC case.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 drivers/pci/pcie_plda_common.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c
index 005b92616a..cd74bb4711 100644
--- a/drivers/pci/pcie_plda_common.c
+++ b/drivers/pci/pcie_plda_common.c
@@ -36,8 +36,8 @@ static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
 				  uint offset, void **paddr)
 {
 	struct pcie_plda *priv = dev_get_priv(udev);
-	int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
-				     PCI_FUNC(bdf), offset);
+	int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(udev),
+				     PCI_DEV(bdf), PCI_FUNC(bdf), offset);
 
 	if (!plda_pcie_addr_valid(priv, bdf))
 		return -ENODEV;
@@ -71,6 +71,7 @@ int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
 	    (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
 		priv->sec_busno =
 			((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 0xff;
+		priv->sec_busno += dev_seq(udev);
 		debug("Secondary bus number was changed to %d\n",
 		      priv->sec_busno);
 	}
-- 
2.17.1

[PATCH v1 2/4] riscv: dts: starfive: Enable pcie0 dts node

[Minda Chen]

In StarFive VF2 board. pcie0 connect to VTI usb controller.
Enable it to support usb host.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index bf7fdb4dd6..e40f57a150 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -311,7 +311,7 @@
 
 &pcie0 {
 	reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
-	status = "disabled";
+	status = "okay";
 };
 
 &pcie1 {
-- 
2.17.1

[PATCH v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHE_LINE_SIZE

[Minda Chen]

Some devices need SYS_CACHE_LINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 867cbcbe74..15da2a8559 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -26,6 +26,7 @@ config TARGET_SIFIVE_UNMATCHED
 
 config TARGET_STARFIVE_VISIONFIVE2
 	bool "Support StarFive VisionFive2 Board"
+	select SYS_CACHE_SHIFT_6
 
 config TARGET_TH1520_LPI4A
 	bool "Support Sipeed's TH1520 Lichee PI 4A Board"
-- 
2.17.1

Re: [PATCH v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHE_LINE_SIZE

[Bin Meng]

On Thu, Aug 3, 2023 at 11:22 AM Minda Chen <minda.chen@starfivetech.com> wrote:
>
> Some devices need SYS_CACHE_LINE_SIZE macro. Add StarFive
> SYS_CACHE_SHIFT_6 to enable it.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
>  arch/riscv/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 867cbcbe74..15da2a8559 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -26,6 +26,7 @@ config TARGET_SIFIVE_UNMATCHED
>
>  config TARGET_STARFIVE_VISIONFIVE2
>         bool "Support StarFive VisionFive2 Board"
> +       select SYS_CACHE_SHIFT_6
>
>  config TARGET_TH1520_LPI4A
>         bool "Support Sipeed's TH1520 Lichee PI 4A Board"

This needs to go into arch/riscv/cpu/jh7110/Kconfig::STARFIVE_JH7110

Regards,
Bin

Re: [PATCH v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHE_LINE_SIZE

[Minda Chen]

On 2023/8/3 12:49, Bin Meng wrote:
> On Thu, Aug 3, 2023 at 11:22 AM Minda Chen <minda.chen@starfivetech.com> wrote:
>>
>> Some devices need SYS_CACHE_LINE_SIZE macro. Add StarFive
>> SYS_CACHE_SHIFT_6 to enable it.
>>
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>> ---
>>  arch/riscv/Kconfig | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index 867cbcbe74..15da2a8559 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -26,6 +26,7 @@ config TARGET_SIFIVE_UNMATCHED
>>
>>  config TARGET_STARFIVE_VISIONFIVE2
>>         bool "Support StarFive VisionFive2 Board"
>> +       select SYS_CACHE_SHIFT_6
>>
>>  config TARGET_TH1520_LPI4A
>>         bool "Support Sipeed's TH1520 Lichee PI 4A Board"
> 
> This needs to go into arch/riscv/cpu/jh7110/Kconfig::STARFIVE_JH7110
> 
> Regards,
> Bin
ok, thanks

[PATCH v1 4/4] configs: riscv: starfive: Add VF2 PCIe XHCI config support

[Minda Chen]

Add PCI_XHCI support to enable usb3-host functions.
Also add usb command and keyboard config.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 configs/starfive_visionfive2_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 5d8a8e28cb..a70ada394f 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -65,6 +65,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_OF_BOARD=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -111,3 +112,7 @@ CONFIG_PINCTRL_STARFIVE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER_EARLY=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_KEYBOARD=y
-- 
2.17.1