From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10069EB64DD for ; Sat, 5 Aug 2023 08:15:26 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0B862867B2; Sat, 5 Aug 2023 10:15:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="dR4fM4gW"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EC3D08672B; Sat, 5 Aug 2023 10:15:03 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 32E1B8678C for ; Sat, 5 Aug 2023 10:14:57 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rogerq@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E5F9860B7C; Sat, 5 Aug 2023 08:14:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB3E0C433C9; Sat, 5 Aug 2023 08:14:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1691223295; bh=oOjtG33XyyyWeyYSLUDSf+YpMAya3+yhGc/Y1hs7LC8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dR4fM4gWK+q+ZO3rprPJAf4x6/D7B6ZB3akG/2gzyscbXSjK58PilI/lO8HcwMF4h bhPVs/DcXQoRjvFua0cDXCclCDqZepsuG9fFlbHq9x0H3El3j8WeNdnU1zsa4uaT7b GNb1K/4fYBQ6E07b9Ye5fB1YlX2fAN4v8GfVg9nKX3erCDwCfAJDLQDo0Vn4D50HX4 AqjPqJ1kaIzYDKx9LH0crdfuUq7qGIJhPQgAB7E1AlG+in4rc24VZfrCoPss0nTWt2 Ou3k6sidLxZn69pBOzErla3aqGlg7/QhMPGTM5lAuLwJ4wnyHW2WqijWG9UJaujdT9 G5fjAda0F8Ggw== From: Roger Quadros To: trini@konsulko.com Cc: nm@ti.com, vigneshr@ti.com, srk@ti.com, r-gunasekaran@ti.com, s-vadapalli@ti.com, u-boot@lists.denx.de, Roger Quadros Subject: [PATCH v5 3/4] doc: board: ti: am64: Add boot flow diagram Date: Sat, 5 Aug 2023 11:14:39 +0300 Message-Id: <20230805081440.7045-4-rogerq@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230805081440.7045-1-rogerq@kernel.org> References: <20230805081440.7045-1-rogerq@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add documenatation and boot flow diagram for AM64 EVM/SoC. Suggested-by: Nishanth Menon Signed-off-by: Roger Quadros Reviewed-by: Nishanth Menon Tested-by: Nishanth Menon #SK-AM64B --- doc/board/ti/am64x_evm.rst | 197 +++ doc/board/ti/img/boot_diagram_am64.svg | 1702 ++++++++++++++++++++++++ doc/board/ti/k3.rst | 1 + 3 files changed, 1900 insertions(+) create mode 100644 doc/board/ti/am64x_evm.rst create mode 100644 doc/board/ti/img/boot_diagram_am64.svg diff --git a/doc/board/ti/am64x_evm.rst b/doc/board/ti/am64x_evm.rst new file mode 100644 index 0000000000..8d3795eb32 --- /dev/null +++ b/doc/board/ti/am64x_evm.rst @@ -0,0 +1,197 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Nishanth Menon + +AM64 Platforms +============== + +Introduction: +------------- +The AM642 SoC belongs to the K3 Multicore SoC architecture platform, +providing advanced system integration to enable applications such as +Motor Drives, PLC, Remote IO and IoT Gateways. + +Some highlights of this SoC are: + +* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F + MCUs, and a single Cortex-M4F. +* Two Gigabit Industrial Communication Subsystems (ICSSG). +* Integrated Ethernet switch supporting up to a total of two external + ports. +* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory + controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other + peripherals. +* Centralized System Controller for Security, Power, and Resource + Management (DMSC). + +More details can be found in the Technical Reference Manual: + https://www.ti.com/lit/pdf/spruim2 + +Platform information: + +* AM64-EVM: https://www.ti.com/tool/TMDS64EVM +* AM64-SK: https://www.ti.com/tool/SK-AM64B + +Boot Flow: +---------- +Below is the pictorial representation of boot flow: + +.. image:: img/boot_diagram_am64.svg + +- Here TIFS acts as master and provides all the critical services. R5/A53 + requests TIFS to get these services done as shown in the above diagram. + +Sources: +-------- + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_boot_sources + :end-before: .. k3_rst_include_end_boot_sources + +Build procedure: +---------------- +0. Setup the environment variables: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_desc + :end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_board_env_vars_desc + :end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_defn + :end-before: .. k3_rst_include_end_common_env_vars_defn +.. code-block:: bash + + $ export UBOOT_CFG_CORTEXR=am64x_evm_r5_defconfig + $ export UBOOT_CFG_CORTEXA=am64x_evm_a53_defconfig + $ export TFA_BOARD=lite + $ # we dont use any extra TFA parameters + $ unset TFA_EXTRA_ARGS + $ export OPTEE_PLATFORM=k3-am64x + $ # we dont use any extra TFA parameters + $ unset OPTEE_EXTRA_ARGS + +.. am64x_evm_rst_include_start_build_steps + +1. Trusted Firmware-A: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_build_steps_tfa + :end-before: .. k3_rst_include_end_build_steps_tfa + + +2. OP-TEE: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_build_steps_optee + :end-before: .. k3_rst_include_end_build_steps_optee + +3. U-Boot: + +* 4.1 R5: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_build_steps_spl_r5 + :end-before: .. k3_rst_include_end_build_steps_spl_r5 + +* 4.2 A53: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_build_steps_uboot + :end-before: .. k3_rst_include_end_build_steps_uboot +.. am64x_evm_rst_include_end_build_steps + +Target Images +-------------- +In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC +variant (GP, HS-FS, HS-SE) requires a different source for these files. + + - GP + + * tiboot3-am64x-gp-evm.bin from step 3.1 + * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2 + + - HS-FS + + * tiboot3-am64x-hs-fs-evm.bin from step 3.1 + * tispl.bin, u-boot.img from step 3.2 + + - HS-SE + + * tiboot3-am64x-hs-evm.bin from step 3.1 + * tispl.bin, u-boot.img from step 3.2 + +Image formats: +-------------- + +- tiboot3.bin + +.. image:: img/multi_cert_tiboot3.bin.svg + +- tispl.bin + +.. image:: img/nodm_tispl.bin.svg + +Switch Setting for Boot Mode +---------------------------- + +Boot Mode pins provide means to select the boot mode and options before the +device is powered up. After every POR, they are the main source to populate +the Boot Parameter Tables. + +The following table shows some common boot modes used on AM64 platform. More +details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruim2 under the `Boot Mode Pins` section. + +.. list-table:: Boot Modes for AM64x-EVM + :widths: 16 16 16 + :header-rows: 1 + + * - Switch Label + - SW2: 12345678 + - SW3: 12345678 + + * - SD/MMC + - 11000010 + - 01000000 + + * - xSPI/SFDP (OSPI) + - 11001110 + - 01000000 + + * - UART + - 11011100 + - 00000000 + +.. note :: + + For SW2 and SW3, the switch state in the "ON" position = 1. + +.. list-table:: Boot Modes for AM64x-SK + :widths: 16 16 16 + :header-rows: 1 + + * - Switch Label + - SW2: 12345678 + - SW3: 12345678 + + * - SD/MMC + - 00000010 + - 01000011 + + * - xSPI/SFDP (OSPI) + - 00000010 + - 01110011 + + * - UART + - 00000000 + - 00111011 + +.. note :: + + For SW2 and SW3, the switch state in the "ON" position = 1. + Boot bits on SK is reversed bits to the bootmode signals diff --git a/doc/board/ti/img/boot_diagram_am64.svg b/doc/board/ti/img/boot_diagram_am64.svg new file mode 100644 index 0000000000..9c922a59fa --- /dev/null +++ b/doc/board/ti/img/boot_diagram_am64.svg @@ -0,0 +1,1702 @@ + + + + + + + + + + + + + + + + + Cortex-R + + + + Cortex-R + + + + + + + + + + ROM + + + + ROM + + + + + + + + + + Cortex-R SPL + + + + Cortex-R SPL + + + + + + + + + Load and auth tiboot3.bin + + + + Load and auth t... + + + + + + + + + Load system + +config data + + + + Load system... + + + + + + + + + DDR Config + + + + DDR Config + + + + + + + + + Load tispl.bin + + + + Load tispl.bin + + + + + + + + + Start Cortex-A + + + + Start Cortex-A + + + + + + + + + + Start Cortex-A + + + + Start Cort... + + + + + + + + + + + + + + + + + + Cortex-A + + + + Cortex-A + + + + + + + + + + + + + Cortex-R/M + +C6x/C7x + + + + Cortex-R/M... + + + + + + + + + + Aux f/w + + + + Aux f/w + + + + + + + + + + TIFS/DMSC + + + + TIFS/DMSC + + + + + + + + + + ROM + + + + ROM + + + + + + + + + + + Start SYSFW + + + + Start SYSFW + + + + + + + + + SYSFW + + + + SYSFW + + + + + + + + + + Security Enclave Boot Processor + + + + Security Enclave Boot... + + + + + + + + + + Boot Loader + +Processor + + + + Boot Loader... + + + + + + + + + + Main CPU + + + + Main CPU + + + + + + + + + + Auxiliary + +Processor + + + + Auxiliary... + + + + + + + + + + H/w Seq: Reset rls + + + + H/w Seq: Reset rls + + + + + + + + + + Auth tiboot3.bin + + + + Auth tiboo... + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + + + + Load system config data + + + + Load syste... + + + + + + + + + Start SYSFW + + + + Start SYSFW + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + + + TF-A + + + + TF-A + + + + + + + + + + OP-TEE + + + + OP-TEE + + + + + + + + + + Cortex A SPL + + + + Cortex A SPL + + + + + + + + + + U-Boot + + + + U-Boot + + + + + + + + + Load u-boot.img + + + + Load u-boot.img + + + + + + + + + Load Aux core f/w + +(optional) + + + + Load Aux core f/w... + + + + + + + + + Start Aux core + +(optional) + + + + Start Aux core... + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + Text is not SVG - cannot display + + + diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 9d40675b60..74fdc6b41c 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -31,6 +31,7 @@ K3 Based SoCs :maxdepth: 1 am62x_sk + am64x_evm am65x_evm j7200_evm j721e_evm -- 2.34.1