From: Minda Chen <minda.chen@starfivetech.com>
To: "Pali Rohár" <pali@kernel.org>, "Rick Chen" <rick@andestech.com>,
Leo <ycliang@andestech.com>, "Torsten Duwe" <duwe@suse.de>,
"Bin Meng" <bmeng.cn@gmail.com>
Cc: <u-boot@lists.denx.de>, Mason Huo <mason.huo@starfivetech.com>,
Minda Chen <minda.chen@starfivetech.com>
Subject: [RESEND, v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE
Date: Mon, 7 Aug 2023 16:53:37 +0800 [thread overview]
Message-ID: <20230807085338.27119-4-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20230807085338.27119-1-minda.chen@starfivetech.com>
Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
arch/riscv/cpu/jh7110/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 4d9581165b..c1d3e6ada2 100644
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -13,6 +13,7 @@ config STARFIVE_JH7110
select SUPPORT_SPL
select SPL_RAM if SPL
select SPL_STARFIVE_DDR
+ select SYS_CACHE_SHIFT_6
select PINCTRL_STARFIVE_JH7110
imply MMC
imply MMC_BROKEN_CD
--
2.17.1
next prev parent reply other threads:[~2023-08-07 8:54 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-07 8:53 [RESEND,v1 0/4] Add StarFive VF2 USB host support Minda Chen
2023-08-07 8:53 ` [RESEND, v1 1/4] pci: plda: Get correct ECAM offset in multiple PCIe RC case Minda Chen
2023-08-09 7:02 ` [RESEND,v1 " Leo Liang
2023-08-07 8:53 ` [RESEND,v1 2/4] riscv: dts: starfive: Enable pcie0 dts node Minda Chen
2023-08-09 7:03 ` Leo Liang
2023-08-07 8:53 ` Minda Chen [this message]
2023-08-07 10:18 ` [RESEND, v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE Bin Meng
2023-08-09 7:04 ` Leo Liang
2023-08-07 8:53 ` [RESEND, v1 4/4] configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support Minda Chen
2023-08-09 7:04 ` Leo Liang
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