From: Tom Rini <trini@konsulko.com>
To: Tony Dinh <mibodhi@gmail.com>
Cc: U-Boot Mailing List <u-boot@lists.denx.de>,
Simon Glass <sjg@chromium.org>, Stefan Roese <sr@denx.de>
Subject: Re: bootstd: CACHE Misaligned operation errors (Marvell Armada 385)
Date: Wed, 13 Sep 2023 16:13:55 -0400 [thread overview]
Message-ID: <20230913201355.GR305624@bill-the-cat> (raw)
In-Reply-To: <CAJaLiFw9btZtcro_qqtYqTJziZwLuUJ=0QAuu+E5=Ooux4-WkA@mail.gmail.com>
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On Wed, Sep 13, 2023 at 12:56:53PM -0700, Tony Dinh wrote:
> Hi Tom,
>
> On Wed, Sep 13, 2023 at 9:22 AM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Tue, Sep 12, 2023 at 12:38:00PM -0700, Tony Dinh wrote:
> >
> > > I've been testing the boostd for a few Marvell boards and seeing this
> > > error on the Thecus N2350 (Marvell Armada 385, dual-core CPU). The
> > > "bootflow scan scsi" command triggered the "CACHE: Misaligned
> > > operation at range" error. However, this error did not affect the
> > > result of the scan, i.e. the bootflow for scsi partition was created
> > > correctly, and u-boot is running normally.
> > >
> > > Enabling CONFIG_SYS_DCACHE_OFF got rid of the errors altogether.
> > > Perhaps this is a case where the DCACHE is not required and should be
> > > turned off?
> > >
> > > Please see the log after the break below.
> >
> > Can you please try -next ? There's at least one SCSI related cache
> > alignment fix there that's not in master, thanks.
>
> Unfortunately I got the same errors. This time the ranges are
> different, of course.
>
> master:
>
> N2350 > bootflow scan scsi
> CACHE: Misaligned operation at range [3fb99f88, 3fb9a388]
> CACHE: Misaligned operation at range [3fb99f88, 3fb9a388]
> CACHE: Misaligned operation at range [3fb99f88, 3fb9a388]
> ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3fb99f88
> ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x3fb9a388
>
> next:
>
> N2350 > bootflow scan scsi
> CACHE: Misaligned operation at range [3fb80388, 3fb80788]
> CACHE: Misaligned operation at range [3fb80388, 3fb80788]
> CACHE: Misaligned operation at range [3fb80388, 3fb80788]
> ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3fb80388
> ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x3fb80788
Can you debug to where these calls are so we can align these buffers?
See 02660defdc8a ("scsi: Cache align temporary buffer") for an example.
--
Tom
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next prev parent reply other threads:[~2023-09-13 20:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 19:38 bootstd: CACHE Misaligned operation errors (Marvell Armada 385) Tony Dinh
2023-09-13 16:22 ` Tom Rini
2023-09-13 19:56 ` Tony Dinh
2023-09-13 20:13 ` Tom Rini [this message]
2023-09-14 0:27 ` Tony Dinh
2023-09-14 3:37 ` Simon Glass
2023-09-14 4:53 ` Tony Dinh
2023-09-16 1:32 ` Tony Dinh
2023-09-16 3:40 ` Tony Dinh
2023-09-16 19:36 ` Tony Dinh
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