From: Fei Wu <fei2.wu@intel.com>
To: xypron.glpk@gmx.de, rick@andestech.com, ycliang@andestech.com,
bmeng.cn@gmail.com, sjg@chromium.org, pali@kernel.org,
u-boot@lists.denx.de, andrei.warkentin@intel.com,
sunilvl@ventanamicro.com
Cc: Fei Wu <fei2.wu@intel.com>
Subject: [PATCH v2] riscv: enable multi-range memory layout
Date: Thu, 14 Sep 2023 13:30:55 +0800 [thread overview]
Message-ID: <20230914053055.745507-1-fei2.wu@intel.com> (raw)
In order to enable PCIe passthrough on qemu riscv, the physical memory
range between 3GB and 4GB is reserved. Therefore if guest has 4GB ram,
two ranges are created as [2G, 3G) and [4G, 7G), currently u-boot sets
ram_top to 4G - 1 if the gd->ram_top is above 4G in
board_get_usable_ram_top(), but that address is not backed by ram. This
patch selects the lowest range instead.
Signed-off-by: Fei Wu <fei2.wu@intel.com>
---
arch/riscv/cpu/generic/dram.c | 2 +-
configs/qemu-riscv64_defconfig | 2 +-
configs/qemu-riscv64_smode_defconfig | 2 +-
configs/qemu-riscv64_spl_defconfig | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 44e11bd56c..fb53a57b4e 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- return fdtdec_setup_mem_size_base();
+ return fdtdec_setup_mem_size_base_lowest();
}
int dram_init_banksize(void)
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index 9a8bbef192..aa55317d26 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -1,6 +1,6 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index 1d0f021ade..de08a49dab 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -1,6 +1,6 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index bb10145e6e..66dc2a1dd9 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -1,6 +1,6 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
--
2.34.1
next reply other threads:[~2023-09-14 5:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-14 5:30 Fei Wu [this message]
2023-09-14 6:05 ` [PATCH v2] riscv: enable multi-range memory layout Heinrich Schuchardt
2023-09-14 6:48 ` Wu, Fei
2023-09-14 7:17 ` Wu, Fei
2023-09-14 7:20 ` Heinrich Schuchardt
2023-09-14 7:42 ` Wu, Fei
2023-09-14 10:21 ` Heinrich Schuchardt
2023-09-14 11:19 ` Heinrich Schuchardt
2023-09-22 6:17 ` Wu, Fei
2023-09-25 5:52 ` Wu, Fei
2023-09-26 5:07 ` Anup Patel
2023-09-26 7:04 ` Heinrich Schuchardt
2023-10-09 10:04 ` Wu, Fei
2023-10-11 10:05 ` Wu, Fei
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