From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <u-boot@lists.denx.de>, <rick@andestech.com>,
<ycliang@andestech.com>, <peterlin@andestech.com>,
<randolph@andestech.com>
Cc: <twarren@nvidia.com>, <sjg@chromium.org>, <saproj@gmail.com>,
<william.zhang@broadcom.com>, <andre.przywara@arm.com>,
<clamor95@gmail.com>, <patrice.chotard@foss.st.com>,
<jonasschwoebel@yahoo.de>, <bmeng@tinylab.org>
Subject: [PATCH] riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode
Date: Wed, 27 Sep 2023 15:25:00 +0800 [thread overview]
Message-ID: <20230927072500.1018499-1-peterlin@andestech.com> (raw)
The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.
Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add SPL_ANDES_PLMT_TIMER
config, the PLMT driver will be compiled only against M-mode
U-Boot or U-Boot SPL.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
arch/riscv/cpu/andesv5/Kconfig | 3 ++-
drivers/timer/Kconfig | 9 ++++++++-
drivers/timer/Makefile | 2 +-
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig
index 82bb5a2a53..eba576af2f 100644
--- a/arch/riscv/cpu/andesv5/Kconfig
+++ b/arch/riscv/cpu/andesv5/Kconfig
@@ -4,8 +4,9 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply ANDES_PLMT_TIMER if RISCV_MMODE
+ imply SPL_ANDES_PLMT_TIMER if SPL_RISCV_MMODE
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
imply V5L2_CACHE
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 915b2af160..157298a941 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -59,7 +59,14 @@ config ALTERA_TIMER
config ANDES_PLMT_TIMER
bool
- depends on RISCV_MMODE || SPL_RISCV_MMODE
+ depends on RISCV_MMODE
+ help
+ The Andes PLMT block holds memory-mapped mtime register
+ associated with timer tick.
+
+config SPL_ANDES_PLMT_TIMER
+ bool
+ depends on SPL_RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 1ca74805fd..1f5c16fdf3 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -4,7 +4,7 @@
obj-y += timer-uclass.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
-obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
+obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
--
2.34.1
next reply other threads:[~2023-09-27 7:27 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 7:25 Yu Chien Peter Lin [this message]
2023-09-27 21:32 ` [PATCH] riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode Samuel Holland
2023-09-29 3:48 ` Yu-Chien Peter Lin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230927072500.1018499-1-peterlin@andestech.com \
--to=peterlin@andestech.com \
--cc=andre.przywara@arm.com \
--cc=bmeng@tinylab.org \
--cc=clamor95@gmail.com \
--cc=jonasschwoebel@yahoo.de \
--cc=patrice.chotard@foss.st.com \
--cc=randolph@andestech.com \
--cc=rick@andestech.com \
--cc=saproj@gmail.com \
--cc=sjg@chromium.org \
--cc=twarren@nvidia.com \
--cc=u-boot@lists.denx.de \
--cc=william.zhang@broadcom.com \
--cc=ycliang@andestech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox