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From: Tom Rini <trini@konsulko.com>
To: Andre Przywara <andre.przywara@arm.com>
Cc: Simon Glass <sjg@chromium.org>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Xiang W <merlew4n6@gmail.com>,
	Chanho Park <chanho61.park@samsung.com>,
	Sughosh Ganu <sughosh.ganu@linaro.org>,
	u-boot@lists.denx.de, Peter Hoyes <Peter.Hoyes@arm.com>,
	Alexey Romanov <avromanov@salutedevices.com>,
	Ilias Apalodimas <ilias.apalodimas@linaro.org>
Subject: Re: [PATCH v3 0/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension
Date: Mon, 6 Nov 2023 11:46:27 -0500	[thread overview]
Message-ID: <20231106164627.GA496310@bill-the-cat> (raw)
In-Reply-To: <20231104171212.3d041a4f@slackpad.lan>

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On Sat, Nov 04, 2023 at 05:12:12PM +0000, Andre Przywara wrote:
> On Fri, 3 Nov 2023 13:38:58 -0600
> Simon Glass <sjg@chromium.org> wrote:
> 
> Hi Simon,
> 
> > Hi Heinrich,
> > 
> > On Wed, 1 Nov 2023 at 14:20, Heinrich Schuchardt
> > <heinrich.schuchardt@canonical.com> wrote:
> > >
> > > On 11/1/23 19:05, Andre Przywara wrote:  
> > > > On Tue, 31 Oct 2023 14:55:50 +0200
> > > > Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote:
> > > >
> > > > Hi Heinrich,
> > > >  
> > > >> The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
> > > >> provides an interface to a physical entropy source.
> > > >>
> > > >> A RNG driver based on the seed CSR is provided. It depends on
> > > >> mseccfg.sseed being set in the SBI firmware.  
> > > >
> > > > As you might have seen, I added a similar driver for the respective Arm
> > > > functionality:
> > > > https://lore.kernel.org/u-boot/20230830113230.3925868-1-andre.przywara@arm.com/
> > > >
> > > > And I see that you seem to use the same mechanism to probe and init the
> > > > driver: U_BOOT_DRVINFO and fail in probe() if the feature is not
> > > > implemented.
> > > > One downside of this approach is that the driver is always loaded (and
> > > > visible in the DM tree), even with the feature not being available.
> > > > That doesn't seem too much of a problem on the first glance, but it
> > > > occupies a device number, and any subsequent other DM_RNG devices
> > > > (like virtio-rng) typically get higher device numbers. So without
> > > > the feature, but with virtio-rng, I get:
> > > > VExpress64# rng 0
> > > > No RNG device  
> > 
> > Why do we get this? If the device is not there, the bind() function
> > can return -ENODEV
> > 
> > I see this in U-Boot:
> > 
> > U_BOOT_DRVINFO(cpu_arm_rndr) = {
> > 
> > We should not use this.
> 
> Agreed.
> 
> > Use the devicetree.
> 
> No, this is definitely not something for the DT, at least not on ARM.
> It's perfectly discoverable via the architected CPU ID registers.
> Similar to PCI and USB devices, which we don't probe via the DT as well.
> 
> It's arguably not proper "driver" material per se, as I've argued before, but
> it's the simplest solution and fits in nicely otherwise.
> 
> I was wondering if it might be something for UCLASS_CPU, something like
> a "CPU feature bus": to let devices register on one on the many CPU
> features (instead of compatible strings), then only bind() those
> drivers it the respective bit is set.
> 
> Does that make sense? Would that be doable without boiling the ocean?
> As I don't know if we see many users apart from this.

I think we have a similar problem with how we're doing with DM_TIMER and
armv7-a/armv7-m/armv8[1]. We shouldn't need the drivers in drivers/timer/
to cover platforms where SYS_ARCH_TIMER is (or should be!) enabled. But
in turn, the code under arch/arm/cpu/*/*timer.c doesn't implement the
uclass side of things, only the regular API. This is because there's
nothing to probe even because we don't support the kind of multi-arch
binary where it'd be possible to not have the feature.

-- 
Tom

[1]: We do have the problem of armv7-r not having this feature so things
like say TI K3 platforms need the platform driver on the Cortex-R host.
A similar issue is the pre-ARMv7 i.MX platforms.

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  parent reply	other threads:[~2023-11-06 16:46 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-31 12:55 [PATCH v3 0/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension Heinrich Schuchardt
2023-10-31 12:55 ` [PATCH v3 1/2] riscv: allow resume after exception Heinrich Schuchardt
2023-11-01  8:55   ` Leo Liang
2023-10-31 12:55 ` [PATCH v3 2/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension Heinrich Schuchardt
2023-11-01 17:05 ` [PATCH v3 0/2] " Andre Przywara
2023-11-01 17:16   ` Sean Anderson
2023-11-01 17:49     ` Andre Przywara
2023-11-01 18:20       ` Sean Anderson
2023-11-01 20:20   ` Heinrich Schuchardt
2023-11-03 19:38     ` Simon Glass
2023-11-04 17:12       ` Andre Przywara
2023-11-04 19:45         ` Simon Glass
2023-11-04 20:36           ` Heinrich Schuchardt
2023-11-04 22:58             ` Simon Glass
2023-11-06 17:26           ` Andre Przywara
2023-11-06 20:13             ` Tom Rini
2023-11-06 20:38             ` Simon Glass
2023-11-06 20:46               ` Tom Rini
2023-11-07  1:10                 ` Simon Glass
2023-11-07 19:30                   ` Tom Rini
2023-11-07 21:52                     ` Rob Herring
2023-11-07 22:10                       ` Tom Rini
2023-11-07 22:27                         ` Conor Dooley
2023-11-07 22:38                           ` Tom Rini
2023-11-07 22:51                             ` Simon Glass
2023-11-07 23:14                               ` Tom Rini
2023-11-07 23:12                             ` Conor Dooley
2023-11-07 23:23                               ` Tom Rini
2023-11-08  0:29                                 ` Conor Dooley
2023-11-08  0:34                                   ` Tom Rini
2023-11-08 14:23                                     ` Heinrich Schuchardt
2023-11-08 14:37                                       ` Tom Rini
2023-11-08 15:25                                         ` Heinrich Schuchardt
2023-11-08 16:44                                           ` Tom Rini
2023-11-08 17:10                                             ` Heinrich Schuchardt
2023-11-08 17:38                               ` Palmer Dabbelt
2023-11-10 11:50                                 ` Simon Glass
2023-11-06 21:53               ` Andre Przywara
2023-11-07  1:08                 ` Simon Glass
2023-11-07 11:27                   ` Andre Przywara
2023-11-07 12:22                     ` Simon Glass
2023-11-07 15:12                       ` Andre Przywara
2023-11-07 22:03                         ` Tom Rini
2023-11-08  4:24                         ` Simon Glass
2023-11-08  7:11                           ` Ilias Apalodimas
2023-11-07 21:53                       ` Tom Rini
2023-11-07 21:24                     ` Tom Rini
2023-11-06 16:46         ` Tom Rini [this message]
2023-11-06 17:24           ` Simon Glass
2023-11-06 17:45           ` Andre Przywara

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