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[2603:6081:7b00:6400::13d]) by smtp.gmail.com with ESMTPSA id a13-20020a0ce90d000000b00670a31f77b4sm3578877qvo.93.2023.11.06.08.46.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 08:46:29 -0800 (PST) Date: Mon, 6 Nov 2023 11:46:27 -0500 From: Tom Rini To: Andre Przywara Cc: Simon Glass , Heinrich Schuchardt , Rick Chen , Leo , Anup Patel , Xiang W , Chanho Park , Sughosh Ganu , u-boot@lists.denx.de, Peter Hoyes , Alexey Romanov , Ilias Apalodimas Subject: Re: [PATCH v3 0/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension Message-ID: <20231106164627.GA496310@bill-the-cat> References: <20231031125552.26698-1-heinrich.schuchardt@canonical.com> <20231101170559.680ab493@donnerap.manchester.arm.com> <50ff2080-5831-4963-937d-331248b59973@canonical.com> <20231104171212.3d041a4f@slackpad.lan> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="p/RvDdwv0Ol1MCSl" Content-Disposition: inline In-Reply-To: <20231104171212.3d041a4f@slackpad.lan> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean --p/RvDdwv0Ol1MCSl Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Nov 04, 2023 at 05:12:12PM +0000, Andre Przywara wrote: > On Fri, 3 Nov 2023 13:38:58 -0600 > Simon Glass wrote: >=20 > Hi Simon, >=20 > > Hi Heinrich, > >=20 > > On Wed, 1 Nov 2023 at 14:20, Heinrich Schuchardt > > wrote: > > > > > > On 11/1/23 19:05, Andre Przywara wrote: =20 > > > > On Tue, 31 Oct 2023 14:55:50 +0200 > > > > Heinrich Schuchardt wrote: > > > > > > > > Hi Heinrich, > > > > =20 > > > >> The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR.= It > > > >> provides an interface to a physical entropy source. > > > >> > > > >> A RNG driver based on the seed CSR is provided. It depends on > > > >> mseccfg.sseed being set in the SBI firmware. =20 > > > > > > > > As you might have seen, I added a similar driver for the respective= Arm > > > > functionality: > > > > https://lore.kernel.org/u-boot/20230830113230.3925868-1-andre.przyw= ara@arm.com/ > > > > > > > > And I see that you seem to use the same mechanism to probe and init= the > > > > driver: U_BOOT_DRVINFO and fail in probe() if the feature is not > > > > implemented. > > > > One downside of this approach is that the driver is always loaded (= and > > > > visible in the DM tree), even with the feature not being available. > > > > That doesn't seem too much of a problem on the first glance, but it > > > > occupies a device number, and any subsequent other DM_RNG devices > > > > (like virtio-rng) typically get higher device numbers. So without > > > > the feature, but with virtio-rng, I get: > > > > VExpress64# rng 0 > > > > No RNG device =20 > >=20 > > Why do we get this? If the device is not there, the bind() function > > can return -ENODEV > >=20 > > I see this in U-Boot: > >=20 > > U_BOOT_DRVINFO(cpu_arm_rndr) =3D { > >=20 > > We should not use this. >=20 > Agreed. >=20 > > Use the devicetree. >=20 > No, this is definitely not something for the DT, at least not on ARM. > It's perfectly discoverable via the architected CPU ID registers. > Similar to PCI and USB devices, which we don't probe via the DT as well. >=20 > It's arguably not proper "driver" material per se, as I've argued before,= but > it's the simplest solution and fits in nicely otherwise. >=20 > I was wondering if it might be something for UCLASS_CPU, something like > a "CPU feature bus": to let devices register on one on the many CPU > features (instead of compatible strings), then only bind() those > drivers it the respective bit is set. >=20 > Does that make sense? Would that be doable without boiling the ocean? > As I don't know if we see many users apart from this. I think we have a similar problem with how we're doing with DM_TIMER and armv7-a/armv7-m/armv8[1]. We shouldn't need the drivers in drivers/timer/ to cover platforms where SYS_ARCH_TIMER is (or should be!) enabled. But in turn, the code under arch/arm/cpu/*/*timer.c doesn't implement the uclass side of things, only the regular API. This is because there's nothing to probe even because we don't support the kind of multi-arch binary where it'd be possible to not have the feature. --=20 Tom [1]: We do have the problem of armv7-r not having this feature so things like say TI K3 platforms need the platform driver on the Cortex-R host. A similar issue is the pre-ARMv7 i.MX platforms. --p/RvDdwv0Ol1MCSl Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmVJGFgACgkQFHw5/5Y0 tyyKXQwAtdUBIY6lZ4yzlX6cPQIGnMwYMjOw9oREwdBkVQM8nsIOMYAHw4S8WGjA 0ejY7ka1T7x4wcJ6W+X4Klfjylf8T5JlFNb9xrNYNTkXyL0DnIU3PuL50whrTINZ Vex/f7p8U2v9T+IfH86WrHSYoAOhCwvJQ3TFehZkZpRwPuE0pXFwOBhkVgtmxoWa M5UUlmTxAIDI+8n2jBK14sd3koCZWsFpzA36PyM25OyFis+svWsE4/CNKhcPM4ZE fOCECI7g6uS2ZC8vKxZJDfr436yYVzxzGBxwR+9V+hPSFVeIDcpxrC4LMweP2x4o Zjrv1WRYBtpVQQSMi743xBKRhA2Dbid3xZ7pOSlXeckdmriXOX4j2IXshpi1+8Iw 7+zOqJ8FVJnWUvmJmGZ1ElbOkAEywwUTFAVrD+ZqTGGhX9xlGXP5Tx5MPDAy8Id5 v3wmM8tJeRKNyV+NVZqKVgjY+IfyVsMhC0HrDbEZ9nD7RR/zYkwvjlSdym3ikAlb m95+/whM =ZtuO -----END PGP SIGNATURE----- --p/RvDdwv0Ol1MCSl--