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From: Tom Rini <trini@konsulko.com>
To: Simon Glass <sjg@chromium.org>
Cc: Andre Przywara <andre.przywara@arm.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Xiang W <merlew4n6@gmail.com>,
	Chanho Park <chanho61.park@samsung.com>,
	Sughosh Ganu <sughosh.ganu@linaro.org>,
	u-boot@lists.denx.de, Peter Hoyes <Peter.Hoyes@arm.com>,
	Alexey Romanov <avromanov@salutedevices.com>,
	Ilias Apalodimas <ilias.apalodimas@linaro.org>,
	Rob Herring <robh@kernel.org>
Subject: Re: [PATCH v3 0/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension
Date: Tue, 7 Nov 2023 14:30:25 -0500	[thread overview]
Message-ID: <20231107193025.GN6601@bill-the-cat> (raw)
In-Reply-To: <CAPnjgZ28HskiFDBDa=s_k6=WNoPfWu88bAaYCY7ew8dcYXW=aQ@mail.gmail.com>

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On Tue, Nov 07, 2023 at 01:10:44AM +0000, Simon Glass wrote:
> Hi Tom,
> 
> On Mon, 6 Nov 2023 at 13:46, Tom Rini <trini@konsulko.com> wrote:
> >
> > On Mon, Nov 06, 2023 at 01:38:39PM -0700, Simon Glass wrote:
> > > Hi Andre,
> > >
> > > On Mon, 6 Nov 2023 at 10:26, Andre Przywara <andre.przywara@arm.com> wrote:
> > > >
> > > > On Sat, 4 Nov 2023 19:45:06 +0000
> > > > Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > Hi,
> > > >
> > > > > On Sat, 4 Nov 2023 at 17:13, Andre Przywara <andre.przywara@arm.com> wrote:
> > > > > >
> > > > > > On Fri, 3 Nov 2023 13:38:58 -0600
> > > > > > Simon Glass <sjg@chromium.org> wrote:
> > > > > >
> > > > > > Hi Simon,
> > > > > >
> > > > > > > Hi Heinrich,
> > > > > > >
> > > > > > > On Wed, 1 Nov 2023 at 14:20, Heinrich Schuchardt
> > > > > > > <heinrich.schuchardt@canonical.com> wrote:
> > > > > > > >
> > > > > > > > On 11/1/23 19:05, Andre Przywara wrote:
> > > > > > > > > On Tue, 31 Oct 2023 14:55:50 +0200
> > > > > > > > > Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote:
> > > > > > > > >
> > > > > > > > > Hi Heinrich,
> > > > > > > > >
> > > > > > > > >> The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
> > > > > > > > >> provides an interface to a physical entropy source.
> > > > > > > > >>
> > > > > > > > >> A RNG driver based on the seed CSR is provided. It depends on
> > > > > > > > >> mseccfg.sseed being set in the SBI firmware.
> > > > > > > > >
> > > > > > > > > As you might have seen, I added a similar driver for the respective Arm
> > > > > > > > > functionality:
> > > > > > > > > https://lore.kernel.org/u-boot/20230830113230.3925868-1-andre.przywara@arm.com/
> > > > > > > > >
> > > > > > > > > And I see that you seem to use the same mechanism to probe and init the
> > > > > > > > > driver: U_BOOT_DRVINFO and fail in probe() if the feature is not
> > > > > > > > > implemented.
> > > > > > > > > One downside of this approach is that the driver is always loaded (and
> > > > > > > > > visible in the DM tree), even with the feature not being available.
> > > > > > > > > That doesn't seem too much of a problem on the first glance, but it
> > > > > > > > > occupies a device number, and any subsequent other DM_RNG devices
> > > > > > > > > (like virtio-rng) typically get higher device numbers. So without
> > > > > > > > > the feature, but with virtio-rng, I get:
> > > > > > > > > VExpress64# rng 0
> > > > > > > > > No RNG device
> > > > > > >
> > > > > > > Why do we get this? If the device is not there, the bind() function
> > > > > > > can return -ENODEV
> > > > > > >
> > > > > > > I see this in U-Boot:
> > > > > > >
> > > > > > > U_BOOT_DRVINFO(cpu_arm_rndr) = {
> > > > > > >
> > > > > > > We should not use this.
> > > > > >
> > > > > > Agreed.
> > > > > >
> > > > > > > Use the devicetree.
> > > > > >
> > > > > > No, this is definitely not something for the DT, at least not on ARM.
> > > > > > It's perfectly discoverable via the architected CPU ID registers.
> > > > > > Similar to PCI and USB devices, which we don't probe via the DT as well.
> > > > > >
> > > > > > It's arguably not proper "driver" material per se, as I've argued before, but
> > > > > > it's the simplest solution and fits in nicely otherwise.
> > > > > >
> > > > > > I was wondering if it might be something for UCLASS_CPU, something like
> > > > > > a "CPU feature bus": to let devices register on one on the many CPU
> > > > > > features (instead of compatible strings), then only bind() those
> > > > > > drivers it the respective bit is set.
> > > > > >
> > > > > > Does that make sense? Would that be doable without boiling the ocean?
> > > > > > As I don't know if we see many users apart from this.
> > > > >
> > > > > I have seen this so many times, where people want to avoid putting
> > > > > things in the DT and then are surprised that everything is difficult,
> > > > > broken and confusing. Why not just follow the rules? It is not just
> > > > > about whether we can avoid it, etc. It is about how devices fit
> > > > > together cohesively in the system, and how U-Boot operates.
> > > >
> > > > A devicetree is only for peripherals *that cannot be located by probing*.
> > >
> > > I have to stop you there. It absolutely is not limited to that.
> >
> > It is limited to that if we're going to keep using the device trees that
> > Linux uses. Full stop. There's not really wiggle room there either.
> 
> That is really the problem, I agree.

And we need to accept that, and what is/isn't something that we can
expect every board developer to have to tweak on top of this.

Heck, maybe part of the issue here is that devicetree-the-spec and
devicetree-the-linux-kernel-input need a little differentiation and some
official statement along the lines of "just because X can be in the
device tree does not mean that X will be defined in the device tree, if
it can be detected in some other reliable manner" for the latter.

> But I would be happy with a u-boot.dtsi file to resolve this, while we
> wait. I believe a binding makes sense in this case.

We don't need a binding, we can easily check at run-time. We only barely
have to worry about run-time failing (yes, QEMU could be fired up with a
model that lacks it, or some future change, and it's cheap to check). I
would say we could use the cpu compatible as a binding, but I don't want
to then have to add a bootph property to that. And the RISC-V example
makes it even clearer that this is not a binding thing.

I do not want a binding here that we just don't upstream because it will
make life harder for everyone else that's adding new platforms to get
the feature to work. Or people won't get it to work and instead add new
code that they most likely didn't need to, per drivers/timer/ today.

I'll let security people argue on what level of RNG (and so perhaps RNG
choice on systems that have more than one source available) devices need
to be present. But I think drivers/timer/ is the better example of
needing to just have the source present, with minimal run-time checking
(since it's a feature of the CPU).

-- 
Tom

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  reply	other threads:[~2023-11-07 19:30 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-31 12:55 [PATCH v3 0/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension Heinrich Schuchardt
2023-10-31 12:55 ` [PATCH v3 1/2] riscv: allow resume after exception Heinrich Schuchardt
2023-11-01  8:55   ` Leo Liang
2023-10-31 12:55 ` [PATCH v3 2/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension Heinrich Schuchardt
2023-11-01 17:05 ` [PATCH v3 0/2] " Andre Przywara
2023-11-01 17:16   ` Sean Anderson
2023-11-01 17:49     ` Andre Przywara
2023-11-01 18:20       ` Sean Anderson
2023-11-01 20:20   ` Heinrich Schuchardt
2023-11-03 19:38     ` Simon Glass
2023-11-04 17:12       ` Andre Przywara
2023-11-04 19:45         ` Simon Glass
2023-11-04 20:36           ` Heinrich Schuchardt
2023-11-04 22:58             ` Simon Glass
2023-11-06 17:26           ` Andre Przywara
2023-11-06 20:13             ` Tom Rini
2023-11-06 20:38             ` Simon Glass
2023-11-06 20:46               ` Tom Rini
2023-11-07  1:10                 ` Simon Glass
2023-11-07 19:30                   ` Tom Rini [this message]
2023-11-07 21:52                     ` Rob Herring
2023-11-07 22:10                       ` Tom Rini
2023-11-07 22:27                         ` Conor Dooley
2023-11-07 22:38                           ` Tom Rini
2023-11-07 22:51                             ` Simon Glass
2023-11-07 23:14                               ` Tom Rini
2023-11-07 23:12                             ` Conor Dooley
2023-11-07 23:23                               ` Tom Rini
2023-11-08  0:29                                 ` Conor Dooley
2023-11-08  0:34                                   ` Tom Rini
2023-11-08 14:23                                     ` Heinrich Schuchardt
2023-11-08 14:37                                       ` Tom Rini
2023-11-08 15:25                                         ` Heinrich Schuchardt
2023-11-08 16:44                                           ` Tom Rini
2023-11-08 17:10                                             ` Heinrich Schuchardt
2023-11-08 17:38                               ` Palmer Dabbelt
2023-11-10 11:50                                 ` Simon Glass
2023-11-06 21:53               ` Andre Przywara
2023-11-07  1:08                 ` Simon Glass
2023-11-07 11:27                   ` Andre Przywara
2023-11-07 12:22                     ` Simon Glass
2023-11-07 15:12                       ` Andre Przywara
2023-11-07 22:03                         ` Tom Rini
2023-11-08  4:24                         ` Simon Glass
2023-11-08  7:11                           ` Ilias Apalodimas
2023-11-07 21:53                       ` Tom Rini
2023-11-07 21:24                     ` Tom Rini
2023-11-06 16:46         ` Tom Rini
2023-11-06 17:24           ` Simon Glass
2023-11-06 17:45           ` Andre Przywara

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