Re: [PATCH v3 0/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension

[Tom Rini <trini@konsulko.com>]

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On Tue, Nov 07, 2023 at 11:27:08AM +0000, Andre Przywara wrote:
> On Tue, 7 Nov 2023 01:08:15 +0000
> Simon Glass <sjg@chromium.org> wrote:
> 
> Hi Simon,
> 
> > On Mon, 6 Nov 2023 at 21:55, Andre Przywara <andre.przywara@arm.com> wrote:
> > >
> > > On Mon, 6 Nov 2023 13:38:39 -0700
> > > Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Hi Simon,
> > >  
> > > > On Mon, 6 Nov 2023 at 10:26, Andre Przywara <andre.przywara@arm.com> wrote:  
> > > > >
> > > > > On Sat, 4 Nov 2023 19:45:06 +0000
> > > > > Simon Glass <sjg@chromium.org> wrote:
> > > > >
> > > > > Hi,
> > > > >  
> > > > > > On Sat, 4 Nov 2023 at 17:13, Andre Przywara <andre.przywara@arm.com> wrote:  
> > > > > > >
> > > > > > > On Fri, 3 Nov 2023 13:38:58 -0600
> > > > > > > Simon Glass <sjg@chromium.org> wrote:
> > > > > > >
> > > > > > > Hi Simon,
> > > > > > >  
> > > > > > > > Hi Heinrich,
> > > > > > > >
> > > > > > > > On Wed, 1 Nov 2023 at 14:20, Heinrich Schuchardt
> > > > > > > > <heinrich.schuchardt@canonical.com> wrote:  
> > > > > > > > >
> > > > > > > > > On 11/1/23 19:05, Andre Przywara wrote:  
> > > > > > > > > > On Tue, 31 Oct 2023 14:55:50 +0200
> > > > > > > > > > Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote:
> > > > > > > > > >
> > > > > > > > > > Hi Heinrich,
> > > > > > > > > >  
> > > > > > > > > >> The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
> > > > > > > > > >> provides an interface to a physical entropy source.
> > > > > > > > > >>
> > > > > > > > > >> A RNG driver based on the seed CSR is provided. It depends on
> > > > > > > > > >> mseccfg.sseed being set in the SBI firmware.  
> > > > > > > > > >
> > > > > > > > > > As you might have seen, I added a similar driver for the respective Arm
> > > > > > > > > > functionality:
> > > > > > > > > > https://lore.kernel.org/u-boot/20230830113230.3925868-1-andre.przywara@arm.com/
> > > > > > > > > >
> > > > > > > > > > And I see that you seem to use the same mechanism to probe and init the
> > > > > > > > > > driver: U_BOOT_DRVINFO and fail in probe() if the feature is not
> > > > > > > > > > implemented.
> > > > > > > > > > One downside of this approach is that the driver is always loaded (and
> > > > > > > > > > visible in the DM tree), even with the feature not being available.
> > > > > > > > > > That doesn't seem too much of a problem on the first glance, but it
> > > > > > > > > > occupies a device number, and any subsequent other DM_RNG devices
> > > > > > > > > > (like virtio-rng) typically get higher device numbers. So without
> > > > > > > > > > the feature, but with virtio-rng, I get:
> > > > > > > > > > VExpress64# rng 0
> > > > > > > > > > No RNG device  
> > > > > > > >
> > > > > > > > Why do we get this? If the device is not there, the bind() function
> > > > > > > > can return -ENODEV
> > > > > > > >
> > > > > > > > I see this in U-Boot:
> > > > > > > >
> > > > > > > > U_BOOT_DRVINFO(cpu_arm_rndr) = {
> > > > > > > >
> > > > > > > > We should not use this.  
> > > > > > >
> > > > > > > Agreed.
> > > > > > >  
> > > > > > > > Use the devicetree.  
> > > > > > >
> > > > > > > No, this is definitely not something for the DT, at least not on ARM.
> > > > > > > It's perfectly discoverable via the architected CPU ID registers.
> > > > > > > Similar to PCI and USB devices, which we don't probe via the DT as well.
> > > > > > >
> > > > > > > It's arguably not proper "driver" material per se, as I've argued before, but
> > > > > > > it's the simplest solution and fits in nicely otherwise.
> > > > > > >
> > > > > > > I was wondering if it might be something for UCLASS_CPU, something like
> > > > > > > a "CPU feature bus": to let devices register on one on the many CPU
> > > > > > > features (instead of compatible strings), then only bind() those
> > > > > > > drivers it the respective bit is set.
> > > > > > >
> > > > > > > Does that make sense? Would that be doable without boiling the ocean?
> > > > > > > As I don't know if we see many users apart from this.  
> > > > > >
> > > > > > I have seen this so many times, where people want to avoid putting
> > > > > > things in the DT and then are surprised that everything is difficult,
> > > > > > broken and confusing. Why not just follow the rules? It is not just
> > > > > > about whether we can avoid it, etc. It is about how devices fit
> > > > > > together cohesively in the system, and how U-Boot operates.  
> > > > >
> > > > > A devicetree is only for peripherals *that cannot be located by probing*.  
> > > >
> > > > I have to stop you there. It absolutely is not limited to that.  
> > >
> > > I am very sorry, but I - (and seemingly everyone else in the kernel DT
> > > community?) - seem to disagree here.  
> > 
> > Really? Where is that even coming from? Certainly not the DT spec.
> 
> It seems to be common agreement between devicetree folks, and I find it in
> one of Frank Roward's slidedeck about devicetree in the early days
> (2015ish). But indeed this should be added to official documents.
> I poked some people to get this sorted.

And it both dates back further still than that, less has always been
more is a phrase that can apply to Linux Kernel device trees for
forever. And like I put in another thread today, yes, an official
declaration that "device trees for the Linux Kernel" are not the same as
"semantically valid and conceptually strictly the hardware". As they
aren't, and that's fine, and will make life clearer moving forward.

> > > > > Which are traditionally most peripherals in non-server Arm SoCs. While I
> > > > > do love the DT, the best DT node is the one you don't need.  
> > > >
> > > > We need it in U-Boot, at least.
> > > >
> > > > I'll send a patch with a warning on U_BOOT_DRVINFO() as it seems that
> > > > some people did not see the header-file comment.  
> > >
> > > Fair enough.
> > >  
> > > > Let's just stop this discussion and instead talk about the binding we need.  
> > >
> > > Alright, if that is your decision, I will send a patch to revert
> > > that "driver". There will never be a binding for a CPU instruction
> > > discoverable by the architected CPU ID register.  
> > 
> > That statement just mystifies me. Why not just send a binding? Even
> > the people that complain that DT should only describe hardware will be
> > happy with it.
> > 
> > The code you sent should have been a clue that you need to know
> > whether the feature is present:
> 
> Ah, sorry, I sense some misunderstanding: I was arguing about the ARM RNDR
> driver. The Arm architecture manual describes the FEAT_RNG feature as
> perfectly discoverable, in a clean way, without any risk or further
> knowledge about the platform.
> 
> This thread here was originally about the RISC-V driver (written by
> Heinrich), where the situation is slightly different: while there seem to
> be CSRs to discover CPU features, this is apparently not the case for every
> instruction. So Heinrich did some probing, testing for an illegal
> instruction, which honestly still sounds better than a DT node to me.
> 
> > +       /* Check if reading seed leads to interrupt */
> > +       set_resume(&resume);
> > +       ret = setjmp(resume.jump);
> > +       if (ret)
> > +               log_debug("Exception %ld reading seed CSR\n", resume.code);
> > +       else
> > +               val = read_seed();
> > +       set_resume(NULL);
> > +       if (ret)
> > +               return -ENODEV;
> > 
> > I have never seen code like that in a driver. Please let's just have
> > the binding discussion with the Linux people and hopefully they will
> > see reason.
> 
> For the RISC-V case: maybe. But there is already a (newish) binding to list
> CPU features in the DT:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/extensions.yaml
> It's just not a normal device node binding, with a compatible string,
> instead a string list inside each CPU's node.

And Simon, you may find it interesting to get involved there and see
what is / isn't supposed to work or intended to work, in that case.

> So one possibility would be some connector code that parses that list
> and looks for drivers having registered? Like a CPU bus, I think Sean
> proposed something like this earlier. Or we ditch the idea of this being a
> regular driver in the first place, instead go with a "CPU entropy
> instruction abstraction".
> 
> But for Arm it's a different story.

In terms of U-Boot design, yes, I'm not entirely sure what's best as
another part of the design needs to be that we make abstractions only
when we need them. Maybe RNG needs a bit more as maybe user (device
designers) need better strength in some cases rather than others. But
even then we should still leverage what we know can and cannot be true
at build time.

> > > I had some gripes with that "driver" in the first place, but it was so
> > > temptingly simple and fit in so nicely, for instance into the UEFI
> > > entropy service without even touching that code, that I couldn't resist
> > > to just try it. And it actually solved a nasty problem for us, where
> > > the kernel boot was stuck for minutes waiting for enough entropy to ...
> > > let a script create a random filename ;-)
> > > But we also have virtio-rng, so are not limited to the instructions.
> > >
> > > But well, I guess I will just bite the bullet and go along the proper
> > > route and create some RNG instruction abstraction, as sketched in that
> > > other email.  
> > 
> > I don't know what that is.
> 
> That's what Tom and I were talking about earlier: 
> ... "a simple get_cpu_random() function, implemented per architecture, and
> with some kind of success flag, should be easy enough to do. Then either the users
> (UEFI?) explicitly call this before trying UCLASS_RNG, or we wrap this for
> every RNG user."

Seeing what's right for exposing to UEFI is another question, disjoint
from just having an RNG available.

> > In the other email I proposed a binding for this, so I hope that can
> > make progress.
> 
> I don't think we need a new DT binding for RISC-V, instead lean on
> riscv,isa-extensions.

Perhaps even then we don't _need_ to be doing that because we're making
binaries that I suspect won't run on platforms that lack the ISA. And so
this is partly a question for the U-Boot riscv people (who are at a
conference this week I believe). But if we just built a binary that will
only run on a core with the Zbb ISA it'd be pretty silly for us to then
run-time check if we have Zbb, since if we don't we wouldn't be there to
start with.

-- 
Tom

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