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From: Tom Rini <trini@konsulko.com>
To: Simon Glass <sjg@chromium.org>
Cc: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	Andre Przywara <andre.przywara@arm.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Xiang W <merlew4n6@gmail.com>,
	Chanho Park <chanho61.park@samsung.com>,
	Sughosh Ganu <sughosh.ganu@linaro.org>,
	u-boot@lists.denx.de, Peter Hoyes <Peter.Hoyes@arm.com>,
	Alexey Romanov <avromanov@salutedevices.com>,
	Ilias Apalodimas <ilias.apalodimas@linaro.org>
Subject: Re: [PATCH v3 0/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension
Date: Tue, 7 Nov 2023 18:14:22 -0500	[thread overview]
Message-ID: <20231107231422.GV6601@bill-the-cat> (raw)
In-Reply-To: <CAPnjgZ0PqwCnm_Dn-ydR+VkN9qGU8FN-wy17802bQpGQrxTbPQ@mail.gmail.com>

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On Tue, Nov 07, 2023 at 03:51:21PM -0700, Simon Glass wrote:
> Hi,
> 
> On Tue, 7 Nov 2023 at 15:38, Tom Rini <trini@konsulko.com> wrote:
> >
> > On Tue, Nov 07, 2023 at 10:27:50PM +0000, Conor Dooley wrote:
> > > On Tue, Nov 07, 2023 at 05:10:23PM -0500, Tom Rini wrote:
> > >
> > >
> > > > further clarify or not
> > > > the RISC-V ISA thing that's elsewhere in this thread (and part of the
> > > > kernel, not a U-Boot thing).
> > >
> > > TBH, this a bit fragmented across threads, and as someone that hasn't
> > > been following it it's a bit difficult to tell exactly what is being
> > > asked for. Would someone be able to ask it as a direct question?
> >
> > Sorry for being unclear, and thanks for asking. What I think the U-Boot
> > community would like to know is, what is the device-tree based way to
> > know if a RISC-V platform has the Zbb extensions and so the RNG opcodes,
> > similar (in concept at least?) to the ARMv8.5 RNG feature.
> 
> Some more details (sorry) from your friendly devicetree and driver
> model maintainer:
> 
> - U-Boot models hardware (and other things) as devices in driver model [1]
> - U-Boot requires devices to be in the devicetree, with very limited
> exceptions [2]
> - Where multiple devices exist in a uclass, it is desirable to be able
> to number them [3]
> - Similarly it is useful to be able select a particular device, e.g.
> with a phandle [4]
> - U-Boot uses devicetree for configuration as it has no userspace

And I'm very specifically trying to NOT dive in to these particular
details and just find out how the accepted bindings for RISC-V are
intended to solve the question U-Boot has and in turn figure out what
U-Boot should do here. I'm not asking Conor how it should all fit in to
what U-Boot does, just how what's defined now can be used in this case.

-- 
Tom

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  reply	other threads:[~2023-11-07 23:14 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-31 12:55 [PATCH v3 0/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension Heinrich Schuchardt
2023-10-31 12:55 ` [PATCH v3 1/2] riscv: allow resume after exception Heinrich Schuchardt
2023-11-01  8:55   ` Leo Liang
2023-10-31 12:55 ` [PATCH v3 2/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension Heinrich Schuchardt
2023-11-01 17:05 ` [PATCH v3 0/2] " Andre Przywara
2023-11-01 17:16   ` Sean Anderson
2023-11-01 17:49     ` Andre Przywara
2023-11-01 18:20       ` Sean Anderson
2023-11-01 20:20   ` Heinrich Schuchardt
2023-11-03 19:38     ` Simon Glass
2023-11-04 17:12       ` Andre Przywara
2023-11-04 19:45         ` Simon Glass
2023-11-04 20:36           ` Heinrich Schuchardt
2023-11-04 22:58             ` Simon Glass
2023-11-06 17:26           ` Andre Przywara
2023-11-06 20:13             ` Tom Rini
2023-11-06 20:38             ` Simon Glass
2023-11-06 20:46               ` Tom Rini
2023-11-07  1:10                 ` Simon Glass
2023-11-07 19:30                   ` Tom Rini
2023-11-07 21:52                     ` Rob Herring
2023-11-07 22:10                       ` Tom Rini
2023-11-07 22:27                         ` Conor Dooley
2023-11-07 22:38                           ` Tom Rini
2023-11-07 22:51                             ` Simon Glass
2023-11-07 23:14                               ` Tom Rini [this message]
2023-11-07 23:12                             ` Conor Dooley
2023-11-07 23:23                               ` Tom Rini
2023-11-08  0:29                                 ` Conor Dooley
2023-11-08  0:34                                   ` Tom Rini
2023-11-08 14:23                                     ` Heinrich Schuchardt
2023-11-08 14:37                                       ` Tom Rini
2023-11-08 15:25                                         ` Heinrich Schuchardt
2023-11-08 16:44                                           ` Tom Rini
2023-11-08 17:10                                             ` Heinrich Schuchardt
2023-11-08 17:38                               ` Palmer Dabbelt
2023-11-10 11:50                                 ` Simon Glass
2023-11-06 21:53               ` Andre Przywara
2023-11-07  1:08                 ` Simon Glass
2023-11-07 11:27                   ` Andre Przywara
2023-11-07 12:22                     ` Simon Glass
2023-11-07 15:12                       ` Andre Przywara
2023-11-07 22:03                         ` Tom Rini
2023-11-08  4:24                         ` Simon Glass
2023-11-08  7:11                           ` Ilias Apalodimas
2023-11-07 21:53                       ` Tom Rini
2023-11-07 21:24                     ` Tom Rini
2023-11-06 16:46         ` Tom Rini
2023-11-06 17:24           ` Simon Glass
2023-11-06 17:45           ` Andre Przywara

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