[PATCH 0/4] riscv: sophgo: milkv_duo: add support for Milk-V Duo board

[PATCH 0/4] riscv: sophgo: milkv_duo: add support for Milk-V Duo board

[Kongyang Liu]

The Milk-V Duo board is built upon Sophgo's CV1800B SoC, featuring two
XuanTie C906 CPUs running at 1.0GHz and 700MHz, respectively.

This series introduces fundamental support for the Milk-V Duo board,
encompassing UART, CPU, and PLIC support. This ensures that U-Boot can
operate in serial console mode.


Kongyang Liu (4):
  riscv: sophgo: milkv_duo: initial support added
  riscv: dts: sophgo: Add basic device tree for Milk-V Duo board
  configs: milkv_duo_defconfig: Add initial config
  doc: sophgo: milkv_duo: document Milk-V Duo board

 arch/riscv/Kconfig                   |   4 +
 arch/riscv/dts/Makefile              |   1 +
 arch/riscv/dts/cv1800b-milkv-duo.dts |  38 +++++++++
 arch/riscv/dts/cv1800b.dtsi          | 123 +++++++++++++++++++++++++++
 board/sophgo/milkv_duo/Kconfig       |  28 ++++++
 board/sophgo/milkv_duo/MAINTAINERS   |   6 ++
 board/sophgo/milkv_duo/Makefile      |   5 ++
 board/sophgo/milkv_duo/board.c       |   9 ++
 configs/milkv_duo_defconfig          |  24 ++++++
 doc/board/index.rst                  |   1 +
 doc/board/sophgo/index.rst           |   8 ++
 doc/board/sophgo/milkv_duo.rst       |  50 +++++++++++
 include/configs/milkv_duo.h          |  16 ++++
 13 files changed, 313 insertions(+)
 create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts
 create mode 100644 arch/riscv/dts/cv1800b.dtsi
 create mode 100644 board/sophgo/milkv_duo/Kconfig
 create mode 100644 board/sophgo/milkv_duo/MAINTAINERS
 create mode 100644 board/sophgo/milkv_duo/Makefile
 create mode 100644 board/sophgo/milkv_duo/board.c
 create mode 100644 configs/milkv_duo_defconfig
 create mode 100644 doc/board/sophgo/index.rst
 create mode 100644 doc/board/sophgo/milkv_duo.rst
 create mode 100644 include/configs/milkv_duo.h

-- 
2.41.0

[PATCH 1/4] riscv: sophgo: milkv_duo: initial support added

[Kongyang Liu]

Add support for Sophgo's Milk-V Duo board, only minimal device tree and
serial console are enabled, and it can boot via vendor first stage
bootloader.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>

---

 arch/riscv/Kconfig                 |  4 ++++
 board/sophgo/milkv_duo/Kconfig     | 28 ++++++++++++++++++++++++++++
 board/sophgo/milkv_duo/MAINTAINERS |  6 ++++++
 board/sophgo/milkv_duo/Makefile    |  5 +++++
 board/sophgo/milkv_duo/board.c     |  9 +++++++++
 include/configs/milkv_duo.h        | 16 ++++++++++++++++
 6 files changed, 68 insertions(+)
 create mode 100644 board/sophgo/milkv_duo/Kconfig
 create mode 100644 board/sophgo/milkv_duo/MAINTAINERS
 create mode 100644 board/sophgo/milkv_duo/Makefile
 create mode 100644 board/sophgo/milkv_duo/board.c
 create mode 100644 include/configs/milkv_duo.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6d0d812ddb..de99ce3a28 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,9 @@ config TARGET_ANDES_AE350
 config TARGET_MICROCHIP_ICICLE
 	bool "Support Microchip PolarFire-SoC Icicle Board"
 
+config TARGET_MILKV_DUO
+	bool "Support Milk-v Duo Board"
+
 config TARGET_OPENPITON_RISCV64
 	bool "Support RISC-V cores on OpenPiton SoC"
 
@@ -80,6 +83,7 @@ source "board/openpiton/riscv64/Kconfig"
 source "board/sifive/unleashed/Kconfig"
 source "board/sifive/unmatched/Kconfig"
 source "board/sipeed/maix/Kconfig"
+source "board/sophgo/milkv_duo/Kconfig"
 source "board/starfive/visionfive2/Kconfig"
 source "board/thead/th1520_lpi4a/Kconfig"
 
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
new file mode 100644
index 0000000000..2a458f291c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_MILKV_DUO
+
+config SYS_BOARD
+	default "milkv_duo"
+
+config SYS_VENDOR
+	default "sophgo"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "milkv_duo"
+
+config TEXT_BASE
+	default 0x80200000
+
+config ENV_SIZE
+	default 0x20000
+
+config ENV_SECT_SIZE
+	default 0x40000
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select GENERIC_RISCV
+
+endif
diff --git a/board/sophgo/milkv_duo/MAINTAINERS b/board/sophgo/milkv_duo/MAINTAINERS
new file mode 100644
index 0000000000..651a0592f7
--- /dev/null
+++ b/board/sophgo/milkv_duo/MAINTAINERS
@@ -0,0 +1,6 @@
+Milk-V Duo
+M:	Kongyang Liu <seashell11234455@gmail.com>
+S:	Maintained
+F:	board/sophgo/milkv_duo/
+F:	configs/milkv_duo_defconfig
+F:	doc/board/sophgo/milkv_duo.rst
diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile
new file mode 100644
index 0000000000..a087013f5c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+
+obj-y := board.o
diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
new file mode 100644
index 0000000000..eaa47be173
--- /dev/null
+++ b/board/sophgo/milkv_duo/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/include/configs/milkv_duo.h b/include/configs/milkv_duo.h
new file mode 100644
index 0000000000..dd1d146c50
--- /dev/null
+++ b/include/configs/milkv_duo.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_SYS_SDRAM_BASE         0x80000000
+
+#define CFG_EXTRA_ENV_SETTINGS                 \
+	"consoledev=ttyS0"                         \
+	"baudrate=115200\0"                        \
+
+#endif /* __CONFIG_H */
-- 
2.41.0

[PATCH 2/4] riscv: dts: sophgo: Add basic device tree for Milk-V Duo board

[Kongyang Liu]

Import device tree from Linux kernel to add basic support for CPU, PLIC,
UART and Timer. The name cv1800b in the filename represent the chip used
on Milk-V Duo board.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
---

 arch/riscv/dts/Makefile              |   1 +
 arch/riscv/dts/cv1800b-milkv-duo.dts |  38 +++++++++
 arch/riscv/dts/cv1800b.dtsi          | 123 +++++++++++++++++++++++++++
 3 files changed, 162 insertions(+)
 create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts
 create mode 100644 arch/riscv/dts/cv1800b.dtsi

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index be6c8a4227..b9e1678676 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts b/arch/riscv/dts/cv1800b-milkv-duo.dts
new file mode 100644
index 0000000000..3af9e34b3b
--- /dev/null
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "cv1800b.dtsi"
+
+/ {
+	model = "Milk-V Duo";
+	compatible = "milkv,duo", "sophgo,cv1800b";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x3f40000>;
+	};
+};
+
+&osc {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
new file mode 100644
index 0000000000..df40e87ee0
--- /dev/null
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "sophgo,cv1800b";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <25000000>;
+
+		cpu0: cpu@0 {
+			compatible = "thead,c906", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <512>;
+			d-cache-size = <65536>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			mmu-type = "riscv,sv39";
+			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+	};
+
+	osc: oscillator {
+		compatible = "fixed-clock";
+		clock-output-names = "osc_25m";
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		dma-noncoherent;
+		ranges;
+
+		uart0: serial@4140000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x04140000 0x100>;
+			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart1: serial@4150000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x04150000 0x100>;
+			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart2: serial@4160000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x04160000 0x100>;
+			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@4170000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x04170000 0x100>;
+			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart4: serial@41c0000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x041c0000 0x100>;
+			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		plic: interrupt-controller@70000000 {
+			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
+			reg = <0x70000000 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			riscv,ndev = <101>;
+		};
+
+		clint: timer@74000000 {
+			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
+			reg = <0x74000000 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+		};
+	};
+};
-- 
2.41.0

[PATCH 3/4] configs: milkv_duo_defconfig: Add initial config

[Kongyang Liu]

Add basic config for Milk-V Duo board which make it capable of booting into
serial console.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
---

 configs/milkv_duo_defconfig | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 configs/milkv_duo_defconfig

diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig
new file mode 100644
index 0000000000..c4782639ef
--- /dev/null
+++ b/configs/milkv_duo_defconfig
@@ -0,0 +1,24 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x820000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000
+CONFIG_DEFAULT_DEVICE_TREE="cv1800b-milkv-duo"
+CONFIG_IDENT_STRING="milkv_duo"
+CONFIG_SYS_LOAD_ADDR=0x80080000
+CONFIG_TARGET_MILKV_DUO=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="milkv_duo# "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=544
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
+# CONFIG_EFI_LOADER is not set
-- 
2.41.0

[PATCH 4/4] doc: sophgo: milkv_duo: document Milk-V Duo board

[Kongyang Liu]

Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
---

 doc/board/index.rst            |  1 +
 doc/board/sophgo/index.rst     |  8 ++++++
 doc/board/sophgo/milkv_duo.rst | 50 ++++++++++++++++++++++++++++++++++
 3 files changed, 59 insertions(+)
 create mode 100644 doc/board/sophgo/index.rst
 create mode 100644 doc/board/sophgo/milkv_duo.rst

diff --git a/doc/board/index.rst b/doc/board/index.rst
index 531e547e7e..a0bd534742 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -45,6 +45,7 @@ Board-specific doc
    sifive/index
    sipeed/index
    socionext/index
+   sophgo/index
    st/index
    starfive/index
    ste/index
diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst
new file mode 100644
index 0000000000..e097afdac6
--- /dev/null
+++ b/doc/board/sophgo/index.rst
@@ -0,0 +1,8 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sophgo
+======
+.. toctree::
+   :maxdepth: 1
+
+   milkv_duo
diff --git a/doc/board/sophgo/milkv_duo.rst b/doc/board/sophgo/milkv_duo.rst
new file mode 100644
index 0000000000..b63304b510
--- /dev/null
+++ b/doc/board/sophgo/milkv_duo.rst
@@ -0,0 +1,50 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Milk-V Duo
+==========
+
+CV1800B RISC-V SoC
+------------------
+The CV1800B is a high-performance, low-power 1+1 64-bit RISC-V SoC from Sophgo.
+
+Mainline support
+----------------
+The support for following drivers are already enabled:
+1. ns16550 UART Driver.
+
+Building
+~~~~~~~~
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: console
+
+   export CROSS_COMPILE=<riscv64 toolchain prefix>
+   cd <U-Boot-dir>
+   make milkv_duo_defconfig
+   make
+
+This will generate u-boot-dtb.bin
+
+Booting
+~~~~~~~
+Currently, we rely on vendor FSBL(First Stage Boot Loader) to initialize the
+clock and load the u-boot image, then bootup from it.
+
+Sample boot log from Milk-V Duo board
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. code-block:: none
+
+   U-Boot 2024.01-rc5-00010-g51965baa36 (Dec 28 2023 - 13:15:53 +0800)milkv_duo
+
+   DRAM:  63.3 MiB
+   Core:  10 devices, 8 uclasses, devicetree: separate
+   Loading Environment from nowhere... OK
+   In:    serial@4140000
+   Out:   serial@4140000
+   Err:   serial@4140000
+   Net:   No ethernet found.
+   milkv_duo# cpu detail
+     0: cpu@0      rv64imafdc
+      ID = 0, freq = 0 Hz: L1 cache, MMU
+   milkv_duo#
-- 
2.41.0

Re: [PATCH 1/4] riscv: sophgo: milkv_duo: initial support added

[Tom Rini]

[-- Attachment #1: Type: text/plain, Size: 1928 bytes --]

On Sun, Jan 07, 2024 at 07:27:07PM +0800, Kongyang Liu wrote:

> Add support for Sophgo's Milk-V Duo board, only minimal device tree and
> serial console are enabled, and it can boot via vendor first stage
> bootloader.
> 
> Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
> 
> ---
> 
>  arch/riscv/Kconfig                 |  4 ++++
>  board/sophgo/milkv_duo/Kconfig     | 28 ++++++++++++++++++++++++++++
>  board/sophgo/milkv_duo/MAINTAINERS |  6 ++++++
>  board/sophgo/milkv_duo/Makefile    |  5 +++++
>  board/sophgo/milkv_duo/board.c     |  9 +++++++++
>  include/configs/milkv_duo.h        | 16 ++++++++++++++++

The defconfig patch should be folded in to this one.

[snip]
> diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
> new file mode 100644
> index 0000000000..eaa47be173
> --- /dev/null
> +++ b/board/sophgo/milkv_duo/board.c
> @@ -0,0 +1,9 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
> + */
> +
> +int board_init(void)
> +{
> +	return 0;
> +}

Shouldn't you enable caches here?

> diff --git a/include/configs/milkv_duo.h b/include/configs/milkv_duo.h
> new file mode 100644
> index 0000000000..dd1d146c50
> --- /dev/null
> +++ b/include/configs/milkv_duo.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
> + *
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CFG_SYS_SDRAM_BASE         0x80000000
> +
> +#define CFG_EXTRA_ENV_SETTINGS                 \
> +	"consoledev=ttyS0"                         \
> +	"baudrate=115200\0"                        \

We shouldn't need to set baudrate, it will be handled for us. Is
consoledev something that must be set? Can it all be done in a plain
text environment anyhow? Thanks.

-- 
Tom

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Re: [PATCH 1/4] riscv: sophgo: milkv_duo: initial support added

[刘孔阳]

Tom Rini <trini@konsulko.com> 于2024年1月9日周二 04:42写道：
>
> On Sun, Jan 07, 2024 at 07:27:07PM +0800, Kongyang Liu wrote:
>
> > Add support for Sophgo's Milk-V Duo board, only minimal device tree and
> > serial console are enabled, and it can boot via vendor first stage
> > bootloader.
> >
> > Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
> >
> > ---
> >
> >  arch/riscv/Kconfig                 |  4 ++++
> >  board/sophgo/milkv_duo/Kconfig     | 28 ++++++++++++++++++++++++++++
> >  board/sophgo/milkv_duo/MAINTAINERS |  6 ++++++
> >  board/sophgo/milkv_duo/Makefile    |  5 +++++
> >  board/sophgo/milkv_duo/board.c     |  9 +++++++++
> >  include/configs/milkv_duo.h        | 16 ++++++++++++++++
>
> The defconfig patch should be folded in to this one.
>
I will fold it in next version.

> [snip]
> > diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
> > new file mode 100644
> > index 0000000000..eaa47be173
> > --- /dev/null
> > +++ b/board/sophgo/milkv_duo/board.c
> > @@ -0,0 +1,9 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
> > + */
> > +
> > +int board_init(void)
> > +{
> > +     return 0;
> > +}
>
> Shouldn't you enable caches here?
>
Enable caches will cause other problems, and I will implement it
in subsequent patches.

> > diff --git a/include/configs/milkv_duo.h b/include/configs/milkv_duo.h
> > new file mode 100644
> > index 0000000000..dd1d146c50
> > --- /dev/null
> > +++ b/include/configs/milkv_duo.h
> > @@ -0,0 +1,16 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
> > + *
> > + */
> > +
> > +#ifndef __CONFIG_H
> > +#define __CONFIG_H
> > +
> > +#define CFG_SYS_SDRAM_BASE         0x80000000
> > +
> > +#define CFG_EXTRA_ENV_SETTINGS                 \
> > +     "consoledev=ttyS0"                         \
> > +     "baudrate=115200\0"                        \
>
> We shouldn't need to set baudrate, it will be handled for us. Is
> consoledev something that must be set? Can it all be done in a plain
> text environment anyhow? Thanks.
>
I will check and detele it if it is unnecessary.

Best regards
Kongyang Liu
> --
> Tom