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[209.91.167.254]) by smtp.gmail.com with ESMTPSA id p13-20020a0cfd8d000000b0067f2559fd5esm6144410qvr.34.2024.01.18.13.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jan 2024 13:00:37 -0800 (PST) Date: Thu, 18 Jan 2024 16:00:35 -0500 From: Trevor Woerner To: Jonas Karlman Cc: Kever Yang , Ramon Fried , Joe Hershberger , Simon Glass , Banglang Huang , u-boot@lists.denx.de Subject: Re: [PATCH 0/2] rockchip: Fix ethernet on Radxa ROCK Pi E v1.21 Message-ID: <20240118210035.GA17102@localhost> References: <20240118071949.927089-1-jonas@kwiboo.se> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20240118071949.927089-1-jonas@kwiboo.se> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Hi Jonas, On Thu 2024-01-18 @ 07:19:44 AM, Jonas Karlman wrote: > Ethernet on a Radxa ROCK Pi E v1.21 with a RTL8211F ethernet PHY > currently fails with the following message: > > Could not get PHY for ethernet@ff540000: addr -1 > > This happens because the ethernet PHY is never reset before a phy-id is > read back from the MDIO bus. > > This series fixes this issue by calling eth_phy_set_mdio_bus() from the > designware ethernet driver to issue a PHY reset before the phy_connect() > call. > > With the driver change and DM_ETH_PHY and PHY_REALTEK enabled the PHY > can be identified and etherent works: > > => mdio list > ethernet@ff540000: > 1 - RealTek RTL8211F <--> ethernet@ff540000 > > This was tested with and without the DM_MDIO option enabled. Decided to > leave it disabled in this series. This works great, thank you! As you suspected, both boards/PHYs work fine now work under Linux (in addition to U-Boot). Tested-By: Trevor Woerner > Jonas Karlman (2): > net: designware: Reset eth phy before phy connect > rockchip: rk3328-rock-pi-e: Enable DM_ETH_PHY and PHY_REALTEK > > configs/rock-pi-e-rk3328_defconfig | 2 ++ > drivers/net/designware.c | 7 +++++++ > 2 files changed, 9 insertions(+) > > -- > 2.43.0 >