[PATCH 0/4] Add New Devices for RGxx3

[PATCH 0/4] Add New Devices for RGxx3

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

This patch series is to clean up a few issues found with the RGxx3,
add support for a new device, and add a board specific ADC button
check routine to the SPL stage. The ADC button routine was part of
a previous patch series that was partially accepted, though making
the ADC button routine board generic was rejected by the Rockchip
maintainer.

Chris Morgan (4):
  arm: dts: rockchip: rk3566: Remove unnecessary clks from rgxx3
  board: rockchip: Add support for Powkiddy RGB10MAX3
  configs: Remove unnecessary options from RGxx3 config
  board: rockchip: Add early ADC button detect for RGxx3

 .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 --------
 arch/arm/dts/rk3566-anbernic-rgxx3.dts        | 16 ++++-
 board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c    | 72 +++++++++++++++++++
 configs/anbernic-rgxx3-rk3566_defconfig       | 15 ++--
 doc/board/anbernic/rgxx3.rst                  |  1 +
 5 files changed, 97 insertions(+), 38 deletions(-)

-- 
2.34.1

[PATCH 1/4] arm: dts: rockchip: rk3566: Remove unnecessary clks from rgxx3

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
Move the necessary defines to the RGxx3 main dts file.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 -------------------
 arch/arm/dts/rk3566-anbernic-rgxx3.dts        |  7 +++++
 2 files changed, 7 insertions(+), 31 deletions(-)

diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index f986e1941e..ef4f81500b 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -15,37 +15,6 @@
 	};
 };
 
-&cru {
-	assigned-clocks =
-			<&pmucru CLK_RTC_32K>,
-			<&pmucru PLL_PPLL>,
-			<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
-			<&cru PLL_GPLL>,
-			<&cru ACLK_BUS>, <&cru PCLK_BUS>,
-			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
-			<&cru HCLK_TOP>, <&cru PCLK_TOP>,
-			<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
-			<&cru CPLL_500M>, <&cru CPLL_333M>,
-			<&cru CPLL_250M>, <&cru CPLL_125M>,
-			<&cru CPLL_100M>, <&cru CPLL_62P5M>,
-			<&cru CPLL_50M>, <&cru CPLL_25M>;
-		assigned-clock-rates =
-			<32768>,
-			<200000000>,
-			<100000000>, <1000000000>,
-			<1188000000>,
-			<150000000>, <100000000>,
-			<500000000>, <400000000>,
-			<150000000>, <100000000>,
-			<300000000>, <150000000>,
-			<500000000>, <333333333>,
-			<250000000>, <125000000>,
-			<100000000>, <62500000>,
-			<50000000>, <25000000>;
-		assigned-clock-parents =
-			<&pmucru CLK_RTC32K_FRAC>;
-};
-
 &dsi_dphy0 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
index 404dddfafb..9e0aa9e63b 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
@@ -16,3 +16,10 @@
 		     "anbernic,rg353v", "anbernic,rg353vs",
 		     "anbernic,rg503", "rockchip,rk3566";
 };
+
+&cru {
+	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+	assigned-clock-rates = <32768>, <1200000000>,
+			       <200000000>, <241500000>;
+};
-- 
2.34.1

[PATCH 2/4] board: rockchip: Add support for Powkiddy RGB10MAX3

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Add support to the RGxx3 device for the Powkiddy RGB10MAX3. This device
is extremely similar to all the other devices and can use the same
bootloader with the same detection logic.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 arch/arm/dts/rk3566-anbernic-rgxx3.dts     | 9 ++++++---
 board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 8 ++++++++
 doc/board/anbernic/rgxx3.rst               | 1 +
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
index 9e0aa9e63b..c393c8d07a 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
@@ -12,9 +12,12 @@
  * set the correct dtb name for loading mainline Linux automatically.
  */
 	model = "RGXX3";
-	compatible = "anbernic,rg353m", "anbernic,rg353p",
-		     "anbernic,rg353v", "anbernic,rg353vs",
-		     "anbernic,rg503", "rockchip,rk3566";
+	compatible = "anbernic,rg-arc-d", "anbernic,rg-arc-s",
+		     "anbernic,rg353m", "anbernic,rg353p",
+		     "anbernic,rg353ps", "anbernic,rg353v",
+		     "anbernic,rg353vs", "anbernic,rg503",
+		     "powkiddy,rgb10max3", "powkiddy,rgb30",
+		     "powkiddy,rk2023", "rockchip,rk3566";
 };
 
 &cru {
diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
index d05502f67a..5c57b902d1 100644
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -50,6 +50,7 @@ enum rgxx3_device_id {
 	RGB30,
 	RK2023,
 	RGARCD,
+	RGB10MAX3,
 	/* Devices with duplicate ADC value */
 	RG353PS,
 	RG353VS,
@@ -107,6 +108,13 @@ static const struct rg3xx_model rg3xx_model_details[] = {
 		.fdtfile = DTB_DIR "rk3566-anbernic-rg-arc-d.dtb",
 		.detect_panel = 0,
 	},
+	[RGB10MAX3] = {
+		.adc_value = 765, /* Observed average from device */
+		.board = "rk3566-powkiddy-rgb10max3",
+		.board_name = "Powkiddy RGB10MAX3",
+		.fdtfile = DTB_DIR "rk3566-powkiddy-rgb10max3.dtb",
+		.detect_panel = 0,
+	},
 	/* Devices with duplicate ADC value */
 	[RG353PS] = {
 		.adc_value = 860, /* Observed average from device */
diff --git a/doc/board/anbernic/rgxx3.rst b/doc/board/anbernic/rgxx3.rst
index d159ed2f76..1e63e6951e 100644
--- a/doc/board/anbernic/rgxx3.rst
+++ b/doc/board/anbernic/rgxx3.rst
@@ -17,6 +17,7 @@ This allows U-Boot to boot the following Anbernic devices:
 Additionally, the following very similar non-Anbernic devices are also
 supported:
 
+ - Powkiddy RGB10MAX3
  - Powkiddy RGB30
  - Powkiddy RK2023
 
-- 
2.34.1

[PATCH 3/4] configs: Remove unnecessary options from RGxx3 config

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Based on feedback from the mailing list while adding support for a new
device (the Powkiddy X55), correct the config options for the RGxx3
as well to remove unnecessary drivers and increase the SPL stack size.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 configs/anbernic-rgxx3-rk3566_defconfig | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
index ed6643d9d4..d52a0d48f2 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -3,6 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
@@ -24,7 +25,9 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
@@ -32,7 +35,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_RNG_SEED=y
-CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x4000000
@@ -41,6 +44,7 @@ CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_POWER=y
 CONFIG_SPL_ATF=y
 CONFIG_CMD_PWM=y
 CONFIG_CMD_GPT=y
@@ -50,8 +54,10 @@ CONFIG_CMD_MMC=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 # CONFIG_NET is not set
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -67,13 +73,13 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_FAN53555=y
 CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_REGULATOR_RK8XX=y
-CONFIG_DM_REGULATOR_SCMI=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 # CONFIG_RAM_ROCKCHIP_DEBUG is not set
@@ -89,5 +95,6 @@ CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_REGEX=y
+# CONFIG_RSA is not set
 CONFIG_ERRNO_STR=y
 # CONFIG_EFI_LOADER is not set
-- 
2.34.1

[PATCH 4/4] board: rockchip: Add early ADC button detect for RGxx3

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Add ADC button detect for early SPL stage for RGxx3 device. This is
important because on at least the RG353P and RG353V a clk pin is not
exposed that would allow us to take the eMMC out of the boot path.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 64 ++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
index 5c57b902d1..099eea60c3 100644
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -6,12 +6,14 @@
 #include <abuf.h>
 #include <adc.h>
 #include <asm/io.h>
+#include <command.h>
 #include <display.h>
 #include <dm.h>
 #include <dm/lists.h>
 #include <env.h>
 #include <fdt_support.h>
 #include <linux/delay.h>
+#include <linux/iopoll.h>
 #include <mipi_dsi.h>
 #include <mmc.h>
 #include <panel.h>
@@ -19,6 +21,8 @@
 #include <stdlib.h>
 #include <video_bridge.h>
 
+#define BOOT_BROM_DOWNLOAD	0xef08a53c
+
 #define GPIO0_BASE		0xfdd60000
 #define GPIO4_BASE		0xfe770000
 #define GPIO_SWPORT_DR_L	0x0000
@@ -32,6 +36,14 @@
 
 #define GPIO_WRITEMASK(bits)	((bits) << 16)
 
+#define SARADC_BASE		0xfe720000
+#define SARADC_DATA		0x0000
+#define SARADC_STAS		0x0004
+#define SARADC_ADC_STATUS	BIT(0)
+#define SARADC_CTRL		0x0008
+#define SARADC_INPUT_SRC_MSK	0x7
+#define SARADC_POWER_CTRL	BIT(3)
+
 #define DTB_DIR			"rockchip/"
 
 struct rg3xx_model {
@@ -157,12 +169,64 @@ static const struct rg353_panel rg353_panel_details[] = {
 	},
 };
 
+/*
+ * The device has internal eMMC, and while some devices have an exposed
+ * clk pin you can ground to force a bypass not all devices do. As a
+ * result it may be possible for some devices to become a perma-brick
+ * if a corrupted TPL or SPL stage with a valid header is flashed to
+ * the internal eMMC. Add functionality to read ADC channel 0 (the func
+ * button) as early as possible in the boot process to provide some
+ * protection against this. If we ever get an open TPL stage, we should
+ * consider moving this function there.
+ */
+void read_func_button(void)
+{
+	int ret;
+	u32 reg;
+
+	/* Turn off SARADC to reset it. */
+	writel(0, (SARADC_BASE + SARADC_CTRL));
+
+	/* Enable channel 0 and power on SARADC. */
+	writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL),
+	       (SARADC_BASE + SARADC_CTRL));
+
+	/*
+	 * Wait for data to be ready. Use timeout of 20000us from
+	 * rockchip_saradc driver.
+	 */
+	ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg,
+				 !(reg & SARADC_ADC_STATUS), 20000);
+	if (ret) {
+		printf("ADC Timeout");
+		return;
+	}
+
+	/* Read the data from the SARADC. */
+	reg = readl((SARADC_BASE + SARADC_DATA));
+
+	/* Turn the SARADC back off so it's ready to be used again. */
+	writel(0, (SARADC_BASE + SARADC_CTRL));
+
+	/*
+	 * If the value is less than 30 the button is being pressed.
+	 * Reset the device back into Rockchip download mode.
+	 */
+	if (reg <= 30) {
+		printf("download key pressed, entering download mode...");
+		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
+		do_reset(NULL, 0, 0, NULL);
+	}
+};
+
 /*
  * Start LED very early so user knows device is on. Set color
  * to red.
  */
 void spl_board_init(void)
 {
+	read_func_button();
+
 	/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
 	writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
 	       (GPIO_C7 | GPIO_C6 | GPIO_C5),
-- 
2.34.1

Re: [PATCH 1/4] arm: dts: rockchip: rk3566: Remove unnecessary clks from rgxx3

[Kever Yang]

Hi Chris,

On 2024/2/6 02:58, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
> Move the necessary defines to the RGxx3 main dts file.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>

First of all, the dts should follow the one in mainline kernel;

and why you need to over write the cru in U-Boot for this board, I 
didn't see this change

in other boards.


Thanks,

- Kever

> ---
>   .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 -------------------
>   arch/arm/dts/rk3566-anbernic-rgxx3.dts        |  7 +++++
>   2 files changed, 7 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> index f986e1941e..ef4f81500b 100644
> --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> @@ -15,37 +15,6 @@
>   	};
>   };
>   
> -&cru {
> -	assigned-clocks =
> -			<&pmucru CLK_RTC_32K>,
> -			<&pmucru PLL_PPLL>,
> -			<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
> -			<&cru PLL_GPLL>,
> -			<&cru ACLK_BUS>, <&cru PCLK_BUS>,
> -			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
> -			<&cru HCLK_TOP>, <&cru PCLK_TOP>,
> -			<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
> -			<&cru CPLL_500M>, <&cru CPLL_333M>,
> -			<&cru CPLL_250M>, <&cru CPLL_125M>,
> -			<&cru CPLL_100M>, <&cru CPLL_62P5M>,
> -			<&cru CPLL_50M>, <&cru CPLL_25M>;
> -		assigned-clock-rates =
> -			<32768>,
> -			<200000000>,
> -			<100000000>, <1000000000>,
> -			<1188000000>,
> -			<150000000>, <100000000>,
> -			<500000000>, <400000000>,
> -			<150000000>, <100000000>,
> -			<300000000>, <150000000>,
> -			<500000000>, <333333333>,
> -			<250000000>, <125000000>,
> -			<100000000>, <62500000>,
> -			<50000000>, <25000000>;
> -		assigned-clock-parents =
> -			<&pmucru CLK_RTC32K_FRAC>;
> -};
> -
>   &dsi_dphy0 {
>   	status = "okay";
>   };
> diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> index 404dddfafb..9e0aa9e63b 100644
> --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> @@ -16,3 +16,10 @@
>   		     "anbernic,rg353v", "anbernic,rg353vs",
>   		     "anbernic,rg503", "rockchip,rk3566";
>   };
> +
> +&cru {
> +	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
> +			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
> +	assigned-clock-rates = <32768>, <1200000000>,
> +			       <200000000>, <241500000>;
> +};

Re: [PATCH 2/4] board: rockchip: Add support for Powkiddy RGB10MAX3

[Kever Yang]

On 2024/2/6 02:58, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add support to the RGxx3 device for the Powkiddy RGB10MAX3. This device
> is extremely similar to all the other devices and can use the same
> bootloader with the same detection logic.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/dts/rk3566-anbernic-rgxx3.dts     | 9 ++++++---
>   board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 8 ++++++++
>   doc/board/anbernic/rgxx3.rst               | 1 +
>   3 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> index 9e0aa9e63b..c393c8d07a 100644
> --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> @@ -12,9 +12,12 @@
>    * set the correct dtb name for loading mainline Linux automatically.
>    */
>   	model = "RGXX3";
> -	compatible = "anbernic,rg353m", "anbernic,rg353p",
> -		     "anbernic,rg353v", "anbernic,rg353vs",
> -		     "anbernic,rg503", "rockchip,rk3566";
> +	compatible = "anbernic,rg-arc-d", "anbernic,rg-arc-s",
> +		     "anbernic,rg353m", "anbernic,rg353p",
> +		     "anbernic,rg353ps", "anbernic,rg353v",
> +		     "anbernic,rg353vs", "anbernic,rg503",
> +		     "powkiddy,rgb10max3", "powkiddy,rgb30",
> +		     "powkiddy,rk2023", "rockchip,rk3566";
>   };
>   
>   &cru {
> diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> index d05502f67a..5c57b902d1 100644
> --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> @@ -50,6 +50,7 @@ enum rgxx3_device_id {
>   	RGB30,
>   	RK2023,
>   	RGARCD,
> +	RGB10MAX3,
>   	/* Devices with duplicate ADC value */
>   	RG353PS,
>   	RG353VS,
> @@ -107,6 +108,13 @@ static const struct rg3xx_model rg3xx_model_details[] = {
>   		.fdtfile = DTB_DIR "rk3566-anbernic-rg-arc-d.dtb",
>   		.detect_panel = 0,
>   	},
> +	[RGB10MAX3] = {
> +		.adc_value = 765, /* Observed average from device */
> +		.board = "rk3566-powkiddy-rgb10max3",
> +		.board_name = "Powkiddy RGB10MAX3",
> +		.fdtfile = DTB_DIR "rk3566-powkiddy-rgb10max3.dtb",
> +		.detect_panel = 0,
> +	},
>   	/* Devices with duplicate ADC value */
>   	[RG353PS] = {
>   		.adc_value = 860, /* Observed average from device */
> diff --git a/doc/board/anbernic/rgxx3.rst b/doc/board/anbernic/rgxx3.rst
> index d159ed2f76..1e63e6951e 100644
> --- a/doc/board/anbernic/rgxx3.rst
> +++ b/doc/board/anbernic/rgxx3.rst
> @@ -17,6 +17,7 @@ This allows U-Boot to boot the following Anbernic devices:
>   Additionally, the following very similar non-Anbernic devices are also
>   supported:
>   
> + - Powkiddy RGB10MAX3
>    - Powkiddy RGB30
>    - Powkiddy RK2023
>   

Re: [PATCH 3/4] configs: Remove unnecessary options from RGxx3 config

[Kever Yang]

On 2024/2/6 02:58, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Based on feedback from the mailing list while adding support for a new
> device (the Powkiddy X55), correct the config options for the RGxx3
> as well to remove unnecessary drivers and increase the SPL stack size.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   configs/anbernic-rgxx3-rk3566_defconfig | 15 +++++++++++----
>   1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
> index ed6643d9d4..d52a0d48f2 100644
> --- a/configs/anbernic-rgxx3-rk3566_defconfig
> +++ b/configs/anbernic-rgxx3-rk3566_defconfig
> @@ -3,6 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
>   CONFIG_COUNTER_FREQUENCY=24000000
>   CONFIG_ARCH_ROCKCHIP=y
>   CONFIG_TEXT_BASE=0x00a00000
> +CONFIG_SPL_GPIO=y
>   CONFIG_SPL_LIBCOMMON_SUPPORT=y
>   CONFIG_SPL_LIBGENERIC_SUPPORT=y
>   CONFIG_NR_DRAM_BANKS=2
> @@ -24,7 +25,9 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
>   CONFIG_DEBUG_UART=y
>   CONFIG_FIT=y
>   CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_FIT_SIGNATURE=y
>   CONFIG_SPL_LOAD_FIT=y
> +CONFIG_LEGACY_IMAGE_FORMAT=y
>   CONFIG_OF_BOARD_SETUP=y
>   CONFIG_OF_STDOUT_VIA_ALIAS=y
>   CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
> @@ -32,7 +35,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
>   # CONFIG_DISPLAY_CPUINFO is not set
>   CONFIG_DISPLAY_BOARDINFO_LATE=y
>   CONFIG_BOARD_RNG_SEED=y
> -CONFIG_SPL_MAX_SIZE=0x20000
> +CONFIG_SPL_MAX_SIZE=0x40000
>   CONFIG_SPL_PAD_TO=0x7f8000
>   CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>   CONFIG_SPL_BSS_START_ADDR=0x4000000
> @@ -41,6 +44,7 @@ CONFIG_SPL_BOARD_INIT=y
>   # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>   # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>   CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_POWER=y
>   CONFIG_SPL_ATF=y
>   CONFIG_CMD_PWM=y
>   CONFIG_CMD_GPT=y
> @@ -50,8 +54,10 @@ CONFIG_CMD_MMC=y
>   # CONFIG_SPL_DOS_PARTITION is not set
>   CONFIG_SPL_OF_CONTROL=y
>   CONFIG_OF_LIVE=y
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
>   CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
>   # CONFIG_NET is not set
> +CONFIG_SPL_DM_SEQ_ALIAS=y
>   CONFIG_SPL_REGMAP=y
>   CONFIG_SPL_SYSCON=y
>   CONFIG_SPL_CLK=y
> @@ -67,13 +73,13 @@ CONFIG_MMC_SDHCI=y
>   CONFIG_MMC_SDHCI_SDMA=y
>   CONFIG_MMC_SDHCI_ROCKCHIP=y
>   CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
> +CONFIG_SPL_PINCTRL=y
>   CONFIG_DM_PMIC=y
>   CONFIG_DM_PMIC_FAN53555=y
>   CONFIG_PMIC_RK8XX=y
> -CONFIG_REGULATOR_PWM=y
> -CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_SPL_DM_REGULATOR=y
> +CONFIG_SPL_DM_REGULATOR_FIXED=y
>   CONFIG_REGULATOR_RK8XX=y
> -CONFIG_DM_REGULATOR_SCMI=y
>   CONFIG_PWM_ROCKCHIP=y
>   CONFIG_SPL_RAM=y
>   # CONFIG_RAM_ROCKCHIP_DEBUG is not set
> @@ -89,5 +95,6 @@ CONFIG_VIDEO_ROCKCHIP=y
>   CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y
>   CONFIG_VIDEO_BRIDGE=y
>   CONFIG_REGEX=y
> +# CONFIG_RSA is not set
>   CONFIG_ERRNO_STR=y
>   # CONFIG_EFI_LOADER is not set

Re: [PATCH 4/4] board: rockchip: Add early ADC button detect for RGxx3

[Kever Yang]

On 2024/2/6 02:58, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add ADC button detect for early SPL stage for RGxx3 device. This is
> important because on at least the RG353P and RG353V a clk pin is not
> exposed that would allow us to take the eMMC out of the boot path.

This is another version of below patch, right?

https://patchwork.ozlabs.org/project/uboot/patch/20240102154654.191055-5-macroalpha82@gmail.com/


Compare to this one, I would prefer previous version :(


Thanks,

- Kever

>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
>   board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 64 ++++++++++++++++++++++
>   1 file changed, 64 insertions(+)
>
> diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> index 5c57b902d1..099eea60c3 100644
> --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> @@ -6,12 +6,14 @@
>   #include <abuf.h>
>   #include <adc.h>
>   #include <asm/io.h>
> +#include <command.h>
>   #include <display.h>
>   #include <dm.h>
>   #include <dm/lists.h>
>   #include <env.h>
>   #include <fdt_support.h>
>   #include <linux/delay.h>
> +#include <linux/iopoll.h>
>   #include <mipi_dsi.h>
>   #include <mmc.h>
>   #include <panel.h>
> @@ -19,6 +21,8 @@
>   #include <stdlib.h>
>   #include <video_bridge.h>
>   
> +#define BOOT_BROM_DOWNLOAD	0xef08a53c
> +
>   #define GPIO0_BASE		0xfdd60000
>   #define GPIO4_BASE		0xfe770000
>   #define GPIO_SWPORT_DR_L	0x0000
> @@ -32,6 +36,14 @@
>   
>   #define GPIO_WRITEMASK(bits)	((bits) << 16)
>   
> +#define SARADC_BASE		0xfe720000
> +#define SARADC_DATA		0x0000
> +#define SARADC_STAS		0x0004
> +#define SARADC_ADC_STATUS	BIT(0)
> +#define SARADC_CTRL		0x0008
> +#define SARADC_INPUT_SRC_MSK	0x7
> +#define SARADC_POWER_CTRL	BIT(3)
> +
>   #define DTB_DIR			"rockchip/"
>   
>   struct rg3xx_model {
> @@ -157,12 +169,64 @@ static const struct rg353_panel rg353_panel_details[] = {
>   	},
>   };
>   
> +/*
> + * The device has internal eMMC, and while some devices have an exposed
> + * clk pin you can ground to force a bypass not all devices do. As a
> + * result it may be possible for some devices to become a perma-brick
> + * if a corrupted TPL or SPL stage with a valid header is flashed to
> + * the internal eMMC. Add functionality to read ADC channel 0 (the func
> + * button) as early as possible in the boot process to provide some
> + * protection against this. If we ever get an open TPL stage, we should
> + * consider moving this function there.
> + */
> +void read_func_button(void)
> +{
> +	int ret;
> +	u32 reg;
> +
> +	/* Turn off SARADC to reset it. */
> +	writel(0, (SARADC_BASE + SARADC_CTRL));
> +
> +	/* Enable channel 0 and power on SARADC. */
> +	writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL),
> +	       (SARADC_BASE + SARADC_CTRL));
> +
> +	/*
> +	 * Wait for data to be ready. Use timeout of 20000us from
> +	 * rockchip_saradc driver.
> +	 */
> +	ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg,
> +				 !(reg & SARADC_ADC_STATUS), 20000);
> +	if (ret) {
> +		printf("ADC Timeout");
> +		return;
> +	}
> +
> +	/* Read the data from the SARADC. */
> +	reg = readl((SARADC_BASE + SARADC_DATA));
> +
> +	/* Turn the SARADC back off so it's ready to be used again. */
> +	writel(0, (SARADC_BASE + SARADC_CTRL));
> +
> +	/*
> +	 * If the value is less than 30 the button is being pressed.
> +	 * Reset the device back into Rockchip download mode.
> +	 */
> +	if (reg <= 30) {
> +		printf("download key pressed, entering download mode...");
> +		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
> +		do_reset(NULL, 0, 0, NULL);
> +	}
> +};
> +
>   /*
>    * Start LED very early so user knows device is on. Set color
>    * to red.
>    */
>   void spl_board_init(void)
>   {
> +	read_func_button();
> +
>   	/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
>   	writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
>   	       (GPIO_C7 | GPIO_C6 | GPIO_C5),

Re: [PATCH 1/4] arm: dts: rockchip: rk3566: Remove unnecessary clks from rgxx3

[Chris Morgan]

On Tue, Feb 06, 2024 at 10:38:40AM +0800, Kever Yang wrote:
> Hi Chris,
> 
> On 2024/2/6 02:58, Chris Morgan wrote:
> > From: Chris Morgan <macromorgan@hotmail.com>
> > 
> > Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
> > Move the necessary defines to the RGxx3 main dts file.
> > 
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> 
> First of all, the dts should follow the one in mainline kernel;
> 
> and why you need to over write the cru in U-Boot for this board, I didn't
> see this change
> 
> in other boards.

This is kind of a special case, because these devices are so similar
they can all use the same bootloader. So as a result I have all 11
of them (and counting) pretending to be a "pseudo" device in U-Boot
called the RGxx3. The only reason I'm setting the clock here is to
set the PLL_VPLL value to something so I can start addressing the
DSI panel. This way, I'm able to probe it and send a panel ID request.
The problem is the manufacturer (Anbernic) has 2 versions of devices
with no distinguishing characteristics.

The specific ask here though is to simplify the clock definition. When
mainlining a different device (the Powkiddy X55) I was asked to not
define so many clocks, especially if they weren't like that in
mainline. It turns out this device also does not need so many
definitions, so this specific patch is to undo them and make it more
simple.

Let me know if you have any other questions. Thank you.
Chris

> 
> 
> Thanks,
> 
> - Kever
> 
> > ---
> >   .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 -------------------
> >   arch/arm/dts/rk3566-anbernic-rgxx3.dts        |  7 +++++
> >   2 files changed, 7 insertions(+), 31 deletions(-)
> > 
> > diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> > index f986e1941e..ef4f81500b 100644
> > --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> > +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> > @@ -15,37 +15,6 @@
> >   	};
> >   };
> > -&cru {
> > -	assigned-clocks =
> > -			<&pmucru CLK_RTC_32K>,
> > -			<&pmucru PLL_PPLL>,
> > -			<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
> > -			<&cru PLL_GPLL>,
> > -			<&cru ACLK_BUS>, <&cru PCLK_BUS>,
> > -			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
> > -			<&cru HCLK_TOP>, <&cru PCLK_TOP>,
> > -			<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
> > -			<&cru CPLL_500M>, <&cru CPLL_333M>,
> > -			<&cru CPLL_250M>, <&cru CPLL_125M>,
> > -			<&cru CPLL_100M>, <&cru CPLL_62P5M>,
> > -			<&cru CPLL_50M>, <&cru CPLL_25M>;
> > -		assigned-clock-rates =
> > -			<32768>,
> > -			<200000000>,
> > -			<100000000>, <1000000000>,
> > -			<1188000000>,
> > -			<150000000>, <100000000>,
> > -			<500000000>, <400000000>,
> > -			<150000000>, <100000000>,
> > -			<300000000>, <150000000>,
> > -			<500000000>, <333333333>,
> > -			<250000000>, <125000000>,
> > -			<100000000>, <62500000>,
> > -			<50000000>, <25000000>;
> > -		assigned-clock-parents =
> > -			<&pmucru CLK_RTC32K_FRAC>;
> > -};
> > -
> >   &dsi_dphy0 {
> >   	status = "okay";
> >   };
> > diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> > index 404dddfafb..9e0aa9e63b 100644
> > --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> > +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> > @@ -16,3 +16,10 @@
> >   		     "anbernic,rg353v", "anbernic,rg353vs",
> >   		     "anbernic,rg503", "rockchip,rk3566";
> >   };
> > +
> > +&cru {
> > +	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
> > +			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
> > +	assigned-clock-rates = <32768>, <1200000000>,
> > +			       <200000000>, <241500000>;
> > +};

Re: [PATCH 4/4] board: rockchip: Add early ADC button detect for RGxx3

[Chris Morgan]

On Tue, Feb 06, 2024 at 10:53:13AM +0800, Kever Yang wrote:
> 
> On 2024/2/6 02:58, Chris Morgan wrote:
> > From: Chris Morgan <macromorgan@hotmail.com>
> > 
> > Add ADC button detect for early SPL stage for RGxx3 device. This is
> > important because on at least the RG353P and RG353V a clk pin is not
> > exposed that would allow us to take the eMMC out of the boot path.
> 
> This is another version of below patch, right?
> 
> https://patchwork.ozlabs.org/project/uboot/patch/20240102154654.191055-5-macroalpha82@gmail.com/
> 
> 
> Compare to this one, I would prefer previous version :(

It is another version of the patch. I did (redid) this in response to
comments on that patch series.

I basically face a unique set of constraints, and am trying to solve
for it. Those constraints are 1) I have a few boards, namely the
Anbernic RG353P and RG353V that do not have exposed pads that would
allow me to remove the eMMC from the boot path, 2) The SDMMC slot
present is after the eMMC in the boot path, and 3) after the binary
A-TF loads the reset to usb loader fails to work properly and simply
resets the board (but not to maskrom as needed/requested).

Your past comments suggested it would not be needed/useful to have this
done in a board generic way, which I understand; so I'm simply doing
it again in a board specific way. Note that I will shortly be
resubmitting another U-Boot request for the Powkiddy X55 which also
needs this; I'm not aware of any other boards currently that will
though.

So I guess my questions that would answer the path forward are
1) should this be done in a board specific way (like so) or should I
go back to the board generic method. 2) Will the binary A-TF be fixed
to allow me to reboot to maskrom mode or is that by design?

Note I've tested this also with the pending A-TF source at
trustedfirmware.org. Sadly I need SCMI clk support before I can replace
the binary A-TF with the open source one.

Thank you,
Chris

> 
> 
> Thanks,
> 
> - Kever
> 
> > 
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > ---
> >   board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 64 ++++++++++++++++++++++
> >   1 file changed, 64 insertions(+)
> > 
> > diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> > index 5c57b902d1..099eea60c3 100644
> > --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> > +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> > @@ -6,12 +6,14 @@
> >   #include <abuf.h>
> >   #include <adc.h>
> >   #include <asm/io.h>
> > +#include <command.h>
> >   #include <display.h>
> >   #include <dm.h>
> >   #include <dm/lists.h>
> >   #include <env.h>
> >   #include <fdt_support.h>
> >   #include <linux/delay.h>
> > +#include <linux/iopoll.h>
> >   #include <mipi_dsi.h>
> >   #include <mmc.h>
> >   #include <panel.h>
> > @@ -19,6 +21,8 @@
> >   #include <stdlib.h>
> >   #include <video_bridge.h>
> > +#define BOOT_BROM_DOWNLOAD	0xef08a53c
> > +
> >   #define GPIO0_BASE		0xfdd60000
> >   #define GPIO4_BASE		0xfe770000
> >   #define GPIO_SWPORT_DR_L	0x0000
> > @@ -32,6 +36,14 @@
> >   #define GPIO_WRITEMASK(bits)	((bits) << 16)
> > +#define SARADC_BASE		0xfe720000
> > +#define SARADC_DATA		0x0000
> > +#define SARADC_STAS		0x0004
> > +#define SARADC_ADC_STATUS	BIT(0)
> > +#define SARADC_CTRL		0x0008
> > +#define SARADC_INPUT_SRC_MSK	0x7
> > +#define SARADC_POWER_CTRL	BIT(3)
> > +
> >   #define DTB_DIR			"rockchip/"
> >   struct rg3xx_model {
> > @@ -157,12 +169,64 @@ static const struct rg353_panel rg353_panel_details[] = {
> >   	},
> >   };
> > +/*
> > + * The device has internal eMMC, and while some devices have an exposed
> > + * clk pin you can ground to force a bypass not all devices do. As a
> > + * result it may be possible for some devices to become a perma-brick
> > + * if a corrupted TPL or SPL stage with a valid header is flashed to
> > + * the internal eMMC. Add functionality to read ADC channel 0 (the func
> > + * button) as early as possible in the boot process to provide some
> > + * protection against this. If we ever get an open TPL stage, we should
> > + * consider moving this function there.
> > + */
> > +void read_func_button(void)
> > +{
> > +	int ret;
> > +	u32 reg;
> > +
> > +	/* Turn off SARADC to reset it. */
> > +	writel(0, (SARADC_BASE + SARADC_CTRL));
> > +
> > +	/* Enable channel 0 and power on SARADC. */
> > +	writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL),
> > +	       (SARADC_BASE + SARADC_CTRL));
> > +
> > +	/*
> > +	 * Wait for data to be ready. Use timeout of 20000us from
> > +	 * rockchip_saradc driver.
> > +	 */
> > +	ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg,
> > +				 !(reg & SARADC_ADC_STATUS), 20000);
> > +	if (ret) {
> > +		printf("ADC Timeout");
> > +		return;
> > +	}
> > +
> > +	/* Read the data from the SARADC. */
> > +	reg = readl((SARADC_BASE + SARADC_DATA));
> > +
> > +	/* Turn the SARADC back off so it's ready to be used again. */
> > +	writel(0, (SARADC_BASE + SARADC_CTRL));
> > +
> > +	/*
> > +	 * If the value is less than 30 the button is being pressed.
> > +	 * Reset the device back into Rockchip download mode.
> > +	 */
> > +	if (reg <= 30) {
> > +		printf("download key pressed, entering download mode...");
> > +		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
> > +		do_reset(NULL, 0, 0, NULL);
> > +	}
> > +};
> > +
> >   /*
> >    * Start LED very early so user knows device is on. Set color
> >    * to red.
> >    */
> >   void spl_board_init(void)
> >   {
> > +	read_func_button();
> > +
> >   	/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
> >   	writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
> >   	       (GPIO_C7 | GPIO_C6 | GPIO_C5),

Re: [PATCH 1/4] arm: dts: rockchip: rk3566: Remove unnecessary clks from rgxx3

[Kever Yang]

On 2024/2/6 02:58, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
> Move the necessary defines to the RGxx3 main dts file.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 -------------------
>   arch/arm/dts/rk3566-anbernic-rgxx3.dts        |  7 +++++
>   2 files changed, 7 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> index f986e1941e..ef4f81500b 100644
> --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> @@ -15,37 +15,6 @@
>   	};
>   };
>   
> -&cru {
> -	assigned-clocks =
> -			<&pmucru CLK_RTC_32K>,
> -			<&pmucru PLL_PPLL>,
> -			<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
> -			<&cru PLL_GPLL>,
> -			<&cru ACLK_BUS>, <&cru PCLK_BUS>,
> -			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
> -			<&cru HCLK_TOP>, <&cru PCLK_TOP>,
> -			<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
> -			<&cru CPLL_500M>, <&cru CPLL_333M>,
> -			<&cru CPLL_250M>, <&cru CPLL_125M>,
> -			<&cru CPLL_100M>, <&cru CPLL_62P5M>,
> -			<&cru CPLL_50M>, <&cru CPLL_25M>;
> -		assigned-clock-rates =
> -			<32768>,
> -			<200000000>,
> -			<100000000>, <1000000000>,
> -			<1188000000>,
> -			<150000000>, <100000000>,
> -			<500000000>, <400000000>,
> -			<150000000>, <100000000>,
> -			<300000000>, <150000000>,
> -			<500000000>, <333333333>,
> -			<250000000>, <125000000>,
> -			<100000000>, <62500000>,
> -			<50000000>, <25000000>;
> -		assigned-clock-parents =
> -			<&pmucru CLK_RTC32K_FRAC>;
> -};
> -
>   &dsi_dphy0 {
>   	status = "okay";
>   };
> diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> index 404dddfafb..9e0aa9e63b 100644
> --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> @@ -16,3 +16,10 @@
>   		     "anbernic,rg353v", "anbernic,rg353vs",
>   		     "anbernic,rg503", "rockchip,rk3566";
>   };
> +
> +&cru {
> +	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
> +			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
> +	assigned-clock-rates = <32768>, <1200000000>,
> +			       <200000000>, <241500000>;
> +};

Re: [PATCH 4/4] board: rockchip: Add early ADC button detect for RGxx3

[Kever Yang]

On 2024/2/6 02:58, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add ADC button detect for early SPL stage for RGxx3 device. This is
> important because on at least the RG353P and RG353V a clk pin is not
> exposed that would allow us to take the eMMC out of the boot path.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 64 ++++++++++++++++++++++
>   1 file changed, 64 insertions(+)
>
> diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> index 5c57b902d1..099eea60c3 100644
> --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> @@ -6,12 +6,14 @@
>   #include <abuf.h>
>   #include <adc.h>
>   #include <asm/io.h>
> +#include <command.h>
>   #include <display.h>
>   #include <dm.h>
>   #include <dm/lists.h>
>   #include <env.h>
>   #include <fdt_support.h>
>   #include <linux/delay.h>
> +#include <linux/iopoll.h>
>   #include <mipi_dsi.h>
>   #include <mmc.h>
>   #include <panel.h>
> @@ -19,6 +21,8 @@
>   #include <stdlib.h>
>   #include <video_bridge.h>
>   
> +#define BOOT_BROM_DOWNLOAD	0xef08a53c
> +
>   #define GPIO0_BASE		0xfdd60000
>   #define GPIO4_BASE		0xfe770000
>   #define GPIO_SWPORT_DR_L	0x0000
> @@ -32,6 +36,14 @@
>   
>   #define GPIO_WRITEMASK(bits)	((bits) << 16)
>   
> +#define SARADC_BASE		0xfe720000
> +#define SARADC_DATA		0x0000
> +#define SARADC_STAS		0x0004
> +#define SARADC_ADC_STATUS	BIT(0)
> +#define SARADC_CTRL		0x0008
> +#define SARADC_INPUT_SRC_MSK	0x7
> +#define SARADC_POWER_CTRL	BIT(3)
> +
>   #define DTB_DIR			"rockchip/"
>   
>   struct rg3xx_model {
> @@ -157,12 +169,64 @@ static const struct rg353_panel rg353_panel_details[] = {
>   	},
>   };
>   
> +/*
> + * The device has internal eMMC, and while some devices have an exposed
> + * clk pin you can ground to force a bypass not all devices do. As a
> + * result it may be possible for some devices to become a perma-brick
> + * if a corrupted TPL or SPL stage with a valid header is flashed to
> + * the internal eMMC. Add functionality to read ADC channel 0 (the func
> + * button) as early as possible in the boot process to provide some
> + * protection against this. If we ever get an open TPL stage, we should
> + * consider moving this function there.
> + */
> +void read_func_button(void)
> +{
> +	int ret;
> +	u32 reg;
> +
> +	/* Turn off SARADC to reset it. */
> +	writel(0, (SARADC_BASE + SARADC_CTRL));
> +
> +	/* Enable channel 0 and power on SARADC. */
> +	writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL),
> +	       (SARADC_BASE + SARADC_CTRL));
> +
> +	/*
> +	 * Wait for data to be ready. Use timeout of 20000us from
> +	 * rockchip_saradc driver.
> +	 */
> +	ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg,
> +				 !(reg & SARADC_ADC_STATUS), 20000);
> +	if (ret) {
> +		printf("ADC Timeout");
> +		return;
> +	}
> +
> +	/* Read the data from the SARADC. */
> +	reg = readl((SARADC_BASE + SARADC_DATA));
> +
> +	/* Turn the SARADC back off so it's ready to be used again. */
> +	writel(0, (SARADC_BASE + SARADC_CTRL));
> +
> +	/*
> +	 * If the value is less than 30 the button is being pressed.
> +	 * Reset the device back into Rockchip download mode.
> +	 */
> +	if (reg <= 30) {
> +		printf("download key pressed, entering download mode...");
> +		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
> +		do_reset(NULL, 0, 0, NULL);
> +	}
> +};
> +
>   /*
>    * Start LED very early so user knows device is on. Set color
>    * to red.
>    */
>   void spl_board_init(void)
>   {
> +	read_func_button();
> +
>   	/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
>   	writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
>   	       (GPIO_C7 | GPIO_C6 | GPIO_C5),