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[31.10.206.125]) by smtp.gmail.com with ESMTPSA id m23-20020a1709062ad700b00a3de8866819sm2909435eje.76.2024.02.19.04.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 04:34:10 -0800 (PST) From: Vitor Soares To: marcel.ziswiler@toradex.com, trini@konsulko.com Cc: u-boot@lists.denx.de, Vitor Soares Subject: [PATCH] arm: dts: k3-am625-verdin-r5: Change CPU frequency to 1000MHz Date: Mon, 19 Feb 2024 12:34:08 +0000 Message-Id: <20240219123408.22054-1-ivitro@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Mon, 19 Feb 2024 14:53:09 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Vitor Soares The same U-Boot binary is compatible with multiple Verdin AM62 board variants. However, some of the SoC models can only operate at a maximum speed of 1 GHz. Previously, the boards with lower-speed grades were running at overclocked speeds, leading to kernel complaints about unsupported configurations. To resolve this issue, the operating speed has been decreased to the maximum allowable value across all Verdin AM62 board variants. As a result, there is a regression in overall boot time, increasing by around 200 milliseconds for the faster SoC variant. Signed-off-by: Vitor Soares --- arch/arm/dts/k3-am625-verdin-r5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index 305d199678..6b03e7405a 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -23,7 +23,7 @@ */ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>; assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>; - assigned-clock-rates = <200000000>, <1200000000>, <25000000>; + assigned-clock-rates = <200000000>, <1000000000>, <25000000>; clocks = <&k3_clks 61 0>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, -- 2.34.1