From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35D2FC54764 for ; Tue, 20 Feb 2024 18:41:18 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 92C4F8802F; Tue, 20 Feb 2024 19:40:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="vYO9UFyy"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4BC5F87FEE; Tue, 20 Feb 2024 19:40:14 +0100 (CET) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 142B688010 for ; Tue, 20 Feb 2024 19:40:00 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=nm@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41KIdrrK084043; Tue, 20 Feb 2024 12:39:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1708454393; bh=zKoIExRVBuhQvnZgHBxg9jxPYNMEOuYGBuZJ5jM/S8M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vYO9UFyyc3npN4VTPM3sHpVSL8Pjzq24iq0HnZtX6Q/n2k53ApazFFgXhQt4BBS5C bboaEL10aXnceqmSYn13QlZtyAcg1hA1U+ZA49uM2H4oU1wddxJoLQp9tZnExRZfUw +oVGTY2IHN+f8Zqgb7B7pPpdefdcYPHvM2Kjux2s= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41KIdrMU059777 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Feb 2024 12:39:53 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 20 Feb 2024 12:39:53 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 20 Feb 2024 12:39:53 -0600 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41KIdrdw128004; Tue, 20 Feb 2024 12:39:53 -0600 From: Nishanth Menon To: Robert Nelson , Tom Rini CC: , Nishanth Menon Subject: [PATCH V2 3/5] arm: mach-k3: am62: Add Debounce configuration register definitions Date: Tue, 20 Feb 2024 12:39:50 -0600 Message-ID: <20240220183952.3614252-4-nm@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240220183952.3614252-1-nm@ti.com> References: <20240220183952.3614252-1-nm@ti.com> MIME-Version: 1.0 Organization: Texas Instruments, Inc. Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add the Debounce configuration registers that need to be configured one time for the platform for the entire SoC. Signed-off-by: Nishanth Menon --- Changes since V1: * Fix 4080 to 0x4080 V1: https://lore.kernel.org/r/20240212155332.541949-4-nm@ti.com arch/arm/mach-k3/include/mach/am62_hardware.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 54380f36e161..4cf7778a89ee 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -75,6 +75,9 @@ #define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170) +/* Debounce register configuration */ +#define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4)) + #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 -- 2.43.0