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From: Sumit Garg <sumit.garg@linaro.org>
To: u-boot@lists.denx.de
Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org,
	trini@konsulko.com, lukma@denx.de, seanga2@gmail.com,
	sjg@chromium.org, laetitia.mariottini@se.com,
	pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com,
	benjamin.missey@non.se.com, daniel.thompson@linaro.org,
	stephan@gerhold.net, Sumit Garg <sumit.garg@linaro.org>
Subject: [PATCH v2 3/5] serial_msm: Enable RS232 flow control
Date: Mon, 11 Mar 2024 16:40:24 +0530	[thread overview]
Message-ID: <20240311111027.44577-4-sumit.garg@linaro.org> (raw)
In-Reply-To: <20240311111027.44577-1-sumit.garg@linaro.org>

SE HMIBSC board debug console requires RS232 flow control, so enable
corresponding support if RS232 gpios are present.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
 drivers/serial/serial_msm.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index eaf024a55b0..7b2a3fdb2c1 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -53,10 +53,11 @@
 #define UARTDM_TF               0x100 /* UART Transmit FIFO register */
 #define UARTDM_RF               0x140 /* UART Receive FIFO register */
 
-#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
-#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
-#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
-#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
+#define UART_DM_CLK_RX_TX_BIT_RATE	0xCC
+#define MSM_BOOT_UART_DM_8_N_1_MODE	0x34
+#define MSM_BOOT_UART_DM_CMD_RESET_RX	0x10
+#define MSM_BOOT_UART_DM_CMD_RESET_TX	0x20
+#define MSM_UART_MR1_RX_RDY_CTL		BIT(7)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -182,7 +183,9 @@ static void uart_dm_init(struct msm_serial_data *priv)
 	mdelay(5);
 
 	writel(priv->clk_bit_rate, priv->base + UARTDM_CSR);
-	writel(0x0, priv->base + UARTDM_MR1);
+
+	/* Enable RS232 flow control to support RS232 db9 connector */
+	writel(MSM_UART_MR1_RX_RDY_CTL, priv->base + UARTDM_MR1);
 	writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
 	writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
 	writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
-- 
2.34.1


  parent reply	other threads:[~2024-03-11 11:11 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-11 11:10 [PATCH v2 0/5] Add SE HMBSC board support Sumit Garg
2024-03-11 11:10 ` [PATCH v2 1/5] qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default Sumit Garg
2024-03-11 12:29   ` Caleb Connolly
2024-03-11 11:10 ` [PATCH v2 2/5] apq8016: Add support for UART1 clocks and pinmux Sumit Garg
2024-03-11 12:27   ` Caleb Connolly
2024-03-11 13:32     ` Stephan Gerhold
2024-03-11 14:50       ` Caleb Connolly
2024-03-12  8:15         ` Sumit Garg
2024-03-12  8:20     ` Sumit Garg
2024-03-11 11:10 ` Sumit Garg [this message]
2024-03-11 12:30   ` [PATCH v2 3/5] serial_msm: Enable RS232 flow control Caleb Connolly
2024-03-11 11:10 ` [PATCH v2 4/5] pinctrl: qcom: Add support for driving GPIO pins output Sumit Garg
2024-03-11 12:37   ` Caleb Connolly
2024-03-12  8:12     ` Sumit Garg
2024-03-11 11:10 ` [PATCH v2 5/5] board: add support for Schneider HMIBSC board Sumit Garg
2024-03-11 14:37   ` Stephan Gerhold
2024-03-13  6:38     ` Sumit Garg
2024-03-13 11:28       ` Stephan Gerhold
2024-03-13 11:39         ` Sumit Garg

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