[PATCH v2 0/6] mtd: nand: raw: Collected improvements

[PATCH v2 0/6] mtd: nand: raw: Collected improvements

[Alexander Dahl]

Hello everyone,

while working on NAND flash support for a custom board based on the at91
SAM9X60 SoC I stumbled over some issues in the raw nand subsystem.

Four of six patches are minor fixes.

Patch 4 introduces a new subcommand for the new atmel nand controller
driver.  Patch 6 introduces a new subcommand for the nand command to
override ONFI timing mode.  Both are are for debugging purposes only and
thus optional, and need to be enabled through menu.  Both helped me a
lot when investigating issues.

Series is based on upstream next branch, but should also apply to master
cleanly.

Greets
Alex

v1:

Link: https://lore.kernel.org/u-boot/20240307091014.39796-1-ada@thorsis.com/T/#t

v2:

- rebased on recent next
- collected tags
- improved patch 4 after feedback from Mihai
- added new patch 5 with another help text fix
- added new patch 6 with a new debug command
- reworded cover letter

See per patch changes in patches for more detailed changes.

Alexander Dahl (6):
  mtd: nand: raw: Use macro nand_to_mtd() where appropriate
  mtd: nand: raw: Port another option flag from Linux
  mtd: nand: raw: Fix (most) Kconfig indentation
  mtd: nand: raw: atmel: Introduce optional debug commands
  mtd: nand: raw: atmel: Fix comment in timings preparation
  cmd: nand: Add new optional sub-command 'onfi'

 cmd/Kconfig                                  |  10 +
 cmd/nand.c                                   |  61 ++++
 drivers/mtd/nand/raw/Kconfig                 | 115 +++----
 drivers/mtd/nand/raw/atmel/nand-controller.c | 299 ++++++++++++++++++-
 drivers/mtd/nand/raw/nand_base.c             |   8 +-
 include/linux/mtd/rawnand.h                  |   8 +
 6 files changed, 441 insertions(+), 60 deletions(-)


base-commit: f048104999db28d49362201eaebfc91adb14f47c
-- 
2.39.2

[PATCH v2 1/6] mtd: nand: raw: Use macro nand_to_mtd() where appropriate

[Alexander Dahl]

In every other place in this file the macro is used, make it consistent.

Fixes: 9d1806fadc24 ("mtd: nand: Get rid of mtd variable in function calls")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
---

Notes:
    v1:
    - initial patch version
    
    v2:
    - collected tags

 drivers/mtd/nand/raw/nand_base.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index c40a0f23d7b..688d17ba3c2 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4118,7 +4118,7 @@ static int nand_get_bits_per_cell(u8 cellinfo)
  */
 void nand_decode_ext_id(struct nand_chip *chip)
 {
-	struct mtd_info *mtd = &chip->mtd;
+	struct mtd_info *mtd = nand_to_mtd(chip);
 	int extid;
 	/* The 3rd id byte holds MLC / multichip data */
 	chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
@@ -4185,7 +4185,7 @@ static int nand_manufacturer_init(struct nand_chip *chip)
  */
 static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
 {
-	struct mtd_info *mtd = &chip->mtd;
+	struct mtd_info *mtd = nand_to_mtd(chip);
 
 	mtd->erasesize = type->erasesize;
 	mtd->writesize = type->pagesize;
@@ -4265,7 +4265,7 @@ static const struct nand_manufacturer *nand_get_manufacturer_desc(u8 id)
 int nand_detect(struct nand_chip *chip, int *maf_id,
 		int *dev_id, struct nand_flash_dev *type)
 {
-	struct mtd_info *mtd = &chip->mtd;
+	struct mtd_info *mtd = nand_to_mtd(chip);
 	const struct nand_manufacturer *manufacturer_desc;
 	int busw, ret;
 	u8 *id_data = chip->id.data;
-- 
2.39.2

[PATCH v2 2/6] mtd: nand: raw: Port another option flag from Linux

[Alexander Dahl]

Introduced in upstream Linux with commit 7a08dbaedd365 for release v5.0.

When the new atmel nand driver was backported to U-Boot with commit
6a8dfd57220d ("nand: atmel: Add DM based NAND driver") that definition
was added to the driver instead of the header file.  Move it over to the
other definitions with the same help text it has in Linux.

Code actually using this has not been ported over to raw nand base yet.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
---

Notes:
    v1:
    - initial patch version
    
    v2:
    - collected tags

 drivers/mtd/nand/raw/atmel/nand-controller.c | 2 --
 include/linux/mtd/rawnand.h                  | 7 +++++++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index 0e0441472b8..e06523f3298 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -1429,8 +1429,6 @@ static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
 	return nc->caps->ops->setup_data_interface(nand, csline, conf);
 }
 
-#define NAND_KEEP_TIMINGS       0x00800000
-
 static void atmel_nand_init(struct atmel_nand_controller *nc,
 			    struct atmel_nand *nand)
 {
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index fb002ae6411..4abaf4734cf 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -249,6 +249,13 @@ enum nand_ecc_algo {
  */
 #define NAND_USE_BOUNCE_BUFFER	0x00100000
 
+/*
+ * Do not try to tweak the timings at runtime. This is needed when the
+ * controller initializes the timings on itself or when it relies on
+ * configuration done by the bootloader.
+ */
+#define NAND_KEEP_TIMINGS	0x00800000
+
 /* Options set by nand scan */
 /* bbt has already been read */
 #define NAND_BBT_SCANNED	0x40000000
-- 
2.39.2

[PATCH v2 3/6] mtd: nand: raw: Fix (most) Kconfig indentation

[Alexander Dahl]

One tab in general.  One tab plus two spaces for help text.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
---

Notes:
    v1:
    - initial patch version
    
    v2:
    - collected tags

 drivers/mtd/nand/raw/Kconfig | 106 +++++++++++++++++------------------
 1 file changed, 53 insertions(+), 53 deletions(-)

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index bb9994b8626..f6644899b0a 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -1,6 +1,6 @@
-
 menuconfig MTD_RAW_NAND
 	bool "Raw NAND Device Support"
+
 if MTD_RAW_NAND
 
 config SYS_NAND_SELF_INIT
@@ -49,12 +49,12 @@ config SYS_NAND_NO_SUBPAGE_WRITE
 	depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD
 
 config DM_NAND_ATMEL
-       bool "Support Atmel NAND controller with DM support"
-       select SYS_NAND_SELF_INIT
-       imply SYS_NAND_USE_FLASH_BBT
-       help
-         Enable this driver for NAND flash platforms using an Atmel NAND
-         controller.
+	bool "Support Atmel NAND controller with DM support"
+	select SYS_NAND_SELF_INIT
+	imply SYS_NAND_USE_FLASH_BBT
+	help
+	  Enable this driver for NAND flash platforms using an Atmel NAND
+	  controller.
 
 config NAND_ATMEL
 	bool "Support Atmel NAND controller"
@@ -133,35 +133,35 @@ config NAND_BRCMNAND_6753
 	  Enable support for broadcom nand driver on bcm6753.
 
 config NAND_BRCMNAND_68360
-       bool "Support Broadcom NAND controller on bcm68360"
-       depends on NAND_BRCMNAND && BCM6856
-       help
-         Enable support for broadcom nand driver on bcm68360.
+	bool "Support Broadcom NAND controller on bcm68360"
+	depends on NAND_BRCMNAND && BCM6856
+	help
+	  Enable support for broadcom nand driver on bcm68360.
 
 config NAND_BRCMNAND_6838
-       bool "Support Broadcom NAND controller on bcm6838"
-       depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
-       help
-         Enable support for broadcom nand driver on bcm6838.
+	bool "Support Broadcom NAND controller on bcm6838"
+	depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
+	help
+	  Enable support for broadcom nand driver on bcm6838.
 
 config NAND_BRCMNAND_6858
-       bool "Support Broadcom NAND controller on bcm6858"
-       depends on NAND_BRCMNAND && BCM6858
-       help
-         Enable support for broadcom nand driver on bcm6858.
+	bool "Support Broadcom NAND controller on bcm6858"
+	depends on NAND_BRCMNAND && BCM6858
+	help
+	  Enable support for broadcom nand driver on bcm6858.
 
 config NAND_BRCMNAND_63158
-       bool "Support Broadcom NAND controller on bcm63158"
-       depends on NAND_BRCMNAND && BCM63158
-       help
-         Enable support for broadcom nand driver on bcm63158.
+	bool "Support Broadcom NAND controller on bcm63158"
+	depends on NAND_BRCMNAND && BCM63158
+	help
+	  Enable support for broadcom nand driver on bcm63158.
 
 config NAND_BRCMNAND_IPROC
-       bool "Support Broadcom NAND controller on the iproc family"
-       depends on NAND_BRCMNAND
-       help
-         Enable support for broadcom nand driver on the Broadcom
-         iproc family such as Northstar (BCM5301x, BCM4708...)
+	bool "Support Broadcom NAND controller on the iproc family"
+	depends on NAND_BRCMNAND
+	help
+	  Enable support for broadcom nand driver on the Broadcom
+	  iproc family such as Northstar (BCM5301x, BCM4708...)
 
 config NAND_DAVINCI
 	bool "Support TI Davinci NAND controller"
@@ -413,10 +413,10 @@ config NAND_VF610_NFC
 if NAND_VF610_NFC
 
 config NAND_VF610_NFC_DT
-        bool "Support Vybrid's vf610 NAND controller as a DT device"
-        depends on OF_CONTROL && DM_MTD
-        help
-          Enable the driver for Vybrid's vf610 NAND flash on platforms
+	bool "Support Vybrid's vf610 NAND controller as a DT device"
+	depends on OF_CONTROL && DM_MTD
+	help
+	  Enable the driver for Vybrid's vf610 NAND flash on platforms
 	  using device tree.
 
 choice
@@ -472,11 +472,11 @@ config NAND_SUNXI
 	select SPL_NAND_SUPPORT
 	select SPL_SYS_NAND_SELF_INIT
 	imply CMD_NAND
-	---help---
-	Enable support for NAND. This option enables the standard and
-	SPL drivers.
-	The SPL driver only supports reading from the NAND using DMA
-	transfers.
+	help
+	  Enable support for NAND. This option enables the standard and
+	  SPL drivers.
+	  The SPL driver only supports reading from the NAND using DMA
+	  transfers.
 
 if NAND_SUNXI
 
@@ -577,16 +577,16 @@ config NAND_OCTEONTX
 	select SYS_NAND_SELF_INIT
 	imply CMD_NAND
 	help
-	 This enables Nand flash controller hardware found on the OcteonTX
-	 processors.
+	  This enables Nand flash controller hardware found on the OcteonTX
+	  processors.
 
 config NAND_OCTEONTX_HW_ECC
 	bool "Support Hardware ECC for OcteonTX NAND controller"
 	depends on NAND_OCTEONTX
 	default y
 	help
-	 This enables Hardware BCH engine found on the OcteonTX processors to
-	 support ECC for NAND flash controller.
+	  This enables Hardware BCH engine found on the OcteonTX processors to
+	  support ECC for NAND flash controller.
 
 config NAND_STM32_FMC2
 	bool "Support for NAND controller on STM32MP SoCs"
@@ -751,37 +751,37 @@ config SYS_NAND_BAD_BLOCK_POS
 config SYS_NAND_U_BOOT_LOCATIONS
 	bool "Define U-Boot binaries locations in NAND"
 	help
-	Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
-	This option should not be enabled when compiling U-Boot for boards
-	defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
-	file.
+	  Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
+	  This option should not be enabled when compiling U-Boot for boards
+	  defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
+	  file.
 
 config SYS_NAND_U_BOOT_OFFS
 	hex "Location in NAND to read U-Boot from"
 	default 0x800000 if NAND_SUNXI
 	depends on SYS_NAND_U_BOOT_LOCATIONS
 	help
-	Set the offset from the start of the nand where u-boot should be
-	loaded from.
+	  Set the offset from the start of the nand where u-boot should be
+	  loaded from.
 
 config SYS_NAND_U_BOOT_OFFS_REDUND
 	hex "Location in NAND to read U-Boot from"
 	default SYS_NAND_U_BOOT_OFFS
 	depends on SYS_NAND_U_BOOT_LOCATIONS
 	help
-	Set the offset from the start of the nand where the redundant u-boot
-	should be loaded from.
+	  Set the offset from the start of the nand where the redundant u-boot
+	  should be loaded from.
 
 config SPL_NAND_AM33XX_BCH
 	bool "Enables SPL-NAND driver which supports ELM based"
 	depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
 	default y
-        help
+	help
 	  Hardware ECC correction. This is useful for platforms which have ELM
 	  hardware engine and use NAND boot mode.
 	  Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
 	  so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
-          SPL-NAND driver with software ECC correction support.
+	  SPL-NAND driver with software ECC correction support.
 
 config SPL_NAND_DENALI
 	bool "Support Denali NAND controller for SPL"
@@ -810,6 +810,6 @@ config SYS_NAND_HW_ECC_OOBFIRST
 	bool "In SPL, read the OOB first and then the data from NAND"
 	depends on SPL_NAND_SIMPLE
 
-endif
+endif	# if SPL
 
-endif   # if NAND
+endif	# if MTD_RAW_NAND
-- 
2.39.2

[PATCH v2 4/6] mtd: nand: raw: atmel: Introduce optional debug commands

[Alexander Dahl]

For now adds one new command 'hsmc' with a single subcommand 'decode' to
read and display the content of the registers of the Static Memory
Controllers (SMC/HSMC) found in different at91 SoCs.  Needed to get a
better picture on what raw nand core and atmel nand controller driver
try to set as timings based on ONFI parameters of the connected NAND
chip.

Tested on SAMA5D2 and SAM9X60 based boards.  Example output:

    U-Boot> hsmc decode

    MCK rate: 200 MHz

    SMC_SETUP3:     0x00000002
    SMC_PULSE3:     0x06030703
    SMC_CYCLE3:     0x00060007
    SMC_MODE3:      0x001f0003
    NCS_RD: setup: 0 (0 ns), pulse: 6 (30 ns), hold: 0 (0 ns), cycle: 6 (30 ns)
       NRD: setup: 0 (0 ns), pulse: 3 (15 ns), hold: 3 (15 ns), cycle: 6 (30 ns)
    NCS_WR: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns)
       NWE: setup: 2 (10 ns), pulse: 3 (15 ns), hold: 2 (10 ns), cycle: 7 (35 ns)
    Standard read applied
    TDF optimization enabled
    TDF cycles: 15 (75 ns)
    Data Bus Width: 8-bit bus
    NWAIT Mode: 0
    Write operation controlled by NWE signal
    Read operation controlled by NRD signal

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Tested-by: Mihai Sain <mihai.sain@microchip.com>
---

Notes:
    v1:
    - initial patch version
    
    v2:
    - Use SMC register definitions
    - Implement atmel_hsmc_print_timings()
    - Improve hsmc command output
    - Collected tags

 drivers/mtd/nand/raw/Kconfig                 |   9 +
 drivers/mtd/nand/raw/atmel/nand-controller.c | 295 +++++++++++++++++++
 2 files changed, 304 insertions(+)

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index f6644899b0a..43057aa6c5b 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -50,12 +50,21 @@ config SYS_NAND_NO_SUBPAGE_WRITE
 
 config DM_NAND_ATMEL
 	bool "Support Atmel NAND controller with DM support"
+	select MFD_ATMEL_SMC
 	select SYS_NAND_SELF_INIT
 	imply SYS_NAND_USE_FLASH_BBT
 	help
 	  Enable this driver for NAND flash platforms using an Atmel NAND
 	  controller.
 
+config CMD_NAND_ATMEL_DEBUG
+	bool "Optional debug commands for Atmel NAND controller"
+	depends on DM_NAND_ATMEL
+	help
+	  Add commands for debugging internals of the Atmel NAND flash
+	  controller, for example:
+	  - Decode Static Memory Controller (SMC) registers
+
 config NAND_ATMEL
 	bool "Support Atmel NAND controller"
 	select SYS_NAND_SELF_INIT
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index e06523f3298..75da15c157b 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -51,11 +51,13 @@
 
 #include <asm-generic/gpio.h>
 #include <clk.h>
+#include <command.h>
 #include <dm/device_compat.h>
 #include <dm/devres.h>
 #include <dm/of_addr.h>
 #include <dm/of_access.h>
 #include <dm/uclass.h>
+#include <linux/bitops.h>
 #include <linux/completion.h>
 #include <linux/io.h>
 #include <linux/iopoll.h>
@@ -69,6 +71,7 @@
 #include <nand.h>
 #include <regmap.h>
 #include <syscon.h>
+#include <vsprintf.h>
 
 #include "pmecc.h"
 
@@ -216,6 +219,7 @@ struct atmel_nand_controller_ops {
 	int (*ecc_init)(struct nand_chip *chip);
 	int (*setup_data_interface)(struct atmel_nand *nand, int csline,
 				    const struct nand_data_interface *conf);
+	void (*print_info)(struct atmel_nand *nand, int csline);
 };
 
 struct atmel_nand_controller_caps {
@@ -2041,12 +2045,260 @@ err:
 	return ret;
 }
 
+#ifdef CONFIG_CMD_NAND_ATMEL_DEBUG
+u32 atmel_smc_decode_ncycles(u32 reg, u32 shift, u32 msbpos, u32 msbwidth, u32 msbfactor)
+{
+	/*
+	 *	Examples:
+	 *
+	 *	NRD setup length = (128 * NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles.
+	 *	NRD pulse length = (256 * NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles.
+	 *	Read cycle length = (NRD_CYCLE[8:7] * 256) + NRD_CYCLE[6:0] clock cycles.
+	 */
+
+	reg >>= shift;
+
+	u32 lsbmask = GENMASK(msbpos - 1, 0);
+	u32 msbmask = GENMASK(msbwidth - 1, 0) << msbpos;
+	u32 msb = (reg & msbmask) >> msbpos;
+	u32 lsb = (reg & lsbmask);
+
+	return msb * msbfactor + lsb;
+}
+
+static void atmel_smc_cs_conf_print_raw(struct atmel_smc_cs_conf *conf, int cs)
+{
+	printf("SMC_SETUP%d:     0x%08x\n", cs, conf->setup);
+	printf("SMC_PULSE%d:     0x%08x\n", cs, conf->pulse);
+	printf("SMC_CYCLE%d:     0x%08x\n", cs, conf->cycle);
+	printf("SMC_MODE%d:      0x%08x\n", cs, conf->mode);
+}
+
+static void atmel_hsmc_cs_conf_print_raw(struct atmel_smc_cs_conf *conf, int cs)
+{
+	printf("HSMC_SETUP%d:    0x%08x\n", cs, conf->setup);
+	printf("HSMC_PULSE%d:    0x%08x\n", cs, conf->pulse);
+	printf("HSMC_CYCLE%d:    0x%08x\n", cs, conf->cycle);
+	printf("HSMC_TIMINGS%d:  0x%08x\n", cs, conf->timings);
+	printf("HSMC_MODE%d:     0x%08x\n", cs, conf->mode);
+}
+
+static void atmel_smc_print_reg(const char *name, u32 setup, u32 pulse,
+				u32 cycle, u32 clk_period_ns)
+{
+	u32 hold = cycle - pulse - setup;
+
+	printf("%6s: setup: %u (%u ns), pulse: %u (%u ns), hold: %u (%u ns), cycle: %u (%u ns)\n",
+	       name, setup, setup * clk_period_ns, pulse, pulse * clk_period_ns,
+	       hold, hold * clk_period_ns, cycle, cycle * clk_period_ns);
+}
+
+static void atmel_smc_print_ncs_rd(struct atmel_smc_cs_conf *conf, u32 clk_period_ns)
+{
+	u32 ncs_rd_setup = atmel_smc_decode_ncycles(conf->setup,
+						    ATMEL_SMC_NCS_RD_SHIFT,
+						    5, 1, 128);
+	u32 ncs_rd_pulse = atmel_smc_decode_ncycles(conf->pulse,
+						    ATMEL_SMC_NCS_RD_SHIFT,
+						    6, 1, 256);
+	u32 nrd_cycle = atmel_smc_decode_ncycles(conf->cycle, 16, 7, 2, 256);
+
+	atmel_smc_print_reg("NCS_RD", ncs_rd_setup, ncs_rd_pulse,
+			    nrd_cycle, clk_period_ns);
+}
+
+static void atmel_smc_print_nrd(struct atmel_smc_cs_conf *conf, u32 clk_period_ns)
+{
+	u32 nrd_setup = atmel_smc_decode_ncycles(conf->setup,
+						 ATMEL_SMC_NRD_SHIFT,
+						 5, 1, 128);
+	u32 nrd_pulse = atmel_smc_decode_ncycles(conf->pulse,
+						 ATMEL_SMC_NRD_SHIFT,
+						 6, 1, 256);
+	u32 nrd_cycle = atmel_smc_decode_ncycles(conf->cycle, 16, 7, 2, 256);
+
+	atmel_smc_print_reg("NRD", nrd_setup, nrd_pulse, nrd_cycle, clk_period_ns);
+}
+
+static void atmel_smc_print_ncs_wr(struct atmel_smc_cs_conf *conf, u32 clk_period_ns)
+{
+	u32 ncs_wr_setup = atmel_smc_decode_ncycles(conf->setup,
+						    ATMEL_SMC_NCS_WR_SHIFT,
+						    5, 1, 128);
+	u32 ncs_wr_pulse = atmel_smc_decode_ncycles(conf->pulse,
+						    ATMEL_SMC_NCS_WR_SHIFT,
+						    6, 1, 256);
+	u32 nwe_cycle = atmel_smc_decode_ncycles(conf->cycle, 0, 7, 2, 256);
+
+	atmel_smc_print_reg("NCS_WR", ncs_wr_setup, ncs_wr_pulse,
+			    nwe_cycle, clk_period_ns);
+}
+
+static void atmel_smc_print_nwe(struct atmel_smc_cs_conf *conf, u32 clk_period_ns)
+{
+	u32 nwe_setup = atmel_smc_decode_ncycles(conf->setup,
+						 ATMEL_SMC_NWE_SHIFT,
+						 5, 1, 128);
+	u32 nwe_pulse = atmel_smc_decode_ncycles(conf->pulse,
+						 ATMEL_SMC_NWE_SHIFT,
+						 6, 1, 256);
+	u32 nwe_cycle = atmel_smc_decode_ncycles(conf->cycle, 0, 7, 2, 256);
+
+	atmel_smc_print_reg("NWE", nwe_setup, nwe_pulse, nwe_cycle, clk_period_ns);
+}
+
+static void atmel_smc_print_mode(struct atmel_smc_cs_conf *conf, u32 clk_period_ns)
+{
+	u32 tdf;
+	u8 dbw;
+
+	if (conf->mode & BIT(24)) {
+		printf("Asynchronous burst read in Page mode applied on the corresponding chip select\n");
+		printf("Page Size: %u-byte page\n",
+		       4 << ((conf->mode & GENMASK(29, 28)) >> 28));
+	} else {
+		printf("Standard read applied\n");
+	}
+
+	tdf = (conf->mode & GENMASK(19, 16)) >> 16;
+	printf("TDF optimization %s\n",
+	       (conf->mode & BIT(20)) ? "enabled" : "disabled");
+	printf("TDF cycles: %u (%u ns)\n", tdf, tdf * clk_period_ns);
+
+	dbw = 8 << ((conf->mode & GENMASK(13, 12)) >> 12);
+	printf("Data Bus Width: %u-bit bus\n", dbw);
+	if (dbw > 8)
+		printf("Byte %s access type\n",
+		       (conf->mode & BIT(8)) ? "write" : "select");
+
+	printf("NWAIT Mode: %lu\n", (conf->mode & GENMASK(5, 4)) >> 4);
+	printf("Write operation controlled by %s signal\n",
+	       (conf->mode & BIT(1)) ? "NWE" : "NCS");
+	printf("Read operation controlled by %s signal\n",
+	       (conf->mode & BIT(0)) ? "NRD" : "NCS");
+}
+
+static void atmel_hsmc_print_mode(struct atmel_smc_cs_conf *conf, u32 clk_period_ns)
+{
+	u32 tdf;
+	u8 dbw;
+
+	tdf = (conf->mode & GENMASK(19, 16)) >> 16;
+	printf("TDF optimization %s\n",
+	       (conf->mode & BIT(20)) ? "enabled" : "disabled");
+	printf("TDF cycles: %u (%u ns)\n", tdf, tdf * clk_period_ns);
+
+	dbw = 8 << ((conf->mode & BIT(12)) >> 12);
+	printf("Data Bus Width: %u-bit bus\n", dbw);
+	if (dbw > 8)
+		printf("Byte %s access type\n",
+		       (conf->mode & BIT(8)) ? "write" : "select");
+
+	printf("NWAIT Mode: %lu\n", (conf->mode & GENMASK(5, 4)) >> 4);
+	printf("Write operation controlled by %s signal\n",
+	       (conf->mode & BIT(1)) ? "NWE" : "NCS");
+	printf("Read operation controlled by %s signal\n",
+	       (conf->mode & BIT(0)) ? "NRD" : "NCS");
+}
+
+static void atmel_hsmc_print_timings(struct atmel_smc_cs_conf *conf, u32 clk_period_ns)
+{
+	u32 twb = atmel_smc_decode_ncycles(conf->timings,
+					   ATMEL_HSMC_TIMINGS_TWB_SHIFT,
+					   3, 1, 64);
+	u32 trr = atmel_smc_decode_ncycles(conf->timings,
+					   ATMEL_HSMC_TIMINGS_TRR_SHIFT,
+					   3, 1, 64);
+	u32 tar = atmel_smc_decode_ncycles(conf->timings,
+					   ATMEL_HSMC_TIMINGS_TAR_SHIFT,
+					   3, 1, 64);
+	u32 tadl = atmel_smc_decode_ncycles(conf->timings,
+					    ATMEL_HSMC_TIMINGS_TADL_SHIFT,
+					    3, 1, 64);
+	u32 tclr = atmel_smc_decode_ncycles(conf->timings,
+					    ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
+					    3, 1, 64);
+
+	printf("NFSEL (NAND Flash Selection) is %s\n",
+	       conf->timings & ATMEL_HSMC_TIMINGS_NFSEL ? "set" : "cleared");
+	printf("OCMS (Off Chip Memory Scrambling) is %s\n",
+	       conf->timings & ATMEL_HSMC_TIMINGS_OCMS ? "enabled" : "disabled");
+
+	printf("TWB (WEN High to REN to Busy): %u (%u ns)\n",
+	       twb, twb * clk_period_ns);
+	printf("TRR (Ready to REN Low Delay):  %u (%u ns)\n",
+	       trr, trr * clk_period_ns);
+	printf("TAR (ALE to REN Low Delay):    %u (%u ns)\n",
+	       tar, tar * clk_period_ns);
+	printf("TADL (ALE to Data Start):      %u (%u ns)\n",
+	       tadl, tadl * clk_period_ns);
+	printf("TCLR (CLE to REN Low Delay):   %u (%u ns)\n",
+	       tclr, tclr * clk_period_ns);
+}
+
+static void atmel_smc_print_info(struct atmel_nand *nand, int csline)
+{
+	struct atmel_nand_controller *nc;
+	struct atmel_smc_cs_conf smcconf;
+	struct atmel_nand_cs *cs;
+	u32 mck_period_ns;
+
+	nc = to_nand_controller(nand->controller);
+	cs = &nand->cs[csline];
+
+	atmel_smc_cs_conf_init(&smcconf);
+	atmel_smc_cs_conf_get(nc->smc, cs->id, &smcconf);
+
+	atmel_smc_cs_conf_print_raw(&smcconf, cs->id);
+
+	mck_period_ns = NSEC_PER_SEC / clk_get_rate(nc->mck);
+
+	atmel_smc_print_ncs_rd(&smcconf, mck_period_ns);
+	atmel_smc_print_nrd(&smcconf, mck_period_ns);
+	atmel_smc_print_ncs_wr(&smcconf, mck_period_ns);
+	atmel_smc_print_nwe(&smcconf, mck_period_ns);
+
+	atmel_smc_print_mode(&smcconf, mck_period_ns);
+}
+
+static void atmel_hsmc_print_info(struct atmel_nand *nand, int csline)
+{
+	struct atmel_hsmc_nand_controller *hsmc_nc;
+	struct atmel_nand_controller *nc;
+	struct atmel_smc_cs_conf smcconf;
+	struct atmel_nand_cs *cs;
+	u32 mck_period_ns;
+
+	nc = to_nand_controller(nand->controller);
+	hsmc_nc = to_hsmc_nand_controller(nand->controller);
+	cs = &nand->cs[csline];
+
+	atmel_smc_cs_conf_init(&smcconf);
+	atmel_hsmc_cs_conf_get(nc->smc, hsmc_nc->hsmc_layout, cs->id, &smcconf);
+
+	atmel_hsmc_cs_conf_print_raw(&smcconf, cs->id);
+
+	mck_period_ns = NSEC_PER_SEC / clk_get_rate(nc->mck);
+
+	atmel_smc_print_ncs_rd(&smcconf, mck_period_ns);
+	atmel_smc_print_nrd(&smcconf, mck_period_ns);
+	atmel_smc_print_ncs_wr(&smcconf, mck_period_ns);
+	atmel_smc_print_nwe(&smcconf, mck_period_ns);
+
+	atmel_hsmc_print_mode(&smcconf, mck_period_ns);
+	atmel_hsmc_print_timings(&smcconf, mck_period_ns);
+}
+#endif
+
 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
 	.probe = atmel_hsmc_nand_controller_probe,
 	.remove = atmel_hsmc_nand_controller_remove,
 	.ecc_init = atmel_hsmc_nand_ecc_init,
 	.nand_init = atmel_hsmc_nand_init,
 	.setup_data_interface = atmel_hsmc_nand_setup_data_interface,
+#ifdef CONFIG_CMD_NAND_ATMEL_DEBUG
+	.print_info = atmel_hsmc_print_info,
+#endif
 };
 
 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
@@ -2117,6 +2369,9 @@ static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
 	.ecc_init = atmel_nand_ecc_init,
 	.nand_init = atmel_smc_nand_init,
 	.setup_data_interface = atmel_smc_nand_setup_data_interface,
+#ifdef CONFIG_CMD_NAND_ATMEL_DEBUG
+	.print_info = atmel_smc_print_info,
+#endif
 };
 
 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
@@ -2247,3 +2502,43 @@ void board_nand_init(void)
 		printf("Failed to initialize NAND controller. (error %d)\n",
 		       ret);
 }
+
+#ifdef CONFIG_CMD_NAND_ATMEL_DEBUG
+static int do_hsmc_decode(struct cmd_tbl *cmdtp, int flag,
+			  int argc, char * const argv[])
+{
+	struct atmel_nand_controller *nc;
+	struct atmel_nand *nand;
+	struct nand_chip *chip;
+	struct mtd_info *mtd;
+	int i, j;
+
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
+		putc('\n');
+		mtd = get_nand_dev_by_index(i);
+		if (!mtd)
+			continue;
+
+		chip = mtd_to_nand(mtd);
+		nand = to_atmel_nand(chip);
+		nc = to_nand_controller(nand->controller);
+		printf("MCK rate: %lu MHz\n", clk_get_rate(nc->mck) / 1000000);
+		if (!nc->caps->ops->print_info)
+			continue;
+
+		for (j = 0; j < nand->numcs; j++) {
+			putc('\n');
+			nc->caps->ops->print_info(nand, j);
+		}
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static char hsmc_help_text[] =
+	"decode - Decode SMC registers\n"
+	;
+
+U_BOOT_CMD_WITH_SUBCMDS(hsmc, "Atmel Static Memory Controller (SMC) debugging", hsmc_help_text,
+			U_BOOT_SUBCMD_MKENT(decode, 1, 1, do_hsmc_decode));
+#endif
-- 
2.39.2

[PATCH v2 5/6] mtd: nand: raw: atmel: Fix comment in timings preparation

[Alexander Dahl]

Introduced with commit 6a8dfd57220d ("nand: atmel: Add DM based NAND
driver") when driver was initially ported from Linux.  The context
around this and especially the code itself suggests 'read' is meant
instead of write.

The fix is the same as accepted in Linux already with mainline Linux
kernel commit 1c60e027ffde ("mtd: nand: raw: atmel: Fix comment in
timings preparation").

Link: https://lore.kernel.org/linux-mtd/20240307172835.3453880-1-miquel.raynal@bootlin.com/T/#t
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---

Notes:
    v2:
    - initial patch version (not present in v1)

 drivers/mtd/nand/raw/atmel/nand-controller.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index 75da15c157b..bbafc88e44c 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -1271,7 +1271,7 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
 		return ret;
 
 	/*
-	 * The write cycle timing is directly matching tWC, but is also
+	 * The read cycle timing is directly matching tRC, but is also
 	 * dependent on the setup and hold timings we calculated earlier,
 	 * which gives:
 	 *
-- 
2.39.2

Re: [PATCH v2 5/6] mtd: nand: raw: atmel: Fix comment in timings preparation

[Michael Nazzareno Trimarchi]

On Wed, Mar 20, 2024 at 10:02 AM Alexander Dahl <ada@thorsis.com> wrote:
>
> Introduced with commit 6a8dfd57220d ("nand: atmel: Add DM based NAND
> driver") when driver was initially ported from Linux.  The context
> around this and especially the code itself suggests 'read' is meant
> instead of write.
>
> The fix is the same as accepted in Linux already with mainline Linux
> kernel commit 1c60e027ffde ("mtd: nand: raw: atmel: Fix comment in
> timings preparation").
>
> Link: https://lore.kernel.org/linux-mtd/20240307172835.3453880-1-miquel.raynal@bootlin.com/T/#t
> Signed-off-by: Alexander Dahl <ada@thorsis.com>
> ---
>
> Notes:
>     v2:
>     - initial patch version (not present in v1)
>
>  drivers/mtd/nand/raw/atmel/nand-controller.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
> index 75da15c157b..bbafc88e44c 100644
> --- a/drivers/mtd/nand/raw/atmel/nand-controller.c
> +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
> @@ -1271,7 +1271,7 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
>                 return ret;
>
>         /*
> -        * The write cycle timing is directly matching tWC, but is also
> +        * The read cycle timing is directly matching tRC, but is also
>          * dependent on the setup and hold timings we calculated earlier,
>          * which gives:
>          *
> --

Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>

> 2.39.2
>


-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

[PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'

[Alexander Dahl]

Override the ONFI timing mode at runtime.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
---

Notes:
    v2:
    - initial patch version (not present in v1)

 cmd/Kconfig                      | 10 ++++++
 cmd/nand.c                       | 61 ++++++++++++++++++++++++++++++++
 drivers/mtd/nand/raw/nand_base.c |  2 +-
 include/linux/mtd/rawnand.h      |  1 +
 4 files changed, 73 insertions(+), 1 deletion(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 61e280fb1a4..c39cc297306 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1421,6 +1421,7 @@ config CMD_NAND
 	  NAND support.
 
 if CMD_NAND
+
 config CMD_NAND_TRIMFFS
 	bool "nand write.trimffs"
 	default y if ARCH_SUNXI
@@ -1437,6 +1438,15 @@ config CMD_NAND_TORTURE
 	help
 	  NAND torture support.
 
+config CMD_NAND_ONFI
+	bool "nand onfi"
+	help
+	  Set ONFI timing modes explicitly.
+	  This is a debugging command to switch to slower ONFI timing
+	  modes for testing.
+	  In normal operation determining the timing mode automatically
+	  should work fine, and you don't need this.
+
 endif # CMD_NAND
 
 config CMD_NVME
diff --git a/cmd/nand.c b/cmd/nand.c
index fe834c4ac5c..2b83a5ad1b8 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -494,6 +494,48 @@ static void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev)
 	}
 }
 
+#ifdef CONFIG_CMD_NAND_ONFI
+static int do_nand_onfi(struct mtd_info *mtd, int mode)
+{
+	struct nand_chip *chip;
+	int ret;
+	int i;
+
+	if (mtd->type != MTD_NANDFLASH) {
+		printf("MTD device is no NAND flash!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	chip = mtd_to_nand(mtd);
+
+	if (mode < 0) {
+		printf("Reporting current ONFI settings not yet supported!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	ret = onfi_init_data_interface(chip, chip->data_interface,
+				       NAND_SDR_IFACE, mode);
+	if (ret) {
+		printf("onfi_init_data_interface() for mode %d failed with error %d\n",
+		       mode, ret);
+		return CMD_RET_FAILURE;
+	}
+
+	for (i = 0; i < chip->numchips; i++) {
+		chip->select_chip(mtd, i);
+		ret = nand_setup_data_interface(chip, i);
+		chip->select_chip(mtd, -1);
+		if (ret) {
+			printf("nand_setup_data_interface() for mode %d failed with error %d\n",
+			       mode, ret);
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	return CMD_RET_SUCCESS;
+}
+#endif
+
 static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc,
 		   char *const argv[])
 {
@@ -919,6 +961,21 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc,
 	}
 #endif
 
+#ifdef CONFIG_CMD_NAND_ONFI
+	/*
+	 * Syntax is:
+	 *   0    1     2
+	 *   nand onfi [mode]
+	 */
+	if (strcmp(cmd, "onfi") == 0) {
+		int mode = -1;
+
+		if (argc > 2)
+			mode = dectoul(argv[2], NULL);
+		return do_nand_onfi(mtd, mode);
+	}
+#endif
+
 usage:
 	return CMD_RET_USAGE;
 }
@@ -961,6 +1018,10 @@ U_BOOT_LONGHELP(nand,
 	"    bring nand to lock state or display locked pages\n"
 	"nand unlock[.allexcept] [offset] [size] - unlock section"
 #endif
+#ifdef CONFIG_CMD_NAND_ONFI
+	"\n"
+	"nand onfi [mode] - set ONFI mode\n"
+#endif
 #ifdef CONFIG_ENV_OFFSET_OOB
 	"\n"
 	"nand env.oob - environment offset in OOB of block 0 of"
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 688d17ba3c2..2384425a746 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -983,7 +983,7 @@ static int nand_onfi_set_timings(struct mtd_info *mtd, struct nand_chip *chip)
  *
  * Returns 0 for success or negative error code otherwise.
  */
-static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
+int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
 {
 	struct mtd_info *mtd = nand_to_mtd(chip);
 	int ret;
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 4abaf4734cf..07bc4cc9051 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -1315,6 +1315,7 @@ void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
 uint8_t nand_read_byte(struct mtd_info *mtd);
+int nand_setup_data_interface(struct nand_chip *chip, int chipnr);
 
 /* get timing characteristics from ONFI timing mode. */
 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
-- 
2.39.2

RE: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'

[Mihai.Sain]

Hi Alex,

------------------------------------------

Override the ONFI timing mode at runtime.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
---

Tested-by: Mihai Sain <mihai.sain@microchip.com>

I tested your new command on a new board/soc sam9x75-curiosity 😊
I find it very very useful !
I also rounded the master clock to 270 MHz 😊
Thanks.

=> nand info

Device 0: nand0, sector size 256 KiB
  Manufacturer  MACRONIX
  Model         MX30LF4G28AD
  Device size        512 MiB
  Page size         4096 b
  OOB size           256 b
  Erase size      262144 b
  ecc strength         8 bits
  ecc step size      512 b
  subpagesize       4096 b
  options       0x40004200
  bbt options   0x00028000

=> hsmc decode

MCK rate: 270 MHz

SMC_SETUP2:     0x00000004
SMC_PULSE2:     0x0c070d05
SMC_CYCLE2:     0x000c000d
SMC_MODE2:      0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 12 (36 ns), hold: 0 (0 ns), cycle: 12 (36 ns)
   NRD: setup: 0 (0 ns), pulse: 7 (21 ns), hold: 5 (15 ns), cycle: 12 (36 ns)
NCS_WR: setup: 0 (0 ns), pulse: 13 (39 ns), hold: 0 (0 ns), cycle: 13 (39 ns)
   NWE: setup: 4 (12 ns), pulse: 5 (15 ns), hold: 4 (12 ns), cycle: 13 (39 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

=> nand onfi 2
=> hsmc decode

MCK rate: 270 MHz

SMC_SETUP2:     0x00000003
SMC_PULSE2:     0x0e090e06
SMC_CYCLE2:     0x000e000e
SMC_MODE2:      0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 14 (42 ns), hold: 0 (0 ns), cycle: 14 (42 ns)
   NRD: setup: 0 (0 ns), pulse: 9 (27 ns), hold: 5 (15 ns), cycle: 14 (42 ns)
NCS_WR: setup: 0 (0 ns), pulse: 14 (42 ns), hold: 0 (0 ns), cycle: 14 (42 ns)
   NWE: setup: 3 (9 ns), pulse: 6 (18 ns), hold: 5 (15 ns), cycle: 14 (42 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

=> nand onfi 1
=> hsmc decode

MCK rate: 270 MHz

SMC_SETUP2:     0x00000003
SMC_PULSE2:     0x110a1109
SMC_CYCLE2:     0x00110011
SMC_MODE2:      0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 0 (0 ns), cycle: 17 (51 ns)
   NRD: setup: 0 (0 ns), pulse: 10 (30 ns), hold: 7 (21 ns), cycle: 17 (51 ns)
NCS_WR: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 0 (0 ns), cycle: 17 (51 ns)
   NWE: setup: 3 (9 ns), pulse: 9 (27 ns), hold: 5 (15 ns), cycle: 17 (51 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

=> nand onfi 3
=> hsmc decode

MCK rate: 270 MHz

SMC_SETUP2:     0x00000004
SMC_PULSE2:     0x0c070d05
SMC_CYCLE2:     0x000c000d
SMC_MODE2:      0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 12 (36 ns), hold: 0 (0 ns), cycle: 12 (36 ns)
   NRD: setup: 0 (0 ns), pulse: 7 (21 ns), hold: 5 (15 ns), cycle: 12 (36 ns)
NCS_WR: setup: 0 (0 ns), pulse: 13 (39 ns), hold: 0 (0 ns), cycle: 13 (39 ns)
   NWE: setup: 4 (12 ns), pulse: 5 (15 ns), hold: 4 (12 ns), cycle: 13 (39 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

=> nand torture 0x800000 0x800000

NAND torture: device 0 offset 0x800000 size 0x800000 (block size 0x40000)
 Passed: 32, failed: 0

=> clk dump

24000000              1        |       |-- mainck
 1080000000           1        |       |   |-- plla_fracck
 1080000000           1        |       |   |   |-- plla_divpmcck
 1080000000           1        |       |   |   |   `-- mck_pres
 270000000            8        |       |   |   |       `-- mck_div

Best regards,
Mihai Sain

RE: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'

[Mihai.Sain]

Hi Alex,

--------------------------------------------------------

Override the ONFI timing mode at runtime.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
---

I used the same board sam9x75-curiosity to test mode 5 😊

I forced in nfc driver the mode 5:
+       if (conf->timings.sdr.tRC_min < 20000)

And I ran the nand torture on 16 MiB:

=> nand onfi 0
=> hsmc decode

MCK rate: 270 MHz

SMC_SETUP2:     0x00000007
SMC_PULSE2:     0x22112211
SMC_CYCLE2:     0x00220022
SMC_MODE2:      0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 ns)
   NRD: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 17 (51 ns), cycle: 34 (102 ns)
NCS_WR: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 ns)
   NWE: setup: 7 (21 ns), pulse: 17 (51 ns), hold: 10 (30 ns), cycle: 34 (102 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

=> time nand torture 0x800000 0x1000000

NAND torture: device 0 offset 0x800000 size 0x1000000 (block size 0x40000)
 Passed: 64, failed: 0

time: 30.152 seconds

=> nand onfi 5
=> hsmc decode

MCK rate: 270 MHz

SMC_SETUP2:     0x00000001
SMC_PULSE2:     0x0b060804
SMC_CYCLE2:     0x000b0008
SMC_MODE2:      0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 11 (33 ns), hold: 0 (0 ns), cycle: 11 (33 ns)
   NRD: setup: 0 (0 ns), pulse: 6 (18 ns), hold: 5 (15 ns), cycle: 11 (33 ns)
NCS_WR: setup: 0 (0 ns), pulse: 8 (24 ns), hold: 0 (0 ns), cycle: 8 (24 ns)
   NWE: setup: 1 (3 ns), pulse: 4 (12 ns), hold: 3 (9 ns), cycle: 8 (24 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

=> time nand torture 0x800000 0x1000000

NAND torture: device 0 offset 0x800000 size 0x1000000 (block size 0x40000)
 Passed: 64, failed: 0

time: 15.891 seconds

Best regards,
Mihai Sain

Re: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'

[Michael Nazzareno Trimarchi]

Hi

I think this command can be really useful.

On Wed, Mar 20, 2024 at 3:09 PM <Mihai.Sain@microchip.com> wrote:
>
> Hi Alex,
>
> --------------------------------------------------------
>
> Override the ONFI timing mode at runtime.
>
> Signed-off-by: Alexander Dahl <ada@thorsis.com>
> ---
>
> I used the same board sam9x75-curiosity to test mode 5 😊
>
> I forced in nfc driver the mode 5:
> +       if (conf->timings.sdr.tRC_min < 20000)
>
> And I ran the nand torture on 16 MiB:
>
> => nand onfi 0
> => hsmc decode
>
> MCK rate: 270 MHz
>
> SMC_SETUP2:     0x00000007
> SMC_PULSE2:     0x22112211
> SMC_CYCLE2:     0x00220022
> SMC_MODE2:      0x001f0003
> NCS_RD: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 ns)
>    NRD: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 17 (51 ns), cycle: 34 (102 ns)
> NCS_WR: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 ns)
>    NWE: setup: 7 (21 ns), pulse: 17 (51 ns), hold: 10 (30 ns), cycle: 34 (102 ns)
> Standard read applied
> TDF optimization enabled
> TDF cycles: 15 (45 ns)
> Data Bus Width: 8-bit bus
> NWAIT Mode: 0
> Write operation controlled by NWE signal
> Read operation controlled by NRD signal
>
> => time nand torture 0x800000 0x1000000
>
> NAND torture: device 0 offset 0x800000 size 0x1000000 (block size 0x40000)
>  Passed: 64, failed: 0
>
> time: 30.152 seconds
>
> => nand onfi 5
> => hsmc decode
>
> MCK rate: 270 MHz
>
> SMC_SETUP2:     0x00000001
> SMC_PULSE2:     0x0b060804
> SMC_CYCLE2:     0x000b0008
> SMC_MODE2:      0x001f0003
> NCS_RD: setup: 0 (0 ns), pulse: 11 (33 ns), hold: 0 (0 ns), cycle: 11 (33 ns)
>    NRD: setup: 0 (0 ns), pulse: 6 (18 ns), hold: 5 (15 ns), cycle: 11 (33 ns)
> NCS_WR: setup: 0 (0 ns), pulse: 8 (24 ns), hold: 0 (0 ns), cycle: 8 (24 ns)
>    NWE: setup: 1 (3 ns), pulse: 4 (12 ns), hold: 3 (9 ns), cycle: 8 (24 ns)
> Standard read applied
> TDF optimization enabled
> TDF cycles: 15 (45 ns)
> Data Bus Width: 8-bit bus
> NWAIT Mode: 0
> Write operation controlled by NWE signal
> Read operation controlled by NRD signal
>
> => time nand torture 0x800000 0x1000000
>
> NAND torture: device 0 offset 0x800000 size 0x1000000 (block size 0x40000)
>  Passed: 64, failed: 0
>
> time: 15.891 seconds
>

Let try to have more testing on more boards

Michael

> Best regards,
> Mihai Sain



-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

RE: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'

[Mihai.Sain]

Hi Michael,

-------------------------------------------------------

I think this command can be really useful.
Let try to have more testing on more boards

---------------------------------------------------------

I managed to test the command on sama7g54-curiosity board.

I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 20000).

=> nand onfi 0
=> hsmc decode

MCK rate: 200 MHz

HSMC_SETUP3:    0x00000004
HSMC_PULSE3:    0x140a140a
HSMC_CYCLE3:    0x00140014
HSMC_TIMINGS3:  0x880805f4
HSMC_MODE3:     0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns)
   NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns)
NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns)
   NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns)
TDF optimization enabled
TDF cycles: 15 (75 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal
NFSEL (NAND Flash Selection) is set
OCMS (Off Chip Memory Scrambling) is disabled
TWB (WEN High to REN to Busy): 64 (320 ns)
TRR (Ready to REN Low Delay):  64 (320 ns)
TAR (ALE to REN Low Delay):    5 (25 ns)
TADL (ALE to Data Start):      71 (355 ns)
TCLR (CLE to REN Low Delay):   4 (20 ns)

=> time nand torture 0x1000000 0x1000000

NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000)
 Passed: 64, failed: 0

time: 22.638 seconds

=> nand onfi 5
=> hsmc decode

MCK rate: 200 MHz

HSMC_SETUP3:    0x00000001
HSMC_PULSE3:    0x07040502
HSMC_CYCLE3:    0x00070005
HSMC_TIMINGS3:  0x880402f2
HSMC_MODE3:     0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns)
   NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns)
NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns)
   NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns)
TDF optimization enabled
TDF cycles: 15 (75 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal
NFSEL (NAND Flash Selection) is set
OCMS (Off Chip Memory Scrambling) is disabled
TWB (WEN High to REN to Busy): 64 (320 ns)
TRR (Ready to REN Low Delay):  4 (20 ns)
TAR (ALE to REN Low Delay):    2 (10 ns)
TADL (ALE to Data Start):      71 (355 ns)
TCLR (CLE to REN Low Delay):   2 (10 ns)

=> time nand torture 0x1000000 0x1000000

NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000)
 Passed: 64, failed: 0

time: 11.661 seconds

=> nand info

Device 0: nand0, sector size 256 KiB
  Manufacturer  MACRONIX
  Model         MX30LF4G28AD
  Device size        512 MiB
  Page size         4096 b
  OOB size           256 b
  Erase size      262144 b
  ecc strength         8 bits
  ecc step size      512 b
  subpagesize       4096 b
  options       0x40004200
  bbt options   0x00028000

Best regards,
Mihai Sain

Re: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'

[Alexander Dahl]

Hello Mihai,

Am Fri, Mar 22, 2024 at 10:02:29AM +0000 schrieb Mihai.Sain@microchip.com:
> Hi Michael,
> 
> -------------------------------------------------------
> 
> I think this command can be really useful.
> Let try to have more testing on more boards
> 
> ---------------------------------------------------------
> 
> I managed to test the command on sama7g54-curiosity board.

Thanks for that.  Nice to see it works on other variants of the SoC
family.

> I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 20000).

You did a similar thing for the sam9x75.  These boards/socs seem to
have a newer SMC / HSMC controller than sama5d2 or sam9x60?  The
driver claims all the (H)SMC incarnations do _not_ support these EDO
modes 4 and 5.  Maybe someone could have a deeper look at the
datasheets of the newer SoCs and propose a patch to support those
newer controllers in the atmel nand-controller driver?  I guess the
problem is the same in Linux, right?

Greets
Alex

> 
> => nand onfi 0
> => hsmc decode
> 
> MCK rate: 200 MHz
> 
> HSMC_SETUP3:    0x00000004
> HSMC_PULSE3:    0x140a140a
> HSMC_CYCLE3:    0x00140014
> HSMC_TIMINGS3:  0x880805f4
> HSMC_MODE3:     0x001f0003
> NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns)
>    NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns)
> NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns)
>    NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns)
> TDF optimization enabled
> TDF cycles: 15 (75 ns)
> Data Bus Width: 8-bit bus
> NWAIT Mode: 0
> Write operation controlled by NWE signal
> Read operation controlled by NRD signal
> NFSEL (NAND Flash Selection) is set
> OCMS (Off Chip Memory Scrambling) is disabled
> TWB (WEN High to REN to Busy): 64 (320 ns)
> TRR (Ready to REN Low Delay):  64 (320 ns)
> TAR (ALE to REN Low Delay):    5 (25 ns)
> TADL (ALE to Data Start):      71 (355 ns)
> TCLR (CLE to REN Low Delay):   4 (20 ns)
> 
> => time nand torture 0x1000000 0x1000000
> 
> NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000)
>  Passed: 64, failed: 0
> 
> time: 22.638 seconds
> 
> => nand onfi 5
> => hsmc decode
> 
> MCK rate: 200 MHz
> 
> HSMC_SETUP3:    0x00000001
> HSMC_PULSE3:    0x07040502
> HSMC_CYCLE3:    0x00070005
> HSMC_TIMINGS3:  0x880402f2
> HSMC_MODE3:     0x001f0003
> NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns)
>    NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns)
> NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns)
>    NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns)
> TDF optimization enabled
> TDF cycles: 15 (75 ns)
> Data Bus Width: 8-bit bus
> NWAIT Mode: 0
> Write operation controlled by NWE signal
> Read operation controlled by NRD signal
> NFSEL (NAND Flash Selection) is set
> OCMS (Off Chip Memory Scrambling) is disabled
> TWB (WEN High to REN to Busy): 64 (320 ns)
> TRR (Ready to REN Low Delay):  4 (20 ns)
> TAR (ALE to REN Low Delay):    2 (10 ns)
> TADL (ALE to Data Start):      71 (355 ns)
> TCLR (CLE to REN Low Delay):   2 (10 ns)
> 
> => time nand torture 0x1000000 0x1000000
> 
> NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000)
>  Passed: 64, failed: 0
> 
> time: 11.661 seconds
> 
> => nand info
> 
> Device 0: nand0, sector size 256 KiB
>   Manufacturer  MACRONIX
>   Model         MX30LF4G28AD
>   Device size        512 MiB
>   Page size         4096 b
>   OOB size           256 b
>   Erase size      262144 b
>   ecc strength         8 bits
>   ecc step size      512 b
>   subpagesize       4096 b
>   options       0x40004200
>   bbt options   0x00028000
> 
> Best regards,
> Mihai Sain

Re: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'

[Michael Nazzareno Trimarchi]

HI

On Fri, Mar 22, 2024 at 12:46 PM Alexander Dahl <ada@thorsis.com> wrote:
>
> Hello Mihai,
>
> Am Fri, Mar 22, 2024 at 10:02:29AM +0000 schrieb Mihai.Sain@microchip.com:
> > Hi Michael,
> >
> > -------------------------------------------------------
> >
> > I think this command can be really useful.
> > Let try to have more testing on more boards
> >
> > ---------------------------------------------------------
> >
> > I managed to test the command on sama7g54-curiosity board.
>
> Thanks for that.  Nice to see it works on other variants of the SoC
> family.
>
> > I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 20000).
>
> You did a similar thing for the sam9x75.  These boards/socs seem to
> have a newer SMC / HSMC controller than sama5d2 or sam9x60?  The
> driver claims all the (H)SMC incarnations do _not_ support these EDO
> modes 4 and 5.  Maybe someone could have a deeper look at the
> datasheets of the newer SoCs and propose a patch to support those
> newer controllers in the atmel nand-controller driver?  I guess the
> problem is the same in Linux, right?
>
> Greets
> Alex
>
> >
> > => nand onfi 0
> > => hsmc decode
> >
> > MCK rate: 200 MHz
> >
> > HSMC_SETUP3:    0x00000004
> > HSMC_PULSE3:    0x140a140a
> > HSMC_CYCLE3:    0x00140014
> > HSMC_TIMINGS3:  0x880805f4
> > HSMC_MODE3:     0x001f0003
> > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns)
> >    NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns)
> > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns)
> >    NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns)
> > TDF optimization enabled
> > TDF cycles: 15 (75 ns)
> > Data Bus Width: 8-bit bus
> > NWAIT Mode: 0
> > Write operation controlled by NWE signal
> > Read operation controlled by NRD signal
> > NFSEL (NAND Flash Selection) is set
> > OCMS (Off Chip Memory Scrambling) is disabled
> > TWB (WEN High to REN to Busy): 64 (320 ns)
> > TRR (Ready to REN Low Delay):  64 (320 ns)
> > TAR (ALE to REN Low Delay):    5 (25 ns)
> > TADL (ALE to Data Start):      71 (355 ns)
> > TCLR (CLE to REN Low Delay):   4 (20 ns)
> >
> > => time nand torture 0x1000000 0x1000000
> >
> > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000)
> >  Passed: 64, failed: 0
> >
> > time: 22.638 seconds
> >
> > => nand onfi 5
> > => hsmc decode
> >
> > MCK rate: 200 MHz
> >
> > HSMC_SETUP3:    0x00000001
> > HSMC_PULSE3:    0x07040502
> > HSMC_CYCLE3:    0x00070005
> > HSMC_TIMINGS3:  0x880402f2
> > HSMC_MODE3:     0x001f0003
> > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns)
> >    NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns)
> > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns)
> >    NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns)
> > TDF optimization enabled
> > TDF cycles: 15 (75 ns)
> > Data Bus Width: 8-bit bus
> > NWAIT Mode: 0
> > Write operation controlled by NWE signal
> > Read operation controlled by NRD signal
> > NFSEL (NAND Flash Selection) is set
> > OCMS (Off Chip Memory Scrambling) is disabled
> > TWB (WEN High to REN to Busy): 64 (320 ns)
> > TRR (Ready to REN Low Delay):  4 (20 ns)
> > TAR (ALE to REN Low Delay):    2 (10 ns)
> > TADL (ALE to Data Start):      71 (355 ns)
> > TCLR (CLE to REN Low Delay):   2 (10 ns)
> >
> > => time nand torture 0x1000000 0x1000000
> >
> > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000)
> >  Passed: 64, failed: 0
> >
> > time: 11.661 seconds
> >
> > => nand info
> >
> > Device 0: nand0, sector size 256 KiB
> >   Manufacturer  MACRONIX
> >   Model         MX30LF4G28AD
> >   Device size        512 MiB
> >   Page size         4096 b
> >   OOB size           256 b
> >   Erase size      262144 b
> >   ecc strength         8 bits
> >   ecc step size      512 b
> >   subpagesize       4096 b
> >   options       0x40004200
> >   bbt options   0x00028000
> >
> > Best regards,
> > Mihai Sain

I'm in favor to have it even cover by one soc family. I would like to
confirm on imx6 and imx8. If you are not in a rush.
Let's us test too

Michael

-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'

[Alexander Dahl]

Hello Michael,

Am Fri, Mar 22, 2024 at 12:54:27PM +0100 schrieb Michael Nazzareno Trimarchi:
> HI
> 
> On Fri, Mar 22, 2024 at 12:46 PM Alexander Dahl <ada@thorsis.com> wrote:
> >
> > Hello Mihai,
> >
> > Am Fri, Mar 22, 2024 at 10:02:29AM +0000 schrieb Mihai.Sain@microchip.com:
> > > Hi Michael,
> > >
> > > -------------------------------------------------------
> > >
> > > I think this command can be really useful.
> > > Let try to have more testing on more boards
> > >
> > > ---------------------------------------------------------
> > >
> > > I managed to test the command on sama7g54-curiosity board.
> >
> > Thanks for that.  Nice to see it works on other variants of the SoC
> > family.
> >
> > > I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 20000).
> >
> > You did a similar thing for the sam9x75.  These boards/socs seem to
> > have a newer SMC / HSMC controller than sama5d2 or sam9x60?  The
> > driver claims all the (H)SMC incarnations do _not_ support these EDO
> > modes 4 and 5.  Maybe someone could have a deeper look at the
> > datasheets of the newer SoCs and propose a patch to support those
> > newer controllers in the atmel nand-controller driver?  I guess the
> > problem is the same in Linux, right?
> >
> > Greets
> > Alex
> >
> > >
> > > => nand onfi 0
> > > => hsmc decode
> > >
> > > MCK rate: 200 MHz
> > >
> > > HSMC_SETUP3:    0x00000004
> > > HSMC_PULSE3:    0x140a140a
> > > HSMC_CYCLE3:    0x00140014
> > > HSMC_TIMINGS3:  0x880805f4
> > > HSMC_MODE3:     0x001f0003
> > > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns)
> > >    NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns)
> > > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns)
> > >    NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns)
> > > TDF optimization enabled
> > > TDF cycles: 15 (75 ns)
> > > Data Bus Width: 8-bit bus
> > > NWAIT Mode: 0
> > > Write operation controlled by NWE signal
> > > Read operation controlled by NRD signal
> > > NFSEL (NAND Flash Selection) is set
> > > OCMS (Off Chip Memory Scrambling) is disabled
> > > TWB (WEN High to REN to Busy): 64 (320 ns)
> > > TRR (Ready to REN Low Delay):  64 (320 ns)
> > > TAR (ALE to REN Low Delay):    5 (25 ns)
> > > TADL (ALE to Data Start):      71 (355 ns)
> > > TCLR (CLE to REN Low Delay):   4 (20 ns)
> > >
> > > => time nand torture 0x1000000 0x1000000
> > >
> > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000)
> > >  Passed: 64, failed: 0
> > >
> > > time: 22.638 seconds
> > >
> > > => nand onfi 5
> > > => hsmc decode
> > >
> > > MCK rate: 200 MHz
> > >
> > > HSMC_SETUP3:    0x00000001
> > > HSMC_PULSE3:    0x07040502
> > > HSMC_CYCLE3:    0x00070005
> > > HSMC_TIMINGS3:  0x880402f2
> > > HSMC_MODE3:     0x001f0003
> > > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns)
> > >    NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns)
> > > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns)
> > >    NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns)
> > > TDF optimization enabled
> > > TDF cycles: 15 (75 ns)
> > > Data Bus Width: 8-bit bus
> > > NWAIT Mode: 0
> > > Write operation controlled by NWE signal
> > > Read operation controlled by NRD signal
> > > NFSEL (NAND Flash Selection) is set
> > > OCMS (Off Chip Memory Scrambling) is disabled
> > > TWB (WEN High to REN to Busy): 64 (320 ns)
> > > TRR (Ready to REN Low Delay):  4 (20 ns)
> > > TAR (ALE to REN Low Delay):    2 (10 ns)
> > > TADL (ALE to Data Start):      71 (355 ns)
> > > TCLR (CLE to REN Low Delay):   2 (10 ns)
> > >
> > > => time nand torture 0x1000000 0x1000000
> > >
> > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000)
> > >  Passed: 64, failed: 0
> > >
> > > time: 11.661 seconds
> > >
> > > => nand info
> > >
> > > Device 0: nand0, sector size 256 KiB
> > >   Manufacturer  MACRONIX
> > >   Model         MX30LF4G28AD
> > >   Device size        512 MiB
> > >   Page size         4096 b
> > >   OOB size           256 b
> > >   Erase size      262144 b
> > >   ecc strength         8 bits
> > >   ecc step size      512 b
> > >   subpagesize       4096 b
> > >   options       0x40004200
> > >   bbt options   0x00028000
> > >
> > > Best regards,
> > > Mihai Sain
> 
> I'm in favor to have it even cover by one soc family. I would like to
> confirm on imx6 and imx8. If you are not in a rush.
> Let's us test too

Agreed.  This is a generic nand command, so it would of course be
reasonable to test it on multiple nand controllers.  I'm afraid I
currently have only at91 boards on my desk for which I have a recent
U-Boot _and_ a NAND chip soldered.  So take your time for this patch.

If you don't mind I would be happy if you could merge the four trivial
patches which do not add new features and which already got your
reviewed-by in the next cycle already, and let those other patches
with the new subcommands for debugging be tested as long as needed.

Kind regards
Alex

> 
> Michael
> 
> -- 
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> michael@amarulasolutions.com
> __________________________________
> 
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> info@amarulasolutions.com
> www.amarulasolutions.com

Re: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'

[Michael Nazzareno Trimarchi]

HI

On Fri, Mar 22, 2024 at 1:02 PM Alexander Dahl <ada@thorsis.com> wrote:
>
> Hello Michael,
>
> Am Fri, Mar 22, 2024 at 12:54:27PM +0100 schrieb Michael Nazzareno Trimarchi:
> > HI
> >
> > On Fri, Mar 22, 2024 at 12:46 PM Alexander Dahl <ada@thorsis.com> wrote:
> > >
> > > Hello Mihai,
> > >
> > > Am Fri, Mar 22, 2024 at 10:02:29AM +0000 schrieb Mihai.Sain@microchip.com:
> > > > Hi Michael,
> > > >
> > > > -------------------------------------------------------
> > > >
> > > > I think this command can be really useful.
> > > > Let try to have more testing on more boards
> > > >
> > > > ---------------------------------------------------------
> > > >
> > > > I managed to test the command on sama7g54-curiosity board.
> > >
> > > Thanks for that.  Nice to see it works on other variants of the SoC
> > > family.
> > >
> > > > I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 20000).
> > >
> > > You did a similar thing for the sam9x75.  These boards/socs seem to
> > > have a newer SMC / HSMC controller than sama5d2 or sam9x60?  The
> > > driver claims all the (H)SMC incarnations do _not_ support these EDO
> > > modes 4 and 5.  Maybe someone could have a deeper look at the
> > > datasheets of the newer SoCs and propose a patch to support those
> > > newer controllers in the atmel nand-controller driver?  I guess the
> > > problem is the same in Linux, right?
> > >
> > > Greets
> > > Alex
> > >
> > > >
> > > > => nand onfi 0
> > > > => hsmc decode
> > > >
> > > > MCK rate: 200 MHz
> > > >
> > > > HSMC_SETUP3:    0x00000004
> > > > HSMC_PULSE3:    0x140a140a
> > > > HSMC_CYCLE3:    0x00140014
> > > > HSMC_TIMINGS3:  0x880805f4
> > > > HSMC_MODE3:     0x001f0003
> > > > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns)
> > > >    NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns)
> > > > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns)
> > > >    NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns)
> > > > TDF optimization enabled
> > > > TDF cycles: 15 (75 ns)
> > > > Data Bus Width: 8-bit bus
> > > > NWAIT Mode: 0
> > > > Write operation controlled by NWE signal
> > > > Read operation controlled by NRD signal
> > > > NFSEL (NAND Flash Selection) is set
> > > > OCMS (Off Chip Memory Scrambling) is disabled
> > > > TWB (WEN High to REN to Busy): 64 (320 ns)
> > > > TRR (Ready to REN Low Delay):  64 (320 ns)
> > > > TAR (ALE to REN Low Delay):    5 (25 ns)
> > > > TADL (ALE to Data Start):      71 (355 ns)
> > > > TCLR (CLE to REN Low Delay):   4 (20 ns)
> > > >
> > > > => time nand torture 0x1000000 0x1000000
> > > >
> > > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000)
> > > >  Passed: 64, failed: 0
> > > >
> > > > time: 22.638 seconds
> > > >
> > > > => nand onfi 5
> > > > => hsmc decode
> > > >
> > > > MCK rate: 200 MHz
> > > >
> > > > HSMC_SETUP3:    0x00000001
> > > > HSMC_PULSE3:    0x07040502
> > > > HSMC_CYCLE3:    0x00070005
> > > > HSMC_TIMINGS3:  0x880402f2
> > > > HSMC_MODE3:     0x001f0003
> > > > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns)
> > > >    NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns)
> > > > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns)
> > > >    NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns)
> > > > TDF optimization enabled
> > > > TDF cycles: 15 (75 ns)
> > > > Data Bus Width: 8-bit bus
> > > > NWAIT Mode: 0
> > > > Write operation controlled by NWE signal
> > > > Read operation controlled by NRD signal
> > > > NFSEL (NAND Flash Selection) is set
> > > > OCMS (Off Chip Memory Scrambling) is disabled
> > > > TWB (WEN High to REN to Busy): 64 (320 ns)
> > > > TRR (Ready to REN Low Delay):  4 (20 ns)
> > > > TAR (ALE to REN Low Delay):    2 (10 ns)
> > > > TADL (ALE to Data Start):      71 (355 ns)
> > > > TCLR (CLE to REN Low Delay):   2 (10 ns)
> > > >
> > > > => time nand torture 0x1000000 0x1000000
> > > >
> > > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000)
> > > >  Passed: 64, failed: 0
> > > >
> > > > time: 11.661 seconds
> > > >
> > > > => nand info
> > > >
> > > > Device 0: nand0, sector size 256 KiB
> > > >   Manufacturer  MACRONIX
> > > >   Model         MX30LF4G28AD
> > > >   Device size        512 MiB
> > > >   Page size         4096 b
> > > >   OOB size           256 b
> > > >   Erase size      262144 b
> > > >   ecc strength         8 bits
> > > >   ecc step size      512 b
> > > >   subpagesize       4096 b
> > > >   options       0x40004200
> > > >   bbt options   0x00028000
> > > >
> > > > Best regards,
> > > > Mihai Sain
> >
> > I'm in favor to have it even cover by one soc family. I would like to
> > confirm on imx6 and imx8. If you are not in a rush.
> > Let's us test too
>
> Agreed.  This is a generic nand command, so it would of course be
> reasonable to test it on multiple nand controllers.  I'm afraid I
> currently have only at91 boards on my desk for which I have a recent
> U-Boot _and_ a NAND chip soldered.  So take your time for this patch.
>
> If you don't mind I would be happy if you could merge the four trivial
> patches which do not add new features and which already got your
> reviewed-by in the next cycle already, and let those other patches
> with the new subcommands for debugging be tested as long as needed.
>

I think Dario already queue them

Michael

> Kind regards
> Alex
>
> >
> > Michael
> >
> > --
> > Michael Nazzareno Trimarchi
> > Co-Founder & Chief Executive Officer
> > M. +39 347 913 2170
> > michael@amarulasolutions.com
> > __________________________________
> >
> > Amarula Solutions BV
> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> > T. +31 (0)85 111 9172
> > info@amarulasolutions.com
> > www.amarulasolutions.com



-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [PATCH v2 0/6] mtd: nand: raw: Collected improvements

[Dario Binacchi]

Hi Alexander,

On Wed, Mar 20, 2024 at 10:02 AM Alexander Dahl <ada@thorsis.com> wrote:
>
> Hello everyone,
>
> while working on NAND flash support for a custom board based on the at91
> SAM9X60 SoC I stumbled over some issues in the raw nand subsystem.
>
> Four of six patches are minor fixes.
>
> Patch 4 introduces a new subcommand for the new atmel nand controller
> driver.  Patch 6 introduces a new subcommand for the nand command to
> override ONFI timing mode.  Both are are for debugging purposes only and
> thus optional, and need to be enabled through menu.  Both helped me a
> lot when investigating issues.
>
> Series is based on upstream next branch, but should also apply to master
> cleanly.
>
> Greets
> Alex
>
> v1:
>
> Link: https://lore.kernel.org/u-boot/20240307091014.39796-1-ada@thorsis.com/T/#t
>
> v2:
>
> - rebased on recent next
> - collected tags
> - improved patch 4 after feedback from Mihai
> - added new patch 5 with another help text fix
> - added new patch 6 with a new debug command
> - reworded cover letter
>
> See per patch changes in patches for more detailed changes.
>
> Alexander Dahl (6):
>   mtd: nand: raw: Use macro nand_to_mtd() where appropriate
>   mtd: nand: raw: Port another option flag from Linux
>   mtd: nand: raw: Fix (most) Kconfig indentation
>   mtd: nand: raw: atmel: Introduce optional debug commands
>   mtd: nand: raw: atmel: Fix comment in timings preparation
>   cmd: nand: Add new optional sub-command 'onfi'
>
>  cmd/Kconfig                                  |  10 +
>  cmd/nand.c                                   |  61 ++++
>  drivers/mtd/nand/raw/Kconfig                 | 115 +++----
>  drivers/mtd/nand/raw/atmel/nand-controller.c | 299 ++++++++++++++++++-
>  drivers/mtd/nand/raw/nand_base.c             |   8 +-
>  include/linux/mtd/rawnand.h                  |   8 +
>  6 files changed, 441 insertions(+), 60 deletions(-)
>
>
> base-commit: f048104999db28d49362201eaebfc91adb14f47c
> --
> 2.39.2
>
Applied to nand-next the first 4 patches.
For the others, we will conduct further testing before applying them.

Thanks and regards,
Dario
-- 

Dario Binacchi

Senior Embedded Linux Developer

dario.binacchi@amarulasolutions.com

__________________________________


Amarula Solutions SRL

Via Le Canevare 30, 31100 Treviso, Veneto, IT

T. +39 042 243 5310
info@amarulasolutions.com

www.amarulasolutions.com

Re: [PATCH v2 0/6] mtd: nand: raw: Collected improvements

[Alexander Dahl]

Hello Dario,

Am Sun, Apr 14, 2024 at 03:41:38PM +0200 schrieb Dario Binacchi:
> Hi Alexander,
> 
> On Wed, Mar 20, 2024 at 10:02 AM Alexander Dahl <ada@thorsis.com> wrote:
> >
> > Hello everyone,
> >
> > while working on NAND flash support for a custom board based on the at91
> > SAM9X60 SoC I stumbled over some issues in the raw nand subsystem.
> >
> > Four of six patches are minor fixes.
> >
> > Patch 4 introduces a new subcommand for the new atmel nand controller
> > driver.  Patch 6 introduces a new subcommand for the nand command to
> > override ONFI timing mode.  Both are are for debugging purposes only and
> > thus optional, and need to be enabled through menu.  Both helped me a
> > lot when investigating issues.
> >
> > Series is based on upstream next branch, but should also apply to master
> > cleanly.
> >
> > Greets
> > Alex
> >
> > v1:
> >
> > Link: https://lore.kernel.org/u-boot/20240307091014.39796-1-ada@thorsis.com/T/#t
> >
> > v2:
> >
> > - rebased on recent next
> > - collected tags
> > - improved patch 4 after feedback from Mihai
> > - added new patch 5 with another help text fix
> > - added new patch 6 with a new debug command
> > - reworded cover letter
> >
> > See per patch changes in patches for more detailed changes.
> >
> > Alexander Dahl (6):
> >   mtd: nand: raw: Use macro nand_to_mtd() where appropriate
> >   mtd: nand: raw: Port another option flag from Linux
> >   mtd: nand: raw: Fix (most) Kconfig indentation
> >   mtd: nand: raw: atmel: Introduce optional debug commands
> >   mtd: nand: raw: atmel: Fix comment in timings preparation
> >   cmd: nand: Add new optional sub-command 'onfi'
> >
> >  cmd/Kconfig                                  |  10 +
> >  cmd/nand.c                                   |  61 ++++
> >  drivers/mtd/nand/raw/Kconfig                 | 115 +++----
> >  drivers/mtd/nand/raw/atmel/nand-controller.c | 299 ++++++++++++++++++-
> >  drivers/mtd/nand/raw/nand_base.c             |   8 +-
> >  include/linux/mtd/rawnand.h                  |   8 +
> >  6 files changed, 441 insertions(+), 60 deletions(-)
> >
> >
> > base-commit: f048104999db28d49362201eaebfc91adb14f47c
> > --
> > 2.39.2
> >
> Applied to nand-next the first 4 patches.
> For the others, we will conduct further testing before applying them.

Thanks so far.  :-)

I have another fix for the atmel raw nand driver, which I forgot to
send with this series.  I could add it to v3.  Or should I send it
separately?

Greets
Alex

Re: [PATCH v2 0/6] mtd: nand: raw: Collected improvements

[Dario Binacchi]

Hello Alexander,

On Mon, Apr 15, 2024 at 8:13 AM Alexander Dahl <ada@thorsis.com> wrote:
>
> Hello Dario,
>
> Am Sun, Apr 14, 2024 at 03:41:38PM +0200 schrieb Dario Binacchi:
> > Hi Alexander,
> >
> > On Wed, Mar 20, 2024 at 10:02 AM Alexander Dahl <ada@thorsis.com> wrote:
> > >
> > > Hello everyone,
> > >
> > > while working on NAND flash support for a custom board based on the at91
> > > SAM9X60 SoC I stumbled over some issues in the raw nand subsystem.
> > >
> > > Four of six patches are minor fixes.
> > >
> > > Patch 4 introduces a new subcommand for the new atmel nand controller
> > > driver.  Patch 6 introduces a new subcommand for the nand command to
> > > override ONFI timing mode.  Both are are for debugging purposes only and
> > > thus optional, and need to be enabled through menu.  Both helped me a
> > > lot when investigating issues.
> > >
> > > Series is based on upstream next branch, but should also apply to master
> > > cleanly.
> > >
> > > Greets
> > > Alex
> > >
> > > v1:
> > >
> > > Link: https://lore.kernel.org/u-boot/20240307091014.39796-1-ada@thorsis.com/T/#t
> > >
> > > v2:
> > >
> > > - rebased on recent next
> > > - collected tags
> > > - improved patch 4 after feedback from Mihai
> > > - added new patch 5 with another help text fix
> > > - added new patch 6 with a new debug command
> > > - reworded cover letter
> > >
> > > See per patch changes in patches for more detailed changes.
> > >
> > > Alexander Dahl (6):
> > >   mtd: nand: raw: Use macro nand_to_mtd() where appropriate
> > >   mtd: nand: raw: Port another option flag from Linux
> > >   mtd: nand: raw: Fix (most) Kconfig indentation
> > >   mtd: nand: raw: atmel: Introduce optional debug commands
> > >   mtd: nand: raw: atmel: Fix comment in timings preparation
> > >   cmd: nand: Add new optional sub-command 'onfi'
> > >
> > >  cmd/Kconfig                                  |  10 +
> > >  cmd/nand.c                                   |  61 ++++
> > >  drivers/mtd/nand/raw/Kconfig                 | 115 +++----
> > >  drivers/mtd/nand/raw/atmel/nand-controller.c | 299 ++++++++++++++++++-
> > >  drivers/mtd/nand/raw/nand_base.c             |   8 +-
> > >  include/linux/mtd/rawnand.h                  |   8 +
> > >  6 files changed, 441 insertions(+), 60 deletions(-)
> > >
> > >
> > > base-commit: f048104999db28d49362201eaebfc91adb14f47c
> > > --
> > > 2.39.2
> > >
> > Applied to nand-next the first 4 patches.
> > For the others, we will conduct further testing before applying them.
>
> Thanks so far.  :-)
>
> I have another fix for the atmel raw nand driver, which I forgot to
> send with this series.  I could add it to v3.

Of course, feel free to add it to version 3.

Thanks and regards,
Dario

> Or should I send it
> separately?
>
> Greets
> Alex



-- 

Dario Binacchi

Senior Embedded Linux Developer

dario.binacchi@amarulasolutions.com

__________________________________


Amarula Solutions SRL

Via Le Canevare 30, 31100 Treviso, Veneto, IT

T. +39 042 243 5310
info@amarulasolutions.com

www.amarulasolutions.com