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[65.184.193.66]) by smtp.gmail.com with ESMTPSA id j1-20020a05620a000100b0078bc5612d15sm209408qki.127.2024.03.28.13.02.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 13:02:11 -0700 (PDT) Date: Thu, 28 Mar 2024 16:02:09 -0400 From: Tom Rini To: Chris Morgan Cc: Eugen Hristev , Kever Yang , Chris Morgan , u-boot@lists.denx.de, xypron.glpk@gmx.de, cym@rock-chips.com, philipp.tomsich@vrull.eu, sjg@chromium.org, jonas@kwiboo.se Subject: Re: [PATCH 1/2] rockchip: rk3588: Add support for ATAG parsing Message-ID: <20240328200209.GE3442575@bill-the-cat> References: <20240326204944.1572667-1-macroalpha82@gmail.com> <20240326204944.1572667-2-macroalpha82@gmail.com> <9541747b-b05c-4bb2-bf73-d720659905d2@collabora.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="MjA6wiX3vGFfPdSp" Content-Disposition: inline In-Reply-To: X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean --MjA6wiX3vGFfPdSp Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Mar 27, 2024 at 10:03:11AM -0500, Chris Morgan wrote: > On Wed, Mar 27, 2024 at 04:21:49PM +0200, Eugen Hristev wrote: > > On 3/27/24 15:32, Chris Morgan wrote: > > > On Wed, Mar 27, 2024 at 06:32:06PM +0800, Kever Yang wrote: > > >> Hi Chris, > > >> > > >> =A0=A0=A0 The ATAGS is used for passing parameter from bootloader to= kernel at > > >> first, which has been replaced by DTB now for ARM platform. > > >> > > >> =A0=A0=A0 And Rockchip using ATAGs for passing parameter like dram m= emory > > >> size/board uart in different boot process like DRAM init binary/ TPL= /SPL to > > >> U-Boot since 2018. > > >> > > >> =A0=A0=A0 And almost at the same time, Simon add bloblist for mainli= ne U-Boot > > >> which for similar purpose. > > >> > > >> =A0=A0=A0 So I'm not sure if this ATAGS should be accept in mainline= U-Boot or > > >> not, even for rockchip platform only seems some kind of regression f= or this > > >> feature support. > > >> > > >> > > >> Hi Simon and Tom, > > >> > > >> =A0=A0=A0=A0 Could you help to give some suggestion for this? > > >> > > >=20 > > > I really meant to do this as an "RFC", so I apologize in advance for > > > possibly causing more work in treating this as a full-fledged patch. > > >=20 > > > The problem I'm trying to solve is that I've got 2 boards, a Rock 5B > > > as well as an Indiedroid Nova both with 16GB of RAM. I noticed that > > > without the memory holes the Rock 5B defined in my Indiedroid it would > > > also fail to boot. I've got 2 other boards as well with less than 16GB > > > of RAM which seem to work fine without any holes (a 4GB Indiedroid No= va > > > prototype and a GameForce Ace with 12GB of RAM). > >=20 > > Hi, > >=20 > > When I initially added these holes in the memory, I tried to ask Rockch= ip what are > > the holes for. I didn't get any answer, however the patches to reserve = the holes > > were accepted. > > If we could get more information about why the holes are there, if that= area is > > specific to something, or that it's fixed in a per-SoC basis, we could = reserve it > > by hardcoding in the Linux DT, without the need for ATAGs. > > Without real information, we cannot be sure that for other variants of = the SoC or > > some other bootrom configuration, the holes will not change/move. > >=20 > > Eugen >=20 > It's not *just* about the holes, but also making sure we use the full > extent of the RAM. For example on my 4GB Indiedroid Nova the existing > logic ignores about 256MB of RAM that's otherwise present. When we > use the existing code the RAM map reported by Linux is as follows: >=20 > [ 0.000000] Early memory node ranges > [ 0.000000] node 0: [mem 0x0000000000200000-0x00000000efffffff] >=20 > Whereas when we do ATAGS parsing to set the banks we get the following: >=20 > [ 0.000000] Early memory node ranges > [ 0.000000] node 0: [mem 0x0000000000200000-0x00000000efffffff] > [ 0.000000] node 0: [mem 0x00000001f0000000-0x00000001ffffffff] >=20 > So basically the issue is two-fold... one we need to create the memory > holes when necessary, and two the current method of defining memory > banks leaves some RAM unallocated. Parsing the ATAGS does both of these, > I'm just curious if it's the RIGHT way or there's something else I'm > missing... It's unfortunate that all of this is in the wild, from the Rockchip side. The best answer is that the platform should be passing all of this along via bloblist. I would hope that future platforms will do that. For now yes, I guess we need to constrain this ATAG parsing to rockchip as much as we can and use it. --=20 Tom --MjA6wiX3vGFfPdSp Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmYFzMEACgkQFHw5/5Y0 tyyf1gv/VP2XGhHUt1fU6NYqexSsLQ1oGSq3zHbxOuM1uLV+HJKLPRUHYKSzXCqA IjKYLGH7rGO+qC4R55rN/7WSJfkldydMTUnnu9/LcE25S8jGruXtS+DR0eRCtvE4 tNoJJ6X9QizwN7Xa3+hLSkTO7kh9a4+t9MWBvKoESh0uNNKPm3ZCKn+wFmoE4F+Z 8HrawBsbQDyWJuQJYh1dykN18AIU3XPy22H0vKjlugs1ITDNE+FixjKBIwakND+B 8+puDsBHcM42mwIXbQOMCJxYh3FZQUidGMWOexi17lqDahSk1NkyA5QJeAca4ts5 t+MFBA4AR8NihbL1VKliVoF1mYhckxVOj+hNJjmbeQlBfsseZ4yqQOD8QJuAMmMi EUIDzujLEfwN2ixHIxY19Z+v0fjgv0jmSrushv/YxZYCnzfuwOB+FZ6i6BqunBgQ f9FRpm7N2gOFcxaFnQ+nGadO73d2tkZuYvUtUcQzOPlg8vnIYdG8l5HhxbNG1FUC J3fcTBx6 =2dYh -----END PGP SIGNATURE----- --MjA6wiX3vGFfPdSp--