[V2 PATCH 0/2] Update RAM Bank Logic for RK3568/RK3588

[V2 PATCH 0/2] Update RAM Bank Logic for RK3568/RK3588

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Use the ATAG info provided by the Rockchip binary TPL to identify
RAM banks on the RK3568 and RK3588 when using the ROCKCHIP_TPL binary.

This is needed because there are specific addresses that should not
be written to for all RK3588 based devices with >=16GB of RAM, writing
to these addresses immediately results in a crash. Additionally on the
RK3568 and RK3588 this allows us to reclaim 256MB of RAM when RAM >=
4GB.

Changes since V1:
 - After additional feedback, removed RFC tag.
 - Made code work for both RK3568 and RK3588.
 - Removed memory hole code for all RK3588 boards.
 - Updated CONFIG_NR_DRAM_BANKS for 3568 and 3588 boards as it is
   the max number of banks supported by the ATAGS code.

Chris Morgan (2):
  rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
  rockchip: Switch RK3568 and RK3588 to new RAM bank logic

 arch/arm/mach-rockchip/sdram.c                | 100 ++++++++++++++++++
 board/friendlyelec/nanopc-t6-rk3588/Makefile  |   6 --
 .../nanopc-t6-rk3588/nanopc-t6-rk3588.c       |  39 -------
 board/pine64/quartzpro64-rk3588/Makefile      |   3 -
 .../quartzpro64-rk3588/quartzpro64-rk3588.c   |  39 -------
 board/radxa/rock5a-rk3588s/Makefile           |   6 --
 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c   |  39 -------
 board/radxa/rock5b-rk3588/Makefile            |   6 --
 board/radxa/rock5b-rk3588/rock5b-rk3588.c     |  39 -------
 board/rockchip/evb_rk3588/Makefile            |   6 --
 board/rockchip/evb_rk3588/evb-rk3588.c        |  39 -------
 board/turing/turing-rk1-rk3588/Makefile       |   6 --
 .../turing-rk1-rk3588/turing-rk1-rk3588.c     |  39 -------
 configs/anbernic-rgxx3-rk3566_defconfig       |   2 +-
 configs/bpi-r2-pro-rk3568_defconfig           |   2 +-
 configs/evb-rk3568_defconfig                  |   2 +-
 configs/evb-rk3588_defconfig                  |   3 +-
 configs/generic-rk3568_defconfig              |   2 +-
 configs/lubancat-2-rk3568_defconfig           |   2 +-
 configs/nanopc-t6-rk3588_defconfig            |   3 +-
 configs/nanopi-r5c-rk3568_defconfig           |   2 +-
 configs/nanopi-r5s-rk3568_defconfig           |   2 +-
 configs/neu6a-io-rk3588_defconfig             |   2 +-
 configs/neu6b-io-rk3588_defconfig             |   2 +-
 configs/odroid-m1-rk3568_defconfig            |   2 +-
 configs/orangepi-5-plus-rk3588_defconfig      |   3 +-
 configs/orangepi-5-rk3588s_defconfig          |   3 +-
 configs/quartz64-a-rk3566_defconfig           |   2 +-
 configs/quartz64-b-rk3566_defconfig           |   2 +-
 configs/quartzpro64-rk3588_defconfig          |   3 +-
 configs/radxa-cm3-io-rk3566_defconfig         |   2 +-
 configs/radxa-e25-rk3568_defconfig            |   2 +-
 configs/rock-3a-rk3568_defconfig              |   2 +-
 configs/rock5a-rk3588s_defconfig              |   3 +-
 configs/rock5b-rk3588_defconfig               |   3 +-
 configs/soquartz-blade-rk3566_defconfig       |   2 +-
 configs/soquartz-cm4-rk3566_defconfig         |   2 +-
 configs/soquartz-model-a-rk3566_defconfig     |   2 +-
 configs/turing-rk1-rk3588_defconfig           |   3 +-
 39 files changed, 126 insertions(+), 301 deletions(-)
 delete mode 100644 board/friendlyelec/nanopc-t6-rk3588/Makefile
 delete mode 100644 board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
 delete mode 100644 board/pine64/quartzpro64-rk3588/Makefile
 delete mode 100644 board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
 delete mode 100644 board/radxa/rock5a-rk3588s/Makefile
 delete mode 100644 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
 delete mode 100644 board/radxa/rock5b-rk3588/Makefile
 delete mode 100644 board/radxa/rock5b-rk3588/rock5b-rk3588.c
 delete mode 100644 board/rockchip/evb_rk3588/Makefile
 delete mode 100644 board/rockchip/evb_rk3588/evb-rk3588.c
 delete mode 100644 board/turing/turing-rk1-rk3588/Makefile
 delete mode 100644 board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c

-- 
2.34.1

[V1 PATCH 1/2] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
>= 16GB of RAM. In the event that neither SOC is used and the
ROCKCHIP_TPL stage is not used, fall back to existing logic.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 arch/arm/mach-rockchip/sdram.c | 100 +++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f..e02fb03c5f 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <asm/arch-rockchip/sdram.h>
 #include <dm/uclass-internal.h>
+#include <linux/errno.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -35,11 +36,110 @@ struct tos_parameter_t {
 	s64 reserve[8];
 };
 
+/* Tag magic */
+#define ATAGS_CORE_MAGIC	0x54410001
+#define ATAGS_DDR_MEM_MAGIC	0x54410052
+
+/* Tag size and offset */
+#define ATAGS_SIZE		SZ_8K
+#define ATAGS_OFFSET		(SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE		(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+
+/* ATAGS memory structure. */
+struct tag_ddr_mem {
+	u32 count;
+	u32 version;
+	u64 bank[20];
+	u32 flags;
+	u32 data[2];
+	u32 hash;
+} __packed;
+
+/**
+ * rockchip_dram_init_banksize() - Get RAM banks from Rockchip TPL
+ *
+ * Iterate through the defined ATAGS memory location to first find a
+ * valid core header, then find a valid ddr_info header. Sanity check
+ * the number of banks found. Then, iterate through the data to add
+ * each individual memory bank. Perform fixups on memory banks that
+ * overlap with a reserved space. If an error condition is received,
+ * it is expected that memory bank setup will fall back on existing
+ * logic. If ROCKCHIP_EXTERNAL_TPL is false then immediately return,
+ * and if neither ROCKCHIP_RK3588 or ROCKCHIP_RK3568 is enabled
+ * immediately return.
+ *
+ * Return number of banks found on success or negative on error.
+ */
+__weak int rockchip_dram_init_banksize(void)
+{
+	struct tag_ddr_mem *ddr_info;
+	size_t val;
+	size_t addr = ATAGS_PHYS_BASE;
+	int i;
+
+	if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+		return 0;
+	if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
+	    !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+		return 0;
+
+	if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+		return -EPERM;
+
+	while (addr < (ATAGS_PHYS_BASE + ATAGS_SIZE)) {
+		val = readl(addr);
+		if (val == ATAGS_CORE_MAGIC)
+			break;
+		addr += 4;
+	}
+	if (addr >= (ATAGS_PHYS_BASE + ATAGS_SIZE))
+		return -ENODATA;
+
+	while (addr < (ATAGS_PHYS_BASE + ATAGS_SIZE)) {
+		val = readl(addr);
+		if (val == ATAGS_DDR_MEM_MAGIC)
+			break;
+		addr += 4;
+	}
+	if (addr >= (ATAGS_PHYS_BASE + ATAGS_SIZE))
+		return -ENODATA;
+
+	ddr_info = (void *)addr + 4;
+	if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS)
+		return -ENODATA;
+
+	for (i = 0; i < (ddr_info->count); i++) {
+		size_t start_addr = ddr_info->bank[i];
+		size_t size = ddr_info->bank[(i + ddr_info->count)];
+		size_t tmp;
+
+		if (start_addr < SZ_2M) {
+			tmp = SZ_2M - start_addr;
+			start_addr = SZ_2M;
+			size = size - tmp;
+		}
+
+		if (start_addr >= SDRAM_MAX_SIZE && start_addr < SZ_4G)
+			start_addr = SZ_4G;
+
+		tmp = start_addr + size;
+		if (tmp > SDRAM_MAX_SIZE && tmp < SZ_4G)
+			size = SDRAM_MAX_SIZE - start_addr;
+
+		gd->bd->bi_dram[i].start = start_addr;
+		gd->bd->bi_dram[i].size = size;
+	}
+
+	return i;
+}
+
 int dram_init_banksize(void)
 {
 	size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE);
 	size_t top = min((unsigned long)ram_top, (unsigned long)(gd->ram_top));
 
+	if (rockchip_dram_init_banksize() > 0)
+		return 0;
 #ifdef CONFIG_ARM64
 	/* Reserve 0x200000 for ATF bl31 */
 	gd->bd->bi_dram[0].start = 0x200000;
-- 
2.34.1

Re: [V1 PATCH 1/2] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588

[Quentin Schulz]

Hi Chris,

On 4/1/24 20:14, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> Allow RK3568 and RK3588 based boards to get the RAM bank configuration
> from the ROCKCHIP_TPL stage instead of the current logic. This fixes
> both an issue where 256MB of RAM is blocked for devices with >= 4GB
> of RAM and where memory holes need to be defined for devices with
>> = 16GB of RAM. In the event that neither SOC is used and the
> ROCKCHIP_TPL stage is not used, fall back to existing logic.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
>   arch/arm/mach-rockchip/sdram.c | 100 +++++++++++++++++++++++++++++++++
>   1 file changed, 100 insertions(+)
> 
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 0d9a0aef6f..e02fb03c5f 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -12,6 +12,7 @@
>   #include <asm/io.h>
>   #include <asm/arch-rockchip/sdram.h>
>   #include <dm/uclass-internal.h>
> +#include <linux/errno.h>
>   
>   DECLARE_GLOBAL_DATA_PTR;
>   
> @@ -35,11 +36,110 @@ struct tos_parameter_t {
>   	s64 reserve[8];
>   };
>   
> +/* Tag magic */
> +#define ATAGS_CORE_MAGIC	0x54410001
> +#define ATAGS_DDR_MEM_MAGIC	0x54410052
> +
> +/* Tag size and offset */
> +#define ATAGS_SIZE		SZ_8K
> +#define ATAGS_OFFSET		(SZ_2M - ATAGS_SIZE)
> +#define ATAGS_PHYS_BASE		(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
> +
> +/* ATAGS memory structure. */
> +struct tag_ddr_mem {
> +	u32 count;
> +	u32 version;
> +	u64 bank[20];
> +	u32 flags;
> +	u32 data[2];
> +	u32 hash;
> +} __packed;
> +
> +/**
> + * rockchip_dram_init_banksize() - Get RAM banks from Rockchip TPL
> + *
> + * Iterate through the defined ATAGS memory location to first find a
> + * valid core header, then find a valid ddr_info header. Sanity check
> + * the number of banks found. Then, iterate through the data to add
> + * each individual memory bank. Perform fixups on memory banks that
> + * overlap with a reserved space. If an error condition is received,
> + * it is expected that memory bank setup will fall back on existing
> + * logic. If ROCKCHIP_EXTERNAL_TPL is false then immediately return,
> + * and if neither ROCKCHIP_RK3588 or ROCKCHIP_RK3568 is enabled
> + * immediately return.
> + *
> + * Return number of banks found on success or negative on error.
> + */
> +__weak int rockchip_dram_init_banksize(void)
> +{
> +	struct tag_ddr_mem *ddr_info;
> +	size_t val;
> +	size_t addr = ATAGS_PHYS_BASE;

I think this should be phys_addr_t instead of size_t?

size_t is an unsigned long on aarch64 and phys_addr_t is an unsigned 
long long so 4B vs 8B.

This however would likely prevent us from reusing this code on aarch32 
machines, but maybe it's a problem for the people who'll look into 
supporting this :) (also, aarch32 and >= 3.75GiB may be a bit optimistic 
:) ).

> +	int i;
> +

u8 is plenty enough here :)

> +	if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
> +		return 0;
> +	if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
> +	    !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
> +		return 0;
> +
> +	if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
> +		return -EPERM;
> +

I think testing once is enough :)

Also, you probably want to use -ENOTSUPP instead?

> +	while (addr < (ATAGS_PHYS_BASE + ATAGS_SIZE)) {
> +		val = readl(addr);
> +		if (val == ATAGS_CORE_MAGIC)

Save a variable by not saving the result of readl and just check against 
ATAGS_CORE_MAGIC.

> +			break;
> +		addr += 4;

This is an incorrect step size, addr is 4B, so this will result in 16B 
increments, which may be too much. Additionally, we shouldn't read every 
4B as the tag is only ever guaranteed to be 4B aligned, not that we 
would have a tag every 4B. This also means that it's possible somehow 
the content of a tag at a 4B-aligned offset has the CORE_MAGIC for some 
reason, but we shouldn't match on it.

I recommend to follow what Rockchip does downstream:

"""
struct tag_header {
     u32 size; /* size in units of 4B */
     u32 magic;
};
"""

if magic != CORE_MAGIC, then we should increment addr by size * 4B and 
check again.

> +	}
> +	if (addr >= (ATAGS_PHYS_BASE + ATAGS_SIZE))
> +		return -ENODATA;

I think it'd be nice to have debug messages here and there :)

> +
> +	while (addr < (ATAGS_PHYS_BASE + ATAGS_SIZE)) {
> +		val = readl(addr);
> +		if (val == ATAGS_DDR_MEM_MAGIC)
> +			break;
> +		addr += 4;

Same remarks here.

> +	}
> +	if (addr >= (ATAGS_PHYS_BASE + ATAGS_SIZE))
> +		return -ENODATA;
> +
> +	ddr_info = (void *)addr + 4;

It seems that arithmetic operations on void pointers is illegal in the C 
standard. This also quite obfuscate what you want to do here.

Considering that in this patch you're iterating for each 4B until you 
get the MAGIC, the next 4B are data for that header of that magic.

If you go for the tag_header I suggested above, I would recommend to do 
the following instead:

"""
ddr_info = (u8*)addr + sizeof(addr);
"""

This is a bit more explicit wrt to what's expected, we want to have the 
address of the data right after the tag_header we point to currently. 
(and in-code comments also do not hurt :) ).


> +	if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS)
> +		return -ENODATA;
> +
> +	for (i = 0; i < (ddr_info->count); i++) {
> +		size_t start_addr = ddr_info->bank[i];

This should be phys_addr_t since it represents an address in physical 
memory?

> +		size_t size = ddr_info->bank[(i + ddr_info->count)];
> +		size_t tmp;
> +

Please add a comment here to explain everything about those first 2M :) 
(reserved for TF-A but sometimes the ATAGS don't have it reserved)

> +		if (start_addr < SZ_2M) {
> +			tmp = SZ_2M - start_addr;
> +			start_addr = SZ_2M;
> +			size = size - tmp;
> +		}
> +

Same here, a small comment to explain the check below would be nice.

> +		if (start_addr >= SDRAM_MAX_SIZE && start_addr < SZ_4G)
> +			start_addr = SZ_4G;
> +

Why are we not changing the size here as well?

Same here, a small comment to explain the check below would be nice.

> +		tmp = start_addr + size;
> +		if (tmp > SDRAM_MAX_SIZE && tmp < SZ_4G)
> +			size = SDRAM_MAX_SIZE - start_addr;
> + > +		gd->bd->bi_dram[i].start = start_addr;
> +		gd->bd->bi_dram[i].size = size;
> +	}
> +
> +	return i;
> +}
> +

Cheers,
Quentin

Re: [V1 PATCH 1/2] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588

[Chris Morgan]

On Tue, Apr 02, 2024 at 06:38:59PM +0200, Quentin Schulz wrote:
> Hi Chris,
> 
> On 4/1/24 20:14, Chris Morgan wrote:
> > From: Chris Morgan <macromorgan@hotmail.com>
> > 
> > Allow RK3568 and RK3588 based boards to get the RAM bank configuration
> > from the ROCKCHIP_TPL stage instead of the current logic. This fixes
> > both an issue where 256MB of RAM is blocked for devices with >= 4GB
> > of RAM and where memory holes need to be defined for devices with
> > > = 16GB of RAM. In the event that neither SOC is used and the
> > ROCKCHIP_TPL stage is not used, fall back to existing logic.
> > 
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > ---
> >   arch/arm/mach-rockchip/sdram.c | 100 +++++++++++++++++++++++++++++++++
> >   1 file changed, 100 insertions(+)
> > 
> > diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> > index 0d9a0aef6f..e02fb03c5f 100644
> > --- a/arch/arm/mach-rockchip/sdram.c
> > +++ b/arch/arm/mach-rockchip/sdram.c
> > @@ -12,6 +12,7 @@
> >   #include <asm/io.h>
> >   #include <asm/arch-rockchip/sdram.h>
> >   #include <dm/uclass-internal.h>
> > +#include <linux/errno.h>
> >   DECLARE_GLOBAL_DATA_PTR;
> > @@ -35,11 +36,110 @@ struct tos_parameter_t {
> >   	s64 reserve[8];
> >   };
> > +/* Tag magic */
> > +#define ATAGS_CORE_MAGIC	0x54410001
> > +#define ATAGS_DDR_MEM_MAGIC	0x54410052
> > +
> > +/* Tag size and offset */
> > +#define ATAGS_SIZE		SZ_8K
> > +#define ATAGS_OFFSET		(SZ_2M - ATAGS_SIZE)
> > +#define ATAGS_PHYS_BASE		(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
> > +
> > +/* ATAGS memory structure. */
> > +struct tag_ddr_mem {
> > +	u32 count;
> > +	u32 version;
> > +	u64 bank[20];
> > +	u32 flags;
> > +	u32 data[2];
> > +	u32 hash;
> > +} __packed;
> > +
> > +/**
> > + * rockchip_dram_init_banksize() - Get RAM banks from Rockchip TPL
> > + *
> > + * Iterate through the defined ATAGS memory location to first find a
> > + * valid core header, then find a valid ddr_info header. Sanity check
> > + * the number of banks found. Then, iterate through the data to add
> > + * each individual memory bank. Perform fixups on memory banks that
> > + * overlap with a reserved space. If an error condition is received,
> > + * it is expected that memory bank setup will fall back on existing
> > + * logic. If ROCKCHIP_EXTERNAL_TPL is false then immediately return,
> > + * and if neither ROCKCHIP_RK3588 or ROCKCHIP_RK3568 is enabled
> > + * immediately return.
> > + *
> > + * Return number of banks found on success or negative on error.
> > + */
> > +__weak int rockchip_dram_init_banksize(void)
> > +{
> > +	struct tag_ddr_mem *ddr_info;
> > +	size_t val;
> > +	size_t addr = ATAGS_PHYS_BASE;
> 
> I think this should be phys_addr_t instead of size_t?
> 
> size_t is an unsigned long on aarch64 and phys_addr_t is an unsigned long
> long so 4B vs 8B.
> 
> This however would likely prevent us from reusing this code on aarch32
> machines, but maybe it's a problem for the people who'll look into
> supporting this :) (also, aarch32 and >= 3.75GiB may be a bit optimistic :)
> ).

Could I just specify a size and not worry about it? A u32 should be more
than enough to hold the maximum RAM address of an RK3588 board (32GB).
That would allow this to work on both 32 and 64 right? Otherwise I could
further restrict this code to the AARCH64 ifdef.

> 
> > +	int i;
> > +
> 
> u8 is plenty enough here :)

I use it as a return value where there are negative numbers (though
obviously this should never be negative since it's an increment
counter). Does that matter?

> 
> > +	if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
> > +		return 0;
> > +	if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
> > +	    !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
> > +		return 0;
> > +
> > +	if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
> > +		return -EPERM;
> > +
> 
> I think testing once is enough :)
> 
> Also, you probably want to use -ENOTSUPP instead?

Acknowledged.

> 
> > +	while (addr < (ATAGS_PHYS_BASE + ATAGS_SIZE)) {
> > +		val = readl(addr);
> > +		if (val == ATAGS_CORE_MAGIC)
> 
> Save a variable by not saving the result of readl and just check against
> ATAGS_CORE_MAGIC.

Acknowledged.

> 
> > +			break;
> > +		addr += 4;
> 
> This is an incorrect step size, addr is 4B, so this will result in 16B
> increments, which may be too much. Additionally, we shouldn't read every 4B
> as the tag is only ever guaranteed to be 4B aligned, not that we would have
> a tag every 4B. This also means that it's possible somehow the content of a
> tag at a 4B-aligned offset has the CORE_MAGIC for some reason, but we
> shouldn't match on it.
> 

I'm not quite sure I follow. Are you saying I need to increment every
4 * the value of size in the tag_header? The value I show is 0x5 in
my header meaning increment every 0x14?

> I recommend to follow what Rockchip does downstream:
> 
> """
> struct tag_header {
>     u32 size; /* size in units of 4B */
>     u32 magic;
> };
> """
> 
> if magic != CORE_MAGIC, then we should increment addr by size * 4B and check
> again.
> 
> > +	}
> > +	if (addr >= (ATAGS_PHYS_BASE + ATAGS_SIZE))
> > +		return -ENODATA;
> 
> I think it'd be nice to have debug messages here and there :)
> 

Will do.

> > +
> > +	while (addr < (ATAGS_PHYS_BASE + ATAGS_SIZE)) {
> > +		val = readl(addr);
> > +		if (val == ATAGS_DDR_MEM_MAGIC)
> > +			break;
> > +		addr += 4;
> 
> Same remarks here.
> 
> > +	}
> > +	if (addr >= (ATAGS_PHYS_BASE + ATAGS_SIZE))
> > +		return -ENODATA;
> > +
> > +	ddr_info = (void *)addr + 4;
> 
> It seems that arithmetic operations on void pointers is illegal in the C
> standard. This also quite obfuscate what you want to do here.
> 
> Considering that in this patch you're iterating for each 4B until you get
> the MAGIC, the next 4B are data for that header of that magic.
> 
> If you go for the tag_header I suggested above, I would recommend to do the
> following instead:
> 
> """
> ddr_info = (u8*)addr + sizeof(addr);
> """
> 
> This is a bit more explicit wrt to what's expected, we want to have the
> address of the data right after the tag_header we point to currently. (and
> in-code comments also do not hurt :) ).
> 

Should I use a (u8*) though? While that works for now, if the ATAGS get
put at a higher offset wouldn't something like a u32 make more sense?

> 
> > +	if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS)
> > +		return -ENODATA;
> > +
> > +	for (i = 0; i < (ddr_info->count); i++) {
> > +		size_t start_addr = ddr_info->bank[i];
> 
> This should be phys_addr_t since it represents an address in physical
> memory?

Most likely, yes.

> 
> > +		size_t size = ddr_info->bank[(i + ddr_info->count)];
> > +		size_t tmp;
> > +
> 
> Please add a comment here to explain everything about those first 2M :)
> (reserved for TF-A but sometimes the ATAGS don't have it reserved)
> 

Will do. My original code had comments inline, but I replaced it with
a function description at the top. I think I'll try to do a simple
description at the top with inline comments in the next version.

> > +		if (start_addr < SZ_2M) {
> > +			tmp = SZ_2M - start_addr;
> > +			start_addr = SZ_2M;
> > +			size = size - tmp;
> > +		}
> > +
> 
> Same here, a small comment to explain the check below would be nice.
> 
> > +		if (start_addr >= SDRAM_MAX_SIZE && start_addr < SZ_4G)
> > +			start_addr = SZ_4G;
> > +
> 
> Why are we not changing the size here as well?

Mistake on my part, will correct. Thank you.

> 
> Same here, a small comment to explain the check below would be nice.
> 
> > +		tmp = start_addr + size;
> > +		if (tmp > SDRAM_MAX_SIZE && tmp < SZ_4G)
> > +			size = SDRAM_MAX_SIZE - start_addr;
> > + > +		gd->bd->bi_dram[i].start = start_addr;
> > +		gd->bd->bi_dram[i].size = size;
> > +	}
> > +
> > +	return i;
> > +}
> > +
> 
> Cheers,
> Quentin

Thank you for your feedback. I'll work on all this and resubmit within
a few days.

Chris

Re: [V1 PATCH 1/2] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588

[Quentin Schulz]

Hi Chris,

On 4/4/24 23:33, Chris Morgan wrote:
> On Tue, Apr 02, 2024 at 06:38:59PM +0200, Quentin Schulz wrote:
>> Hi Chris,
>>
>> On 4/1/24 20:14, Chris Morgan wrote:
>>> From: Chris Morgan <macromorgan@hotmail.com>
>>>
>>> Allow RK3568 and RK3588 based boards to get the RAM bank configuration
>>> from the ROCKCHIP_TPL stage instead of the current logic. This fixes
>>> both an issue where 256MB of RAM is blocked for devices with >= 4GB
>>> of RAM and where memory holes need to be defined for devices with
>>>> = 16GB of RAM. In the event that neither SOC is used and the
>>> ROCKCHIP_TPL stage is not used, fall back to existing logic.
>>>
>>> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
>>> ---
>>>    arch/arm/mach-rockchip/sdram.c | 100 +++++++++++++++++++++++++++++++++
>>>    1 file changed, 100 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
>>> index 0d9a0aef6f..e02fb03c5f 100644
>>> --- a/arch/arm/mach-rockchip/sdram.c
>>> +++ b/arch/arm/mach-rockchip/sdram.c
>>> @@ -12,6 +12,7 @@
>>>    #include <asm/io.h>
>>>    #include <asm/arch-rockchip/sdram.h>
>>>    #include <dm/uclass-internal.h>
>>> +#include <linux/errno.h>
>>>    DECLARE_GLOBAL_DATA_PTR;
>>> @@ -35,11 +36,110 @@ struct tos_parameter_t {
>>>    	s64 reserve[8];
>>>    };
>>> +/* Tag magic */
>>> +#define ATAGS_CORE_MAGIC	0x54410001
>>> +#define ATAGS_DDR_MEM_MAGIC	0x54410052
>>> +
>>> +/* Tag size and offset */
>>> +#define ATAGS_SIZE		SZ_8K
>>> +#define ATAGS_OFFSET		(SZ_2M - ATAGS_SIZE)
>>> +#define ATAGS_PHYS_BASE		(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
>>> +
>>> +/* ATAGS memory structure. */
>>> +struct tag_ddr_mem {
>>> +	u32 count;
>>> +	u32 version;
>>> +	u64 bank[20];
>>> +	u32 flags;
>>> +	u32 data[2];
>>> +	u32 hash;
>>> +} __packed;
>>> +
>>> +/**
>>> + * rockchip_dram_init_banksize() - Get RAM banks from Rockchip TPL
>>> + *
>>> + * Iterate through the defined ATAGS memory location to first find a
>>> + * valid core header, then find a valid ddr_info header. Sanity check
>>> + * the number of banks found. Then, iterate through the data to add
>>> + * each individual memory bank. Perform fixups on memory banks that
>>> + * overlap with a reserved space. If an error condition is received,
>>> + * it is expected that memory bank setup will fall back on existing
>>> + * logic. If ROCKCHIP_EXTERNAL_TPL is false then immediately return,
>>> + * and if neither ROCKCHIP_RK3588 or ROCKCHIP_RK3568 is enabled
>>> + * immediately return.
>>> + *
>>> + * Return number of banks found on success or negative on error.
>>> + */
>>> +__weak int rockchip_dram_init_banksize(void)
>>> +{
>>> +	struct tag_ddr_mem *ddr_info;
>>> +	size_t val;
>>> +	size_t addr = ATAGS_PHYS_BASE;
>>
>> I think this should be phys_addr_t instead of size_t?
>>
>> size_t is an unsigned long on aarch64 and phys_addr_t is an unsigned long
>> long so 4B vs 8B.
>>
>> This however would likely prevent us from reusing this code on aarch32
>> machines, but maybe it's a problem for the people who'll look into
>> supporting this :) (also, aarch32 and >= 3.75GiB may be a bit optimistic :)
>> ).
> 
> Could I just specify a size and not worry about it? A u32 should be more
> than enough to hold the maximum RAM address of an RK3588 board (32GB).
> That would allow this to work on both 32 and 64 right? Otherwise I could
> further restrict this code to the AARCH64 ifdef.
> 

There's even a bigger issue here as phys_t is an 8B structure (on 
Aarch64) while the atags are actually 4B aligned, so that would 
unnecessarily increase the complexity for arithmetic on those addresses. 
So u32 would probably be fine then.

>>
>>> +	int i;
>>> +
>>
>> u8 is plenty enough here :)
> 
> I use it as a return value where there are negative numbers (though
> obviously this should never be negative since it's an increment
> counter). Does that matter?
> 

You could return i still and let the compiler do the conversion.

No, it's not a blocker, but that may unnecessarily increase the size of 
the TPL.

[...]

>>> +			break;
>>> +		addr += 4;
>>
>> This is an incorrect step size, addr is 4B, so this will result in 16B
>> increments, which may be too much. Additionally, we shouldn't read every 4B
>> as the tag is only ever guaranteed to be 4B aligned, not that we would have
>> a tag every 4B. This also means that it's possible somehow the content of a
>> tag at a 4B-aligned offset has the CORE_MAGIC for some reason, but we
>> shouldn't match on it.
>>
> 
> I'm not quite sure I follow. Are you saying I need to increment every
> 4 * the value of size in the tag_header? The value I show is 0x5 in
> my header meaning increment every 0x14?
> 

What we have in memory is (each 4B) (correct me if I misread Rockchip's 
code)

tag1.size = 6
tag1.magic
data1[0]
data1[1]
data1[2]
data1[3]
tag2.size = 4
tag2.magic
data2[0]
data2[1]

...

You start with addr = &tag1.size
when you do addr +4, you now have addr= &data1[2]

By casting data1[2] into a tag struct, you would have

tagX.size = data1[2]
tagX.magic = data1[3]

If somehow data1[3] matches the magic, you'll detect tag data as a tag 
header, and that's no good. Also, you may be missing a tag by checking 
every 16B, which isn't guaranteed by Rockchip's ATAGS (only guaranteed 
to be 4B aligned)

tag1.size is the size of the tag1 in multiples of 4B (u32), so the 
header + data.

That's what I got from

"""
#define tag_next(t)     ((struct tag *)((u32 *)(t) + (t)->hdr.size))
"""

because of pointer arithmetic there.

[...]

>>> +	}
>>> +	if (addr >= (ATAGS_PHYS_BASE + ATAGS_SIZE))
>>> +		return -ENODATA;
>>> +
>>> +	ddr_info = (void *)addr + 4;
>>
>> It seems that arithmetic operations on void pointers is illegal in the C
>> standard. This also quite obfuscate what you want to do here.
>>
>> Considering that in this patch you're iterating for each 4B until you get
>> the MAGIC, the next 4B are data for that header of that magic.
>>
>> If you go for the tag_header I suggested above, I would recommend to do the
>> following instead:
>>
>> """
>> ddr_info = (u8*)addr + sizeof(addr);
>> """
>>
>> This is a bit more explicit wrt to what's expected, we want to have the
>> address of the data right after the tag_header we point to currently. (and
>> in-code comments also do not hurt :) ).
>>
> 
> Should I use a (u8*) though? While that works for now, if the ATAGS get
> put at a higher offset wouldn't something like a u32 make more sense?
> 

That's a good point, but because of pointer arithmetic you cannot simply 
have

"""
ddr_info = (u32*)addr + sizeof(addr);
"""

Because that would make ddr_info 4* 4B (sizeof(addr) * u32 pointer 
arithmetic).

What you could do is:

"""
bool core_found = false;
u32* addr = (void *)ATAGS_PHYS_BASE;
struct tag_header *tag = addr;

while (addr < (ATAGS_PHYS_BASE + ATAGS_SIZE)) {
	val = tag->magic;
	if (!core_found) {
         	if (val == ATAGS_CORE_MAGIC)
			core_found = true;
         } else if (val == ATAGS_DDR_MEM_MAGIC) {
		break;
	}

	addr += tag->size;
         tag = addr;
}

if (addr >= (ATAGS_PHYS_BASE + ATAGS_SIZE))
	return -ENODATA;

ddr_info = addr + sizeof(tag) / sizeof(u32);
if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS)
	return -ENODATA;
"""

(NOT COMPILED/TESTED)

Cheers,
Quentin

[V2 PATCH 2/2] rockchip: Switch RK3568 and RK3588 to new RAM bank logic

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Switch all RK3568 and RK3588 boards to use the ATAGS based RAM bank
logic. This allows us to access all RAM when >= 4GB of RAM is available
while also automatically creating the memory holes when >= 16GB of RAM
is available.

Remove the board specific logic that previously created the memory
holes, and update the CONFIG_NR_DRAM_BANKS to 10 which is the maximum
supported number of banks using the ATAGS method. Only the number of
banks found by the RAM init code will get added.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 board/friendlyelec/nanopc-t6-rk3588/Makefile  |  6 ---
 .../nanopc-t6-rk3588/nanopc-t6-rk3588.c       | 39 -------------------
 board/pine64/quartzpro64-rk3588/Makefile      |  3 --
 .../quartzpro64-rk3588/quartzpro64-rk3588.c   | 39 -------------------
 board/radxa/rock5a-rk3588s/Makefile           |  6 ---
 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c   | 39 -------------------
 board/radxa/rock5b-rk3588/Makefile            |  6 ---
 board/radxa/rock5b-rk3588/rock5b-rk3588.c     | 39 -------------------
 board/rockchip/evb_rk3588/Makefile            |  6 ---
 board/rockchip/evb_rk3588/evb-rk3588.c        | 39 -------------------
 board/turing/turing-rk1-rk3588/Makefile       |  6 ---
 .../turing-rk1-rk3588/turing-rk1-rk3588.c     | 39 -------------------
 configs/anbernic-rgxx3-rk3566_defconfig       |  2 +-
 configs/bpi-r2-pro-rk3568_defconfig           |  2 +-
 configs/evb-rk3568_defconfig                  |  2 +-
 configs/evb-rk3588_defconfig                  |  3 +-
 configs/generic-rk3568_defconfig              |  2 +-
 configs/lubancat-2-rk3568_defconfig           |  2 +-
 configs/nanopc-t6-rk3588_defconfig            |  3 +-
 configs/nanopi-r5c-rk3568_defconfig           |  2 +-
 configs/nanopi-r5s-rk3568_defconfig           |  2 +-
 configs/neu6a-io-rk3588_defconfig             |  2 +-
 configs/neu6b-io-rk3588_defconfig             |  2 +-
 configs/odroid-m1-rk3568_defconfig            |  2 +-
 configs/orangepi-5-plus-rk3588_defconfig      |  3 +-
 configs/orangepi-5-rk3588s_defconfig          |  3 +-
 configs/quartz64-a-rk3566_defconfig           |  2 +-
 configs/quartz64-b-rk3566_defconfig           |  2 +-
 configs/quartzpro64-rk3588_defconfig          |  3 +-
 configs/radxa-cm3-io-rk3566_defconfig         |  2 +-
 configs/radxa-e25-rk3568_defconfig            |  2 +-
 configs/rock-3a-rk3568_defconfig              |  2 +-
 configs/rock5a-rk3588s_defconfig              |  3 +-
 configs/rock5b-rk3588_defconfig               |  3 +-
 configs/soquartz-blade-rk3566_defconfig       |  2 +-
 configs/soquartz-cm4-rk3566_defconfig         |  2 +-
 configs/soquartz-model-a-rk3566_defconfig     |  2 +-
 configs/turing-rk1-rk3588_defconfig           |  3 +-
 38 files changed, 26 insertions(+), 301 deletions(-)
 delete mode 100644 board/friendlyelec/nanopc-t6-rk3588/Makefile
 delete mode 100644 board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
 delete mode 100644 board/pine64/quartzpro64-rk3588/Makefile
 delete mode 100644 board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
 delete mode 100644 board/radxa/rock5a-rk3588s/Makefile
 delete mode 100644 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
 delete mode 100644 board/radxa/rock5b-rk3588/Makefile
 delete mode 100644 board/radxa/rock5b-rk3588/rock5b-rk3588.c
 delete mode 100644 board/rockchip/evb_rk3588/Makefile
 delete mode 100644 board/rockchip/evb_rk3588/evb-rk3588.c
 delete mode 100644 board/turing/turing-rk1-rk3588/Makefile
 delete mode 100644 board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c

diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile b/board/friendlyelec/nanopc-t6-rk3588/Makefile
deleted file mode 100644
index c1c49b1970..0000000000
--- a/board/friendlyelec/nanopc-t6-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier:     GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += nanopc-t6-rk3588.o
diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
deleted file mode 100644
index 99bbef964e..0000000000
--- a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int nanopc_t6_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-	struct fdt_memory gap1 = {
-		.start = 0x3fc000000,
-		.end = 0x3fc4fffff,
-	};
-	struct fdt_memory gap2 = {
-		.start = 0x3fff00000,
-		.end = 0x3ffffffff,
-	};
-	unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-	unsigned int ret;
-
-	/*
-	 * Inject the reserved-memory nodes into the DTS
-	 */
-	ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1,  NULL, 0,
-					 NULL, flags);
-	if (ret)
-		return ret;
-
-	return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2,  NULL, 0,
-					  NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	return nanopc_t6_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/pine64/quartzpro64-rk3588/Makefile b/board/pine64/quartzpro64-rk3588/Makefile
deleted file mode 100644
index 47819d9be9..0000000000
--- a/board/pine64/quartzpro64-rk3588/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier:     GPL-2.0+
-
-obj-y += quartzpro64-rk3588.o
diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
deleted file mode 100644
index bda804a89e..0000000000
--- a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2023 Google, Inc
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-	struct fdt_memory gap1 = {
-		.start = 0x3fc000000,
-		.end = 0x3fc4fffff,
-	};
-	struct fdt_memory gap2 = {
-		.start = 0x3fff00000,
-		.end = 0x3ffffffff,
-	};
-	unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-	unsigned int ret;
-
-	/*
-	 * Inject the reserved-memory nodes into the DTS
-	 */
-	ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1,  NULL, 0,
-					 NULL, flags);
-	if (ret)
-		return ret;
-
-	return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2,  NULL, 0,
-					  NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	return quartzpro64_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/radxa/rock5a-rk3588s/Makefile b/board/radxa/rock5a-rk3588s/Makefile
deleted file mode 100644
index 48dd512455..0000000000
--- a/board/radxa/rock5a-rk3588s/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier:     GPL-2.0+
-#
-# Copyright (c) 2023 Collabora Ltd.
-#
-
-obj-y += rock5a-rk3588s.o
diff --git a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
deleted file mode 100644
index 2d7a8c07dc..0000000000
--- a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5a_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-	struct fdt_memory gap1 = {
-		.start = 0x3fc000000,
-		.end = 0x3fc4fffff,
-	};
-	struct fdt_memory gap2 = {
-		.start = 0x3fff00000,
-		.end = 0x3ffffffff,
-	};
-	unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-	unsigned int ret;
-
-	/*
-	 * Inject the reserved-memory nodes into the DTS
-	 */
-	ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1,  NULL, 0,
-					 NULL, flags);
-	if (ret)
-		return ret;
-
-	return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2,  NULL, 0,
-					  NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	return rock5a_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/radxa/rock5b-rk3588/Makefile b/board/radxa/rock5b-rk3588/Makefile
deleted file mode 100644
index 95d813596d..0000000000
--- a/board/radxa/rock5b-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier:     GPL-2.0+
-#
-# Copyright (c) 2022 Collabora Ltd.
-#
-
-obj-y += rock5b-rk3588.o
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
deleted file mode 100644
index 5c3b52b948..0000000000
--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5b_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-	struct fdt_memory gap1 = {
-		.start = 0x3fc000000,
-		.end = 0x3fc4fffff,
-	};
-	struct fdt_memory gap2 = {
-		.start = 0x3fff00000,
-		.end = 0x3ffffffff,
-	};
-	unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-	unsigned int ret;
-
-	/*
-	 * Inject the reserved-memory nodes into the DTS
-	 */
-	ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1,  NULL, 0,
-					 NULL, flags);
-	if (ret)
-		return ret;
-
-	return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2,  NULL, 0,
-					  NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	return rock5b_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/rockchip/evb_rk3588/Makefile b/board/rockchip/evb_rk3588/Makefile
deleted file mode 100644
index 240d2ec597..0000000000
--- a/board/rockchip/evb_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier:     GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += evb-rk3588.o
diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c b/board/rockchip/evb_rk3588/evb-rk3588.c
deleted file mode 100644
index caf94d8d29..0000000000
--- a/board/rockchip/evb_rk3588/evb-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-	struct fdt_memory gap1 = {
-		.start = 0x3fc000000,
-		.end = 0x3fc4fffff,
-	};
-	struct fdt_memory gap2 = {
-		.start = 0x3fff00000,
-		.end = 0x3ffffffff,
-	};
-	unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-	unsigned int ret;
-
-	/*
-	 * Inject the reserved-memory nodes into the DTS
-	 */
-	ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1,  NULL, 0,
-					 NULL, flags);
-	if (ret)
-		return ret;
-
-	return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2,  NULL, 0,
-					  NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/turing/turing-rk1-rk3588/Makefile b/board/turing/turing-rk1-rk3588/Makefile
deleted file mode 100644
index a979d8023a..0000000000
--- a/board/turing/turing-rk1-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier:     GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += turing-rk1-rk3588.o
diff --git a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c b/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
deleted file mode 100644
index e2338a2a35..0000000000
--- a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int turing_rk1_add_reserved_memory_fdt_nodes(void *new_blob)
-{
-	struct fdt_memory gap1 = {
-		.start = 0x3fc000000,
-		.end = 0x3fc4fffff,
-	};
-	struct fdt_memory gap2 = {
-		.start = 0x3fff00000,
-		.end = 0x3ffffffff,
-	};
-	unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
-	unsigned int ret;
-
-	/*
-	 * Inject the reserved-memory nodes into the DTS
-	 */
-	ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1,  NULL, 0,
-					 NULL, flags);
-	if (ret)
-		return ret;
-
-	return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2,  NULL, 0,
-					  NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	return turing_rk1_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
index ed6643d9d4..c85b4d0128 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3"
diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig
index e6e0e6fc6f..7b7a8e2af3 100644
--- a/configs/bpi-r2-pro-rk3568_defconfig
+++ b/configs/bpi-r2-pro-rk3568_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro"
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index cb9b87ff12..a1bd81ea9f 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 8a6aa91cb2..51e794c78c 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
@@ -24,7 +24,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index 8fb79c9b44..4f3feb3177 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic"
diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig
index 80ae6ec3a2..5589fd769c 100644
--- a/configs/lubancat-2-rk3568_defconfig
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2"
diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig
index 7609932209..cb8f61344a 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -6,7 +6,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_SF_DEFAULT_SPEED=24000000
@@ -31,7 +31,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig
index f5a472d03d..d7cb138547 100644
--- a/configs/nanopi-r5c-rk3568_defconfig
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -6,7 +6,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig
index 99692d341f..60b3b332a3 100644
--- a/configs/nanopi-r5s-rk3568_defconfig
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -6,7 +6,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig
index d5301c630b..5b60747ecd 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig
index b13c9b5db1..09150ee293 100644
--- a/configs/neu6b-io-rk3588_defconfig
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io"
diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig
index 3130e341e7..bc1b49d286 100644
--- a/configs/odroid-m1-rk3568_defconfig
+++ b/configs/odroid-m1-rk3568_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig
index a58f96d577..f743c4077b 100644
--- a/configs/orangepi-5-plus-rk3588_defconfig
+++ b/configs/orangepi-5-plus-rk3588_defconfig
@@ -6,7 +6,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_SF_DEFAULT_SPEED=24000000
@@ -32,7 +32,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-plus.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig
index a9404c912e..fe453e0191 100644
--- a/configs/orangepi-5-rk3588s_defconfig
+++ b/configs/orangepi-5-rk3588s_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_SF_DEFAULT_SPEED=24000000
@@ -31,7 +31,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-orangepi-5.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig
index ade08867f6..d71e69cda3 100644
--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -6,7 +6,7 @@ CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig
index 8d01db5440..2b32e141de 100644
--- a/configs/quartz64-b-rk3566_defconfig
+++ b/configs/quartz64-b-rk3566_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig
index 9cc4eb02e0..6d4f1fa97f 100644
--- a/configs/quartzpro64-rk3588_defconfig
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -6,7 +6,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
@@ -27,7 +27,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
index 4b606dcb8e..fceb88716b 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io"
diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig
index fedb137877..6d97c5b8f6 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -6,7 +6,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25"
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 18372a570e..1ad5bab836 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index efa7bcbdcd..05c96b39ce 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
@@ -24,7 +24,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index a0678ff129..fc3118c807 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -6,7 +6,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_SF_DEFAULT_SPEED=24000000
@@ -32,7 +32,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig
index 9693cc2f9e..8163b9be86 100644
--- a/configs/soquartz-blade-rk3566_defconfig
+++ b/configs/soquartz-blade-rk3566_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade"
diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig
index 9c6b12d230..1ab633a179 100644
--- a/configs/soquartz-cm4-rk3566_defconfig
+++ b/configs/soquartz-cm4-rk3566_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4"
diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig
index fd72d78a47..c08a062ea3 100644
--- a/configs/soquartz-model-a-rk3566_defconfig
+++ b/configs/soquartz-model-a-rk3566_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a"
diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig
index 0f903cf6e8..67b0feea5d 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -6,7 +6,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=10
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
 CONFIG_SF_DEFAULT_SPEED=24000000
@@ -32,7 +32,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-- 
2.34.1

Re: [V2 PATCH 2/2] rockchip: Switch RK3568 and RK3588 to new RAM bank logic

[Quentin Schulz]

Hi Chris,

On 4/1/24 20:14, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> Switch all RK3568 and RK3588 boards to use the ATAGS based RAM bank
> logic. This allows us to access all RAM when >= 4GB of RAM is available
> while also automatically creating the memory holes when >= 16GB of RAM
> is available.
> 
> Remove the board specific logic that previously created the memory
> holes, and update the CONFIG_NR_DRAM_BANKS to 10 which is the maximum
> supported number of banks using the ATAGS method. Only the number of
> banks found by the RAM init code will get added.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>

Could you please rebase on top of next to have all new boards as well? I 
don't see my Jaguar in there and it feels sad being left on the side :( 
You may want to have your Indiedroid Nova patch based on that series as 
well?

Half wondering if we shouldn't have CONFIG_NR_DRAM_BANKS=10 forcibly set 
when ROCKCHIP_EXTERNAL_TPL is used?

> ---
>   board/friendlyelec/nanopc-t6-rk3588/Makefile  |  6 ---
>   .../nanopc-t6-rk3588/nanopc-t6-rk3588.c       | 39 -------------------
>   board/pine64/quartzpro64-rk3588/Makefile      |  3 --
>   .../quartzpro64-rk3588/quartzpro64-rk3588.c   | 39 -------------------
>   board/radxa/rock5a-rk3588s/Makefile           |  6 ---
>   board/radxa/rock5a-rk3588s/rock5a-rk3588s.c   | 39 -------------------
>   board/radxa/rock5b-rk3588/Makefile            |  6 ---
>   board/radxa/rock5b-rk3588/rock5b-rk3588.c     | 39 -------------------
>   board/rockchip/evb_rk3588/Makefile            |  6 ---
>   board/rockchip/evb_rk3588/evb-rk3588.c        | 39 -------------------
>   board/turing/turing-rk1-rk3588/Makefile       |  6 ---
>   .../turing-rk1-rk3588/turing-rk1-rk3588.c     | 39 -------------------
>   configs/anbernic-rgxx3-rk3566_defconfig       |  2 +-
>   configs/bpi-r2-pro-rk3568_defconfig           |  2 +-
>   configs/evb-rk3568_defconfig                  |  2 +-
>   configs/evb-rk3588_defconfig                  |  3 +-
>   configs/generic-rk3568_defconfig              |  2 +-
>   configs/lubancat-2-rk3568_defconfig           |  2 +-
>   configs/nanopc-t6-rk3588_defconfig            |  3 +-
>   configs/nanopi-r5c-rk3568_defconfig           |  2 +-
>   configs/nanopi-r5s-rk3568_defconfig           |  2 +-
>   configs/neu6a-io-rk3588_defconfig             |  2 +-
>   configs/neu6b-io-rk3588_defconfig             |  2 +-
>   configs/odroid-m1-rk3568_defconfig            |  2 +-
>   configs/orangepi-5-plus-rk3588_defconfig      |  3 +-
>   configs/orangepi-5-rk3588s_defconfig          |  3 +-
>   configs/quartz64-a-rk3566_defconfig           |  2 +-
>   configs/quartz64-b-rk3566_defconfig           |  2 +-
>   configs/quartzpro64-rk3588_defconfig          |  3 +-
>   configs/radxa-cm3-io-rk3566_defconfig         |  2 +-
>   configs/radxa-e25-rk3568_defconfig            |  2 +-
>   configs/rock-3a-rk3568_defconfig              |  2 +-
>   configs/rock5a-rk3588s_defconfig              |  3 +-
>   configs/rock5b-rk3588_defconfig               |  3 +-
>   configs/soquartz-blade-rk3566_defconfig       |  2 +-
>   configs/soquartz-cm4-rk3566_defconfig         |  2 +-
>   configs/soquartz-model-a-rk3566_defconfig     |  2 +-
>   configs/turing-rk1-rk3588_defconfig           |  3 +-
>   38 files changed, 26 insertions(+), 301 deletions(-)
>   delete mode 100644 board/friendlyelec/nanopc-t6-rk3588/Makefile
>   delete mode 100644 board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
>   delete mode 100644 board/pine64/quartzpro64-rk3588/Makefile
>   delete mode 100644 board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
>   delete mode 100644 board/radxa/rock5a-rk3588s/Makefile
>   delete mode 100644 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
>   delete mode 100644 board/radxa/rock5b-rk3588/Makefile
>   delete mode 100644 board/radxa/rock5b-rk3588/rock5b-rk3588.c
>   delete mode 100644 board/rockchip/evb_rk3588/Makefile
>   delete mode 100644 board/rockchip/evb_rk3588/evb-rk3588.c
>   delete mode 100644 board/turing/turing-rk1-rk3588/Makefile
>   delete mode 100644 board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
> 
> diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile b/board/friendlyelec/nanopc-t6-rk3588/Makefile
> deleted file mode 100644
> index c1c49b1970..0000000000
> --- a/board/friendlyelec/nanopc-t6-rk3588/Makefile
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# SPDX-License-Identifier:     GPL-2.0+
> -#
> -# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
> -#
> -
> -obj-y += nanopc-t6-rk3588.o
> diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
> deleted file mode 100644
> index 99bbef964e..0000000000
> --- a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
> - */
> -
> -#include <fdtdec.h>
> -#include <fdt_support.h>
> -
> -#ifdef CONFIG_OF_BOARD_SETUP

I think it may now be possible to remove this symbol from the 
appropriate defconfigs? Not sure though.

Cheers,
Quentin