[PATCH v2 2/3] riscv: dts: sophgo: Add ethernet node

[Kongyang Liu <seashell11234455@gmail.com>]

Add ethernet node for cv1800b SoC

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>

---

Changes in v2:
- Change compatible
- Add clocks and interrupt properties.

 arch/riscv/dts/cv1800b-milkv-duo.dts |  7 ++++++-
 arch/riscv/dts/cv18xx.dtsi           | 23 +++++++++++++++++++++++
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts b/arch/riscv/dts/cv1800b-milkv-duo.dts
index 94e64ddce8..c1e6611e33 100644
--- a/arch/riscv/dts/cv1800b-milkv-duo.dts
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -29,6 +29,11 @@
 	};
 };
 
+&ethernet0 {
+	status = "okay";
+	phy-mode = "rmii";
+};
+
 &osc {
 	clock-frequency = <25000000>;
 };
@@ -39,7 +44,7 @@
 	no-1-8-v;
 	no-mmc;
 	no-sdio;
-};
+}
 
 &uart0 {
 	status = "okay";
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index ec99c4deeb..c95bac77be 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -50,6 +50,20 @@
 		clock-frequency = <375000000>;
 		clock-output-names = "sdhci_clk";
 		#clock-cells = <0>;
+	}
+
+	eth_csrclk: eth-csrclk {
+		compatible = "fixed-clock";
+		clock-frequency = <250000000>;
+		clock-output-names = "eth_csrclk";
+		#clock-cells = <0x0>;
+	};
+
+	eth_ptpclk: eth-ptpclk {
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+		clock-output-names = "eth_ptpclk";
+		#clock-cells = <0x0>;
 	};
 
 	soc {
@@ -138,6 +152,15 @@
 			};
 		};
 
+		ethernet0: ethernet@4070000 {
+			compatible = "sophgo,cv1800b-dwmac";
+			reg = <0x04070000 0x10000>;
+			interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&eth_csrclk>, <&eth_ptpclk>;
+			clock-names = "stmmaceth", "ptp_ref";
+			status = "disabled";
+		};
+
 		uart0: serial@4140000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x04140000 0x100>;
-- 
2.41.0