From: Heesub Shin <heesub@gmail.com>
To: u-boot@lists.denx.de
Cc: Heesub Shin <heesub@gmail.com>
Subject: [PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK
Date: Sun, 28 Apr 2024 23:24:02 +0900 [thread overview]
Message-ID: <20240428142406.28445-1-heesub@gmail.com> (raw)
Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to
125, 62.5 and 62.5Mhz in respectively.
Signed-off-by: Heesub Shin <heesub@gmail.com>
---
arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
index b780dbd95e..d07fdcf4bc 100644
--- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
@@ -115,11 +115,11 @@
bootph-all;
};
- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+ /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+ cfg = < 3 124 5 9 9 PQR(1,1,1) >;
bootph-all;
};
};
--
2.34.1
next reply other threads:[~2024-04-28 14:40 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-28 14:24 Heesub Shin [this message]
2024-04-28 14:24 ` [PATCH 2/5] dts: stm32mp157c-odyssey: use internal clock for Tx Heesub Shin
2024-06-06 14:37 ` Patrice CHOTARD
2024-06-14 12:08 ` Patrice CHOTARD
2024-04-28 14:24 ` [PATCH 3/5] dts: stm32mp157c-odyssey: fix incorrect PHY address Heesub Shin
2024-06-06 14:37 ` Patrice CHOTARD
2024-06-14 12:08 ` Patrice CHOTARD
2024-06-14 12:10 ` Patrice CHOTARD
2024-04-28 14:24 ` [PATCH 4/5] net: dwc_eth_qos: add support for phy-reset-gpios property Heesub Shin
2024-06-06 14:38 ` Patrice CHOTARD
2024-06-14 12:08 ` Patrice CHOTARD
2024-04-28 14:24 ` [PATCH 5/5] dts: stm32mp157c-odyssey: add phy-reset-gpios property to ethernet node Heesub Shin
2024-06-06 14:39 ` Patrice CHOTARD
2024-06-14 12:08 ` Patrice CHOTARD
2024-06-06 14:36 ` [PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK Patrice CHOTARD
2024-06-14 12:08 ` Patrice CHOTARD
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