From: Heesub Shin <heesub@gmail.com>
To: u-boot@lists.denx.de
Cc: Heesub Shin <heesub@gmail.com>
Subject: [PATCH 2/5] dts: stm32mp157c-odyssey: use internal clock for Tx
Date: Sun, 28 Apr 2024 23:24:03 +0900 [thread overview]
Message-ID: <20240428142406.28445-2-heesub@gmail.com> (raw)
In-Reply-To: <20240428142406.28445-1-heesub@gmail.com>
In Odyssey board, we should use the internal clock from RCC as the
transmit clock, instead of the external clock from ETH_CLK125 pad. This
commit adds a property, st,eth-clk-sel, so that the ETH_CLK_SEL mux
selects ETH_CLK.
Signed-off-by: Heesub Shin <heesub@gmail.com>
---
arch/arm/dts/stm32mp157c-odyssey.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts
index 17bcf56f74..53ba018197 100644
--- a/arch/arm/dts/stm32mp157c-odyssey.dts
+++ b/arch/arm/dts/stm32mp157c-odyssey.dts
@@ -75,6 +75,7 @@
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
+ st,ext-phyclk;
mdio0 {
#address-cells = <1>;
--
2.34.1
next prev parent reply other threads:[~2024-04-28 14:40 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-28 14:24 [PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK Heesub Shin
2024-04-28 14:24 ` Heesub Shin [this message]
2024-06-06 14:37 ` [PATCH 2/5] dts: stm32mp157c-odyssey: use internal clock for Tx Patrice CHOTARD
2024-06-14 12:08 ` Patrice CHOTARD
2024-04-28 14:24 ` [PATCH 3/5] dts: stm32mp157c-odyssey: fix incorrect PHY address Heesub Shin
2024-06-06 14:37 ` Patrice CHOTARD
2024-06-14 12:08 ` Patrice CHOTARD
2024-06-14 12:10 ` Patrice CHOTARD
2024-04-28 14:24 ` [PATCH 4/5] net: dwc_eth_qos: add support for phy-reset-gpios property Heesub Shin
2024-06-06 14:38 ` Patrice CHOTARD
2024-06-14 12:08 ` Patrice CHOTARD
2024-04-28 14:24 ` [PATCH 5/5] dts: stm32mp157c-odyssey: add phy-reset-gpios property to ethernet node Heesub Shin
2024-06-06 14:39 ` Patrice CHOTARD
2024-06-14 12:08 ` Patrice CHOTARD
2024-06-06 14:36 ` [PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK Patrice CHOTARD
2024-06-14 12:08 ` Patrice CHOTARD
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240428142406.28445-2-heesub@gmail.com \
--to=heesub@gmail.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox