From: Hal Feng <hal.feng@starfivetech.com>
To: Leo Yu-Chi Liang <ycliang@andestech.com>,
Tom Rini <trini@konsulko.com>, Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>, Rick Chen <rick@andestech.com>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Nam Cao <namcao@linutronix.de>, Bo Gan <ganboing@gmail.com>,
Yanhong Wang <yanhong.wang@starfivetech.com>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Minda Chen <minda.chen@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>
Cc: u-boot@lists.denx.de
Subject: [PATCH v1 2/4] dt-bindings: reset: jh7110: Sync with Linux
Date: Mon, 3 Jun 2024 21:27:19 +0800 [thread overview]
Message-ID: <20240603132721.6522-3-hal.feng@starfivetech.com> (raw)
In-Reply-To: <20240603132721.6522-1-hal.feng@starfivetech.com>
Sync JH7110 reset dt-bindings with Linux, which is the same with
dts/upstream/include/dt-bindings/reset/starfive,jh7110-crg.h
except copyright.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../dt-bindings/reset/starfive,jh7110-crg.h | 144 +++++++++++-------
1 file changed, 88 insertions(+), 56 deletions(-)
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
index 1d596581da..771b1aecd0 100644
--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -5,13 +5,13 @@
* Author: Yanhong Wang <yanhong.wang@starfivetech.com>
*/
-#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
-#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
/* SYSCRG resets */
-#define JH7110_SYSRST_JTAG2APB 0
-#define JH7110_SYSRST_SYSCON 1
-#define JH7110_SYSRST_IOMUX_APB 2
+#define JH7110_SYSRST_JTAG_APB 0
+#define JH7110_SYSRST_SYSCON_APB 1
+#define JH7110_SYSRST_IOMUX_APB 2
#define JH7110_SYSRST_BUS 3
#define JH7110_SYSRST_DEBUG 4
#define JH7110_SYSRST_CORE0 5
@@ -29,10 +29,10 @@
#define JH7110_SYSRST_TRACE2 17
#define JH7110_SYSRST_TRACE3 18
#define JH7110_SYSRST_TRACE4 19
-#define JH7110_SYSRST_TRACE_COM 20
+#define JH7110_SYSRST_TRACE_COM 20
#define JH7110_SYSRST_GPU_APB 21
#define JH7110_SYSRST_GPU_DOMA 22
-#define JH7110_SYSRST_NOC_BUS_APB_BUS 23
+#define JH7110_SYSRST_NOC_BUS_APB 23
#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
@@ -43,17 +43,17 @@
#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
-#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33
-#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34
-#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35
-#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36
-#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37
+#define JH7110_SYSRST_AXI_CFG1_AHB 33
+#define JH7110_SYSRST_AXI_CFG1_MAIN 34
+#define JH7110_SYSRST_AXI_CFG0_MAIN 35
+#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36
+#define JH7110_SYSRST_AXI_CFG0_HIFI4 37
#define JH7110_SYSRST_DDR_AXI 38
#define JH7110_SYSRST_DDR_OSC 39
#define JH7110_SYSRST_DDR_APB 40
-#define JH7110_SYSRST_DOM_ISP_TOP_N 41
-#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42
-#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43
+#define JH7110_SYSRST_ISP_TOP 41
+#define JH7110_SYSRST_ISP_TOP_AXI 42
+#define JH7110_SYSRST_VOUT_TOP_SRC 43
#define JH7110_SYSRST_CODAJ12_AXI 44
#define JH7110_SYSRST_CODAJ12_CORE 45
#define JH7110_SYSRST_CODAJ12_APB 46
@@ -61,8 +61,8 @@
#define JH7110_SYSRST_WAVE511_BPU 48
#define JH7110_SYSRST_WAVE511_VCE 49
#define JH7110_SYSRST_WAVE511_APB 50
-#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51
-#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52
+#define JH7110_SYSRST_VDEC_JPG 51
+#define JH7110_SYSRST_VDEC_MAIN 52
#define JH7110_SYSRST_AXIMEM0_AXI 53
#define JH7110_SYSRST_WAVE420L_AXI 54
#define JH7110_SYSRST_WAVE420L_BPU 55
@@ -75,11 +75,11 @@
#define JH7110_SYSRST_QSPI_APB 62
#define JH7110_SYSRST_QSPI_REF 63
-#define JH7110_SYSRST_SDIO0_AHB 64
-#define JH7110_SYSRST_SDIO1_AHB 65
-#define JH7110_SYSRST_GMAC1_AXI 66
-#define JH7110_SYSRST_GMAC1_AHB 67
-#define JH7110_SYSRST_MAILBOX 68
+#define JH7110_SYSRST_SDIO0_AHB 64
+#define JH7110_SYSRST_SDIO1_AHB 65
+#define JH7110_SYSRST_GMAC1_AXI 66
+#define JH7110_SYSRST_GMAC1_AHB 67
+#define JH7110_SYSRST_MAILBOX_APB 68
#define JH7110_SYSRST_SPI0_APB 69
#define JH7110_SYSRST_SPI1_APB 70
#define JH7110_SYSRST_SPI2_APB 71
@@ -94,24 +94,24 @@
#define JH7110_SYSRST_I2C4_APB 80
#define JH7110_SYSRST_I2C5_APB 81
#define JH7110_SYSRST_I2C6_APB 82
-#define JH7110_SYSRST_UART0_APB 83
+#define JH7110_SYSRST_UART0_APB 83
#define JH7110_SYSRST_UART0_CORE 84
-#define JH7110_SYSRST_UART1_APB 85
+#define JH7110_SYSRST_UART1_APB 85
#define JH7110_SYSRST_UART1_CORE 86
-#define JH7110_SYSRST_UART2_APB 87
+#define JH7110_SYSRST_UART2_APB 87
#define JH7110_SYSRST_UART2_CORE 88
-#define JH7110_SYSRST_UART3_APB 89
+#define JH7110_SYSRST_UART3_APB 89
#define JH7110_SYSRST_UART3_CORE 90
-#define JH7110_SYSRST_UART4_APB 91
+#define JH7110_SYSRST_UART4_APB 91
#define JH7110_SYSRST_UART4_CORE 92
-#define JH7110_SYSRST_UART5_APB 93
+#define JH7110_SYSRST_UART5_APB 93
#define JH7110_SYSRST_UART5_CORE 94
-#define JH7110_SYSRST_SPDIF_APB 95
+#define JH7110_SYSRST_SPDIF_APB 95
#define JH7110_SYSRST_PWMDAC_APB 96
#define JH7110_SYSRST_PDM_DMIC 97
#define JH7110_SYSRST_PDM_APB 98
-#define JH7110_SYSRST_I2SRX_APB 99
+#define JH7110_SYSRST_I2SRX_APB 99
#define JH7110_SYSRST_I2SRX_BCLK 100
#define JH7110_SYSRST_I2STX0_APB 101
#define JH7110_SYSRST_I2STX0_BCLK 102
@@ -124,26 +124,26 @@
#define JH7110_SYSRST_WDT_APB 109
#define JH7110_SYSRST_WDT_CORE 110
#define JH7110_SYSRST_CAN0_APB 111
-#define JH7110_SYSRST_CAN0_CORE 112
+#define JH7110_SYSRST_CAN0_CORE 112
#define JH7110_SYSRST_CAN0_TIMER 113
#define JH7110_SYSRST_CAN1_APB 114
-#define JH7110_SYSRST_CAN1_CORE 115
+#define JH7110_SYSRST_CAN1_CORE 115
#define JH7110_SYSRST_CAN1_TIMER 116
-#define JH7110_SYSRST_TIMER_APB 117
+#define JH7110_SYSRST_TIMER_APB 117
#define JH7110_SYSRST_TIMER0 118
#define JH7110_SYSRST_TIMER1 119
#define JH7110_SYSRST_TIMER2 120
#define JH7110_SYSRST_TIMER3 121
#define JH7110_SYSRST_INT_CTRL_APB 122
#define JH7110_SYSRST_TEMP_APB 123
-#define JH7110_SYSRST_TEMP_CORE 124
+#define JH7110_SYSRST_TEMP_CORE 124
#define JH7110_SYSRST_JTAG_CERTIFICATION 125
#define JH7110_SYSRST_END 126
/* AONCRG resets */
-#define JH7110_AONRST_GMAC0_AXI 0
-#define JH7110_AONRST_GMAC0_AHB 1
+#define JH7110_AONRST_GMAC0_AXI 0
+#define JH7110_AONRST_GMAC0_AHB 1
#define JH7110_AONRST_IOMUX 2
#define JH7110_AONRST_PMU_APB 3
#define JH7110_AONRST_PMU_WKUP 4
@@ -154,30 +154,62 @@
#define JH7110_AONRST_END 8
/* STGCRG resets */
-#define JH7110_STGRST_SYSCON_PRESETN 0
+#define JH7110_STGRST_SYSCON 0
#define JH7110_STGRST_HIFI4_CORE 1
-#define JH7110_STGRST_HIFI4_AXI 2
-#define JH7110_STGRST_SEC_TOP_HRESETN 3
+#define JH7110_STGRST_HIFI4_AXI 2
+#define JH7110_STGRST_SEC_AHB 3
#define JH7110_STGRST_E24_CORE 4
-#define JH7110_STGRST_DMA1P_AXI 5
-#define JH7110_STGRST_DMA1P_AHB 6
-#define JH7110_STGRST_USB_AXI 7
-#define JH7110_STGRST_USB_APB 8
-#define JH7110_STGRST_USB_UTMI_APB 9
-#define JH7110_STGRST_USB_PWRUP 10
-#define JH7110_STGRST_PCIE0_MST0 11
-#define JH7110_STGRST_PCIE0_SLV0 12
-#define JH7110_STGRST_PCIE0_SLV 13
-#define JH7110_STGRST_PCIE0_BRG 14
+#define JH7110_STGRST_DMA1P_AXI 5
+#define JH7110_STGRST_DMA1P_AHB 6
+#define JH7110_STGRST_USB0_AXI 7
+#define JH7110_STGRST_USB0_APB 8
+#define JH7110_STGRST_USB0_UTMI_APB 9
+#define JH7110_STGRST_USB0_PWRUP 10
+#define JH7110_STGRST_PCIE0_AXI_MST0 11
+#define JH7110_STGRST_PCIE0_AXI_SLV0 12
+#define JH7110_STGRST_PCIE0_AXI_SLV 13
+#define JH7110_STGRST_PCIE0_BRG 14
#define JH7110_STGRST_PCIE0_CORE 15
-#define JH7110_STGRST_PCIE0_APB 16
-#define JH7110_STGRST_PCIE1_MST0 17
-#define JH7110_STGRST_PCIE1_SLV0 18
-#define JH7110_STGRST_PCIE1_SLV 19
-#define JH7110_STGRST_PCIE1_BRG 20
+#define JH7110_STGRST_PCIE0_APB 16
+#define JH7110_STGRST_PCIE1_AXI_MST0 17
+#define JH7110_STGRST_PCIE1_AXI_SLV0 18
+#define JH7110_STGRST_PCIE1_AXI_SLV 19
+#define JH7110_STGRST_PCIE1_BRG 20
#define JH7110_STGRST_PCIE1_CORE 21
-#define JH7110_STGRST_PCIE1_APB 22
+#define JH7110_STGRST_PCIE1_APB 22
#define JH7110_STGRST_END 23
-#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
+/* ISPCRG resets */
+#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0
+#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1
+#define JH7110_ISPRST_M31DPHY_HW 2
+#define JH7110_ISPRST_M31DPHY_B09_AON 3
+#define JH7110_ISPRST_VIN_APB 4
+#define JH7110_ISPRST_VIN_PIXEL_IF0 5
+#define JH7110_ISPRST_VIN_PIXEL_IF1 6
+#define JH7110_ISPRST_VIN_PIXEL_IF2 7
+#define JH7110_ISPRST_VIN_PIXEL_IF3 8
+#define JH7110_ISPRST_VIN_SYS 9
+#define JH7110_ISPRST_VIN_P_AXI_RD 10
+#define JH7110_ISPRST_VIN_P_AXI_WR 11
+
+#define JH7110_ISPRST_END 12
+
+/* VOUTCRG resets */
+#define JH7110_VOUTRST_DC8200_AXI 0
+#define JH7110_VOUTRST_DC8200_AHB 1
+#define JH7110_VOUTRST_DC8200_CORE 2
+#define JH7110_VOUTRST_DSITX_DPI 3
+#define JH7110_VOUTRST_DSITX_APB 4
+#define JH7110_VOUTRST_DSITX_RXESC 5
+#define JH7110_VOUTRST_DSITX_SYS 6
+#define JH7110_VOUTRST_DSITX_TXBYTEHS 7
+#define JH7110_VOUTRST_DSITX_TXESC 8
+#define JH7110_VOUTRST_HDMI_TX_HDMI 9
+#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10
+#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11
+
+#define JH7110_VOUTRST_END 12
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
--
2.43.2
next prev parent reply other threads:[~2024-06-03 13:57 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-03 13:27 [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux Hal Feng
2024-06-03 13:27 ` [PATCH v1 1/4] dt-bindings: clock: jh7110: Sync " Hal Feng
2024-06-03 13:27 ` Hal Feng [this message]
2024-06-03 13:27 ` [PATCH v1 3/4] clk: starfive: jh7110: Sync clock definitions " Hal Feng
2024-06-03 13:27 ` [PATCH v1 4/4] riscv: dts: jh7110: Sync clock and reset " Hal Feng
2024-06-03 20:32 ` [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings " E Shattow
2024-06-05 1:56 ` Hal Feng
2024-06-05 14:35 ` Tom Rini
2024-06-05 15:37 ` Conor Dooley
2024-07-04 9:31 ` Hal Feng
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