* [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM
@ 2024-08-03 8:32 Christian Marangi
2024-08-03 8:32 ` [PATCH 01/13] clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL Christian Marangi
` (13 more replies)
0 siblings, 14 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
Christian Marangi (13):
clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL
clk: mediatek: mt7988: rename TOP_DA_SELM_XTAL_SEL to TOP_DA_SEL
clk: mediatek: mt7988: rename TOP_CK_NPU_SEL_CM_TOPS_SEL to
TOP_NPU_SEL
clk: mediatek: mt7988: move INFRA_PCIE_PERI_26M_CK_Px clock at top
clk: mediatek: mt7988: fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2
clk: mediatek: mt7988: drop 1/1 infracfg spurious factor
clk: mediatek: mt7988: rename TOPCKGEN factor clock to upstream naming
clk: mediatek: mt7988: reorder TOPCKGEN factor ID
clk: mediatek: mt7988: drop 1/1 spurious factor for topckgen
clk: mediatek: mt7988: comment out infracfg clk not defined
clk: mediatek: mt7988: replace clock ID with upstream linux
clk: mediatek: mt7988: convert to unified infracfg gates + muxes
clk: mediatek: mt7988: rename CK to CLK
arch/arm/dts/mt7988.dtsi | 93 +-
drivers/clk/mediatek/clk-mt7988.c | 1085 +++++++++++-------------
include/dt-bindings/clock/mt7988-clk.h | 545 +++++-------
3 files changed, 787 insertions(+), 936 deletions(-)
--
2.45.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 01/13] clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
@ 2024-08-03 8:32 ` Christian Marangi
2024-08-03 8:32 ` [PATCH 02/13] clk: mediatek: mt7988: rename TOP_DA_SELM_XTAL_SEL to TOP_DA_SEL Christian Marangi
` (12 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Upstream kernel linux clock include use TOP_XTAL instead of CB_CKSQ_40M.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm/dts/mt7988.dtsi | 6 +-
drivers/clk/mediatek/clk-mt7988.c | 100 ++++++++++++-------------
include/dt-bindings/clock/mt7988-clk.h | 4 +-
3 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index 5c0c5bcfd6e..2605e60c993 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -265,7 +265,7 @@
clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
<&infracfg_ao CK_INFRA_UART_O0>;
status = "disabled";
};
@@ -277,7 +277,7 @@
clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
<&infracfg_ao CK_INFRA_UART_O1>;
status = "disabled";
};
@@ -289,7 +289,7 @@
clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
<&infracfg_ao CK_INFRA_UART_O2>;
status = "disabled";
};
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 32b04511781..e7ef58c4fb9 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -51,7 +51,7 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
- XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1),
+ XTAL_FACTOR(CK_TOP_XTAL, "xtal", CLK_XTAL, 1, 1),
PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
@@ -92,10 +92,10 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
CK_APMIXED_NETSYSPLL, 1, 1),
PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1,
1),
- TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
- TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL, 1, 2),
+ TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_XTAL, 1,
1250),
- TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_XTAL, 1,
1220),
TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1,
1),
@@ -135,125 +135,125 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
};
/* TOPCKGEN MUX PARENTS */
-static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
+static const int netsys_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET2_D2,
CK_TOP_CB_MM_D2 };
-static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int netsys_500m_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_NET1_D5,
CK_TOP_NET1_D5_D2 };
-static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int netsys_2x_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_NET2_800M,
CK_TOP_CB_MM_720M };
-static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4,
+static const int netsys_gsw_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET1_D4,
CK_TOP_CB_NET1_D5 };
-static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+static const int eth_gmii_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D4 };
static const int netsys_mcu_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
+ CK_TOP_XTAL, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M
};
static const int eip197_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
+ CK_TOP_XTAL, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5
};
-static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int axi_infra_parents[] = { CK_TOP_XTAL,
CK_TOP_NET1_D8_D2 };
-static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
+static const int uart_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D8,
CK_TOP_M_D8_D2 };
-static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2,
+static const int emmc_250m_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D2,
CK_TOP_CB_MM_D4 };
static const int emmc_400m_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
+ CK_TOP_XTAL, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2
};
-static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
+static const int spi_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D2,
CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
-static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
+static const int nfi1x_parents[] = { CK_TOP_XTAL, CK_TOP_CB_MM_D4,
CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
-static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
+static const int spinfi_parents[] = { CK_TOP_XTAL_D2, CK_TOP_XTAL,
CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
-static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
+static const int pwm_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D2,
CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
-static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
+static const int i2c_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D4,
CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
-static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int pcie_mbist_250m_parents[] = { CK_TOP_XTAL,
CK_TOP_NET1_D5_D2 };
-static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int pextp_tl_ck_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8,
CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
-static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int usb_frmcnt_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_MM_D3_D5 };
-static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
+static const int aud_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_196M };
-static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 };
+static const int a1sys_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_D4 };
-static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
+static const int aud_l_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_196M,
CK_TOP_M_D8_D2 };
-static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
+static const int sspxtp_parents[] = { CK_TOP_XTAL_D2, CK_TOP_M_D8_D2 };
-static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int usxgmii_sbus_0_parents[] = { CK_TOP_XTAL,
CK_TOP_NET1_D8_D4 };
-static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M };
+static const int sgm_0_parents[] = { CK_TOP_XTAL, CK_TOP_CB_SGM_325M };
-static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
+static const int sysapb_parents[] = { CK_TOP_XTAL, CK_TOP_M_D3_D2 };
-static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int eth_refck_50m_parents[] = { CK_TOP_XTAL,
CK_TOP_NET2_D4_D4 };
-static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int eth_sys_200m_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_NET2_D4 };
-static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8,
+static const int eth_xgmii_parents[] = { CK_TOP_XTAL_D2, CK_TOP_NET1_D8_D8,
CK_TOP_NET1_D8_D16 };
-static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
+static const int bus_tops_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET1_D5,
CK_TOP_CB_NET2_D2 };
-static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int npu_tops_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_NET2_800M };
-static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
+static const int dramc_md32_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D2,
CK_TOP_CB_WEDMCU_208M };
-static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int da_xtp_glb_p0_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_NET2_D8 };
-static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int mcusys_backup_625m_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_NET1_D4 };
-static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M,
+static const int macsec_parents[] = { CK_TOP_XTAL, CK_TOP_CB_SGM_325M,
CK_TOP_CB_NET1_D8 };
-static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int netsys_tops_400m_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_NET2_D2 };
-static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 };
+static const int eth_mii_parents[] = { CK_TOP_XTAL_D2, CK_TOP_NET2_D4_D8 };
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd) \
@@ -814,7 +814,7 @@ static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
};
static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
- .fdivs_offs = CK_TOP_CB_CKSQ_40M,
+ .fdivs_offs = CK_TOP_XTAL,
.muxes_offs = CK_TOP_NETSYS_SEL,
.fdivs = topckgen_mtk_fixed_factors,
.muxes = topckgen_mtk_muxes,
@@ -991,10 +991,10 @@ static const struct mtk_gate_regs sgmii0_cg_regs = {
}
static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2),
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3),
+ /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
+ GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_XTAL, 2),
+ /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
+ GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_XTAL, 3),
};
static int mt7988_sgmiisys_0_probe(struct udevice *dev)
@@ -1035,10 +1035,10 @@ static const struct mtk_gate_regs sgmii1_cg_regs = {
}
static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2),
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3),
+ /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
+ GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_XTAL, 2),
+ /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
+ GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_XTAL, 3),
};
static int mt7988_sgmiisys_1_probe(struct udevice *dev)
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 5c21bf63119..88a5cf45ccb 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -170,7 +170,7 @@
/* TOPCKGEN */
/* mtk_fixed_factor */
-#define CK_TOP_CB_CKSQ_40M 0 /* Linux CLK ID (74) */
+#define CK_TOP_XTAL 0 /* Linux CLK ID (74) */
#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */
#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */
#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */
@@ -205,7 +205,7 @@
#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */
#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */
#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */
-#define CK_TOP_CKSQ_40M_D2 35 /* Linux CLK ID (109) */
+#define CK_TOP_XTAL_D2 35 /* Linux CLK ID (109) */
#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */
#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */
#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 02/13] clk: mediatek: mt7988: rename TOP_DA_SELM_XTAL_SEL to TOP_DA_SEL
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
2024-08-03 8:32 ` [PATCH 01/13] clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL Christian Marangi
@ 2024-08-03 8:32 ` Christian Marangi
2024-08-03 8:32 ` [PATCH 03/13] clk: mediatek: mt7988: rename TOP_CK_NPU_SEL_CM_TOPS_SEL to TOP_NPU_SEL Christian Marangi
` (11 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Upstream kernel linux clock include use TOP_DA_SEL instead of
TOP_DA_SELM_XTAL_SEL.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/mediatek/clk-mt7988.c | 2 +-
include/dt-bindings/clock/mt7988-clk.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index e7ef58c4fb9..e2324f40084 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -396,7 +396,7 @@ static const struct mtk_composite topckgen_mtk_muxes[] = {
da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
1, 23, 0x1c8, 0),
- TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents,
+ TOP_MUX(CK_TOP_DA_SEL, "da_sel", sspxtp_parents,
0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
0x108, 0, 1, 7, 0x1c8, 2),
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 88a5cf45ccb..841dd419e75 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -299,7 +299,7 @@
#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */
#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */
#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */
-#define CK_TOP_DA_SELM_XTAL_SEL 128 /* Linux CLK ID (63) */
+#define CK_TOP_DA_SEL 128 /* Linux CLK ID (63) */
#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */
#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */
#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 03/13] clk: mediatek: mt7988: rename TOP_CK_NPU_SEL_CM_TOPS_SEL to TOP_NPU_SEL
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
2024-08-03 8:32 ` [PATCH 01/13] clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL Christian Marangi
2024-08-03 8:32 ` [PATCH 02/13] clk: mediatek: mt7988: rename TOP_DA_SELM_XTAL_SEL to TOP_DA_SEL Christian Marangi
@ 2024-08-03 8:32 ` Christian Marangi
2024-08-03 8:32 ` [PATCH 04/13] clk: mediatek: mt7988: move INFRA_PCIE_PERI_26M_CK_Px clock at top Christian Marangi
` (10 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Upstream kernel linux clock include use TOP_NPU_SEL instead of
TOP_CK_NPU_SEL_CM_TOPS_SEL.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/mediatek/clk-mt7988.c | 2 +-
include/dt-bindings/clock/mt7988-clk.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index e2324f40084..1ce8c4d8fef 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -420,7 +420,7 @@ static const struct mtk_composite topckgen_mtk_muxes[] = {
0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
0x124, 0x128, 0, 1, 7, 0x1c8, 10),
- TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel",
+ TOP_MUX(CK_TOP_NPU_SEL, "ck_npu_sel",
netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
};
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 841dd419e75..4fd968a12ca 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -309,7 +309,7 @@
#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */
#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */
#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */
-#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */
+#define CK_TOP_NPU_SEL 138 /* Linux CLK ID (73) */
/* APMIXEDSYS */
/* mtk_pll_data */
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 04/13] clk: mediatek: mt7988: move INFRA_PCIE_PERI_26M_CK_Px clock at top
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (2 preceding siblings ...)
2024-08-03 8:32 ` [PATCH 03/13] clk: mediatek: mt7988: rename TOP_CK_NPU_SEL_CM_TOPS_SEL to TOP_NPU_SEL Christian Marangi
@ 2024-08-03 8:32 ` Christian Marangi
2024-08-03 8:32 ` [PATCH 05/13] clk: mediatek: mt7988: fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2 Christian Marangi
` (9 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Move INFRA_PCIE_PERI_26M_CK_Px clock at top of the infracfg gates
in preparation for support of OF_UPSTREAM to have a 1:1 match with
upstream clock ID.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/mediatek/clk-mt7988.c | 16 +--
include/dt-bindings/clock/mt7988-clk.h | 168 ++++++++++++-------------
2 files changed, 92 insertions(+), 92 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 1ce8c4d8fef..5d146246fea 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -645,6 +645,14 @@ static const struct mtk_gate_regs infra_3_cg_regs = {
/* INFRA GATE */
static const struct mtk_gate infracfg_mtk_gates[] = {
+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
+ "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
+ "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
+ "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
+ "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
CK_INFRA_66M_MCK, 0),
GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
@@ -797,14 +805,6 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
CK_INFRA_133M_PHCK, 30),
GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
CK_INFRA_133M_PHCK, 31),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
- "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
- "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
- "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
- "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
};
static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 4fd968a12ca..5c643b979b5 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -80,93 +80,93 @@
#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */
#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */
/* mtk_gate */
-#define CK_INFRA_66M_GPT_BCK (65 - GATE_OFFSET) /* Linux CLK ID (19) */
-#define CK_INFRA_66M_PWM_HCK (66 - GATE_OFFSET) /* Linux CLK ID (20) */
-#define CK_INFRA_66M_PWM_BCK (67 - GATE_OFFSET) /* Linux CLK ID (21) */
-#define CK_INFRA_66M_PWM_CK1 (68 - GATE_OFFSET) /* Linux CLK ID (22) */
-#define CK_INFRA_66M_PWM_CK2 (69 - GATE_OFFSET) /* Linux CLK ID (23) */
-#define CK_INFRA_66M_PWM_CK3 (70 - GATE_OFFSET) /* Linux CLK ID (24) */
-#define CK_INFRA_66M_PWM_CK4 (71 - GATE_OFFSET) /* Linux CLK ID (25) */
-#define CK_INFRA_66M_PWM_CK5 (72 - GATE_OFFSET) /* Linux CLK ID (26) */
-#define CK_INFRA_66M_PWM_CK6 (73 - GATE_OFFSET) /* Linux CLK ID (27) */
-#define CK_INFRA_66M_PWM_CK7 (74 - GATE_OFFSET) /* Linux CLK ID (28) */
-#define CK_INFRA_66M_PWM_CK8 (75 - GATE_OFFSET) /* Linux CLK ID (29) */
-#define CK_INFRA_133M_CQDMA_BCK (76 - GATE_OFFSET) /* Linux CLK ID (30) */
-#define CK_INFRA_66M_AUD_SLV_BCK (77 - GATE_OFFSET) /* Linux CLK ID (31) */
-#define CK_INFRA_AUD_26M (78 - GATE_OFFSET) /* Linux CLK ID (32) */
-#define CK_INFRA_AUD_L (79 - GATE_OFFSET) /* Linux CLK ID (33) */
-#define CK_INFRA_AUD_AUD (80 - GATE_OFFSET) /* Linux CLK ID (34) */
-#define CK_INFRA_AUD_EG2 (81 - GATE_OFFSET) /* Linux CLK ID (35) */
-#define CK_INFRA_DRAMC_F26M (82 - GATE_OFFSET) /* Linux CLK ID (36) */
-#define CK_INFRA_133M_DBG_ACKM (83 - GATE_OFFSET) /* Linux CLK ID (37) */
-#define CK_INFRA_66M_AP_DMA_BCK (84 - GATE_OFFSET) /* Linux CLK ID (38) */
-#define CK_INFRA_66M_SEJ_BCK (85 - GATE_OFFSET) /* Linux CLK ID (39) */
-#define CK_INFRA_PRE_CK_SEJ_F13M (86 - GATE_OFFSET) /* Linux CLK ID (40) */
-#define CK_INFRA_66M_TRNG (87 - GATE_OFFSET) /* Linux CLK ID (41) */
-#define CK_INFRA_26M_THERM_SYSTEM (88 - GATE_OFFSET) /* Linux CLK ID (42) */
-#define CK_INFRA_I2C_BCK (89 - GATE_OFFSET) /* Linux CLK ID (43) */
-#define CK_INFRA_66M_UART0_PCK (90 - GATE_OFFSET) /* Linux CLK ID (44) */
-#define CK_INFRA_66M_UART1_PCK (91 - GATE_OFFSET) /* Linux CLK ID (45) */
-#define CK_INFRA_66M_UART2_PCK (92 - GATE_OFFSET) /* Linux CLK ID (46) */
-#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */
-#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */
-#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */
-#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */
-#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */
-#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */
-#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */
-#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */
-#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */
-#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */
-#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */
-#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */
-#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */
-#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */
-#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */
-#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */
-#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */
-#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */
-#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */
-#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */
-#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */
-#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */
-#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */
-#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */
-#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */
-#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */
-#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */
-#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */
-#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */
-#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */
-#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */
-#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */
-#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */
-#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */
-#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */
-#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */
-#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */
-#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */
-#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */
-#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */
-#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */
-#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */
-#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */
-#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */
-#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */
-#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */
-#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */
-#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */
-#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */
-#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */
-#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */
-#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */
+#define CK_INFRA_PCIE_PERI_26M_CK_P0 (65 - GATE_OFFSET) /* Linux CLK ID (99) */
#define CK_INFRA_PCIE_PERI_26M_CK_P1 \
- (146 - GATE_OFFSET) /* Linux CLK ID (100) */
+ (66 - GATE_OFFSET) /* Linux CLK ID (100) */
#define CK_INFRA_PCIE_PERI_26M_CK_P2 \
- (147 - GATE_OFFSET) /* Linux CLK ID (101) */
+ (67 - GATE_OFFSET) /* Linux CLK ID (101) */
#define CK_INFRA_PCIE_PERI_26M_CK_P3 \
- (148 - GATE_OFFSET) /* Linux CLK ID (102) */
+ (68 - GATE_OFFSET) /* Linux CLK ID (102) */
+#define CK_INFRA_66M_GPT_BCK (69 - GATE_OFFSET) /* Linux CLK ID (19) */
+#define CK_INFRA_66M_PWM_HCK (70 - GATE_OFFSET) /* Linux CLK ID (20) */
+#define CK_INFRA_66M_PWM_BCK (71 - GATE_OFFSET) /* Linux CLK ID (21) */
+#define CK_INFRA_66M_PWM_CK1 (72 - GATE_OFFSET) /* Linux CLK ID (22) */
+#define CK_INFRA_66M_PWM_CK2 (73 - GATE_OFFSET) /* Linux CLK ID (23) */
+#define CK_INFRA_66M_PWM_CK3 (74 - GATE_OFFSET) /* Linux CLK ID (24) */
+#define CK_INFRA_66M_PWM_CK4 (75 - GATE_OFFSET) /* Linux CLK ID (25) */
+#define CK_INFRA_66M_PWM_CK5 (76 - GATE_OFFSET) /* Linux CLK ID (26) */
+#define CK_INFRA_66M_PWM_CK6 (77 - GATE_OFFSET) /* Linux CLK ID (27) */
+#define CK_INFRA_66M_PWM_CK7 (78 - GATE_OFFSET) /* Linux CLK ID (28) */
+#define CK_INFRA_66M_PWM_CK8 (79 - GATE_OFFSET) /* Linux CLK ID (29) */
+#define CK_INFRA_133M_CQDMA_BCK (80 - GATE_OFFSET) /* Linux CLK ID (30) */
+#define CK_INFRA_66M_AUD_SLV_BCK (81 - GATE_OFFSET) /* Linux CLK ID (31) */
+#define CK_INFRA_AUD_26M (82 - GATE_OFFSET) /* Linux CLK ID (32) */
+#define CK_INFRA_AUD_L (83 - GATE_OFFSET) /* Linux CLK ID (33) */
+#define CK_INFRA_AUD_AUD (84 - GATE_OFFSET) /* Linux CLK ID (34) */
+#define CK_INFRA_AUD_EG2 (85 - GATE_OFFSET) /* Linux CLK ID (35) */
+#define CK_INFRA_DRAMC_F26M (86 - GATE_OFFSET) /* Linux CLK ID (36) */
+#define CK_INFRA_133M_DBG_ACKM (87 - GATE_OFFSET) /* Linux CLK ID (37) */
+#define CK_INFRA_66M_AP_DMA_BCK (88 - GATE_OFFSET) /* Linux CLK ID (38) */
+#define CK_INFRA_66M_SEJ_BCK (89 - GATE_OFFSET) /* Linux CLK ID (39) */
+#define CK_INFRA_PRE_CK_SEJ_F13M (90 - GATE_OFFSET) /* Linux CLK ID (40) */
+#define CK_INFRA_66M_TRNG (91 - GATE_OFFSET) /* Linux CLK ID (41) */
+#define CK_INFRA_26M_THERM_SYSTEM (92 - GATE_OFFSET) /* Linux CLK ID (42) */
+#define CK_INFRA_I2C_BCK (93 - GATE_OFFSET) /* Linux CLK ID (43) */
+#define CK_INFRA_66M_UART0_PCK (94 - GATE_OFFSET) /* Linux CLK ID (44) */
+#define CK_INFRA_66M_UART1_PCK (95 - GATE_OFFSET) /* Linux CLK ID (45) */
+#define CK_INFRA_66M_UART2_PCK (96 - GATE_OFFSET) /* Linux CLK ID (46) */
+#define CK_INFRA_52M_UART0_CK (97 - GATE_OFFSET) /* Linux CLK ID (47) */
+#define CK_INFRA_52M_UART1_CK (98 - GATE_OFFSET) /* Linux CLK ID (48) */
+#define CK_INFRA_52M_UART2_CK (99 - GATE_OFFSET) /* Linux CLK ID (49) */
+#define CK_INFRA_NFI (100 - GATE_OFFSET) /* Linux CLK ID (50) */
+#define CK_INFRA_SPINFI (101 - GATE_OFFSET) /* Linux CLK ID (51) */
+#define CK_INFRA_66M_NFI_HCK (102 - GATE_OFFSET) /* Linux CLK ID (52) */
+#define CK_INFRA_104M_SPI0 (103 - GATE_OFFSET) /* Linux CLK ID (53) */
+#define CK_INFRA_104M_SPI1 (104 - GATE_OFFSET) /* Linux CLK ID (54) */
+#define CK_INFRA_104M_SPI2_BCK (105 - GATE_OFFSET) /* Linux CLK ID (55) */
+#define CK_INFRA_66M_SPI0_HCK (106 - GATE_OFFSET) /* Linux CLK ID (56) */
+#define CK_INFRA_66M_SPI1_HCK (107 - GATE_OFFSET) /* Linux CLK ID (57) */
+#define CK_INFRA_66M_SPI2_HCK (108 - GATE_OFFSET) /* Linux CLK ID (58) */
+#define CK_INFRA_66M_FLASHIF_AXI (109 - GATE_OFFSET) /* Linux CLK ID (59) */
+#define CK_INFRA_RTC (110 - GATE_OFFSET) /* Linux CLK ID (60) */
+#define CK_INFRA_26M_ADC_BCK (111 - GATE_OFFSET) /* Linux CLK ID (61) */
+#define CK_INFRA_RC_ADC (112 - GATE_OFFSET) /* Linux CLK ID (62) */
+#define CK_INFRA_MSDC400 (113 - GATE_OFFSET) /* Linux CLK ID (63) */
+#define CK_INFRA_MSDC2_HCK (114 - GATE_OFFSET) /* Linux CLK ID (64) */
+#define CK_INFRA_133M_MSDC_0_HCK (115 - GATE_OFFSET) /* Linux CLK ID (65) */
+#define CK_INFRA_66M_MSDC_0_HCK (116 - GATE_OFFSET) /* Linux CLK ID (66) */
+#define CK_INFRA_133M_CPUM_BCK (117 - GATE_OFFSET) /* Linux CLK ID (67) */
+#define CK_INFRA_BIST2FPC (118 - GATE_OFFSET) /* Linux CLK ID (68) */
+#define CK_INFRA_I2C_X16W_MCK_CK_P1 (119 - GATE_OFFSET) /* Linux CLK ID (69) */
+#define CK_INFRA_I2C_X16W_PCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (70) */
+#define CK_INFRA_133M_USB_HCK (121 - GATE_OFFSET) /* Linux CLK ID (71) */
+#define CK_INFRA_133M_USB_HCK_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (72) */
+#define CK_INFRA_66M_USB_HCK (123 - GATE_OFFSET) /* Linux CLK ID (73) */
+#define CK_INFRA_66M_USB_HCK_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (74) */
+#define CK_INFRA_USB_SYS (125 - GATE_OFFSET) /* Linux CLK ID (75) */
+#define CK_INFRA_USB_SYS_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (76) */
+#define CK_INFRA_USB_REF (127 - GATE_OFFSET) /* Linux CLK ID (77) */
+#define CK_INFRA_USB_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (78) */
+#define CK_INFRA_USB_FRMCNT (129 - GATE_OFFSET) /* Linux CLK ID (79) */
+#define CK_INFRA_USB_FRMCNT_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (80) */
+#define CK_INFRA_USB_PIPE (131 - GATE_OFFSET) /* Linux CLK ID (81) */
+#define CK_INFRA_USB_PIPE_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (82) */
+#define CK_INFRA_USB_UTMI (133 - GATE_OFFSET) /* Linux CLK ID (83) */
+#define CK_INFRA_USB_UTMI_CK_P1 (134 - GATE_OFFSET) /* Linux CLK ID (84) */
+#define CK_INFRA_USB_XHCI (135 - GATE_OFFSET) /* Linux CLK ID (85) */
+#define CK_INFRA_USB_XHCI_CK_P1 (136 - GATE_OFFSET) /* Linux CLK ID (86) */
+#define CK_INFRA_PCIE_GFMUX_TL_P0 (137 - GATE_OFFSET) /* Linux CLK ID (87) */
+#define CK_INFRA_PCIE_GFMUX_TL_P1 (138 - GATE_OFFSET) /* Linux CLK ID (88) */
+#define CK_INFRA_PCIE_GFMUX_TL_P2 (139 - GATE_OFFSET) /* Linux CLK ID (89) */
+#define CK_INFRA_PCIE_GFMUX_TL_P3 (140 - GATE_OFFSET) /* Linux CLK ID (90) */
+#define CK_INFRA_PCIE_PIPE_P0 (141 - GATE_OFFSET) /* Linux CLK ID (91) */
+#define CK_INFRA_PCIE_PIPE_P1 (142 - GATE_OFFSET) /* Linux CLK ID (92) */
+#define CK_INFRA_PCIE_PIPE_P2 (143 - GATE_OFFSET) /* Linux CLK ID (93) */
+#define CK_INFRA_PCIE_PIPE_P3 (144 - GATE_OFFSET) /* Linux CLK ID (94) */
+#define CK_INFRA_133M_PCIE_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (95) */
+#define CK_INFRA_133M_PCIE_CK_P1 (146 - GATE_OFFSET) /* Linux CLK ID (96) */
+#define CK_INFRA_133M_PCIE_CK_P2 (147 - GATE_OFFSET) /* Linux CLK ID (97) */
+#define CK_INFRA_133M_PCIE_CK_P3 (148 - GATE_OFFSET) /* Linux CLK ID (98) */
/* TOPCKGEN */
/* mtk_fixed_factor */
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 05/13] clk: mediatek: mt7988: fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (3 preceding siblings ...)
2024-08-03 8:32 ` [PATCH 04/13] clk: mediatek: mt7988: move INFRA_PCIE_PERI_26M_CK_Px clock at top Christian Marangi
@ 2024-08-03 8:32 ` Christian Marangi
2024-08-03 8:32 ` [PATCH 06/13] clk: mediatek: mt7988: drop 1/1 infracfg spurious factor Christian Marangi
` (8 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2 as should be
INFRA_PCIE_PERI_26M_CK_P3 instead of INFRA_F26M_O0. This is to match
implementation on upstream kernel linux.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/mediatek/clk-mt7988.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 5d146246fea..a37ad574e11 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -650,7 +650,7 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
"infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
- "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
+ "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_PCIE_PERI_26M_CK_P3, 9),
GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
"infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 06/13] clk: mediatek: mt7988: drop 1/1 infracfg spurious factor
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (4 preceding siblings ...)
2024-08-03 8:32 ` [PATCH 05/13] clk: mediatek: mt7988: fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2 Christian Marangi
@ 2024-08-03 8:32 ` Christian Marangi
2024-08-03 8:32 ` [PATCH 07/13] clk: mediatek: mt7988: rename TOPCKGEN factor clock to upstream naming Christian Marangi
` (7 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7988.
Drop the factor entry from mt7988-clk.h and reference to them in
mt7988.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm/dts/mt7988.dtsi | 6 +-
drivers/clk/mediatek/clk-mt7988.c | 468 +++++++++++--------------
include/dt-bindings/clock/mt7988-clk.h | 87 +----
3 files changed, 227 insertions(+), 334 deletions(-)
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index 2605e60c993..e8ab5e625da 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -266,7 +266,7 @@
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
- <&infracfg_ao CK_INFRA_UART_O0>;
+ <&topckgen CK_TOP_UART_SEL>;
status = "disabled";
};
@@ -278,7 +278,7 @@
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
- <&infracfg_ao CK_INFRA_UART_O1>;
+ <&topckgen CK_TOP_UART_SEL>;
status = "disabled";
};
@@ -290,7 +290,7 @@
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
- <&infracfg_ao CK_INFRA_UART_O2>;
+ <&topckgen CK_TOP_UART_SEL>;
status = "disabled";
};
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index a37ad574e11..104f072cd0d 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -424,116 +424,42 @@ static const struct mtk_composite topckgen_mtk_muxes[] = {
netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
};
-/* INFRA FIXED DIV */
-static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = {
- TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0",
- CK_TOP_PEXTP_TL_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
- CK_TOP_PEXTP_TL_P1_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
- CK_TOP_PEXTP_TL_P2_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
- CK_TOP_PEXTP_TL_P3_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
- INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
- 1),
- TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1,
- 1),
- TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1),
- TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1),
- TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1,
- 1),
- TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1),
- TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1),
- INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC,
- 1, 1),
- TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1,
- 1),
- TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ",
- CK_TOP_EMMC_250M, 1, 1),
- TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o",
- CK_TOP_USB_FRMCNT, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
- CK_TOP_USB_FRMCNT_P1, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1,
- 1),
- TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1",
- CK_TOP_USB_XHCI_P1, 1, 1),
- XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1,
- 1),
- XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1,
- 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
- CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
- CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
- CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
- CLK_XTAL, 1, 1),
- TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1),
- TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1,
- 1),
- TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1",
- CK_TOP_USB_SYS_P1, 1, 1),
-};
-
/* INFRASYS MUX PARENTS */
-static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M,
- CK_INFRA_UART_O0 };
+static const int infra_mux_uart0_parents[] = { CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_UART_SEL };
-static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M,
- CK_INFRA_UART_O1 };
+static const int infra_mux_uart1_parents[] = { CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_UART_SEL };
-static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M,
- CK_INFRA_UART_O2 };
+static const int infra_mux_uart2_parents[] = { CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_UART_SEL };
-static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O };
+static const int infra_mux_spi0_parents[] = { CK_TOP_I2C_BCK, CK_TOP_SPI };
-static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O };
+static const int infra_mux_spi1_parents[] = { CK_TOP_I2C_BCK, CK_TOP_SPIM_MST };
static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K,
- CK_INFRA_CK_F26M, CK_INFRA_66M_MCK,
- CK_INFRA_PWM_O };
+ CK_TOP_INFRA_F26M_SEL, CK_TOP_SYSAXI,
+ CK_TOP_PWM_SEL };
static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P0
+ CK_TOP_INFRA_F32K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_PEXTP_TL_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P1
+ CK_TOP_INFRA_F32K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_PEXTP_TL_P1_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P2
+ CK_TOP_INFRA_F32K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_PEXTP_TL_P2_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P3
+ CK_TOP_INFRA_F32K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_PEXTP_TL_P3_SEL
};
#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
@@ -542,7 +468,7 @@ static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
.mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .parent = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \
}
/* INFRA MUX */
@@ -615,196 +541,214 @@ static const struct mtk_gate_regs infra_3_cg_regs = {
.sta_ofs = 0x68,
};
-#define GATE_INFRA0(_id, _name, _parent, _shift) \
+#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA1(_id, _name, _parent, _shift) \
+#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA2(_id, _name, _parent, _shift) \
+#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA3(_id, _name, _parent, _shift) \
+#define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_3_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
/* INFRA GATE */
static const struct mtk_gate infracfg_mtk_gates[] = {
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
- "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
- "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
- "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_PCIE_PERI_26M_CK_P3, 9),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
- "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
- GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
- CK_INFRA_66M_MCK, 0),
- GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
- CK_INFRA_66M_MCK, 1),
- GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
- CK_INFRA_PWM_SEL, 2),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
- CK_INFRA_PWM_CK1_SEL, 3),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
- CK_INFRA_PWM_CK2_SEL, 4),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
- CK_INFRA_PWM_CK3_SEL, 5),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
- CK_INFRA_PWM_CK4_SEL, 6),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
- CK_INFRA_PWM_CK5_SEL, 7),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
- CK_INFRA_PWM_CK6_SEL, 8),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
- CK_INFRA_PWM_CK7_SEL, 9),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
- CK_INFRA_PWM_CK8_SEL, 10),
- GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
- CK_INFRA_133M_MCK, 12),
- GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
- CK_INFRA_66M_PHCK, 13),
- GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14),
- GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15),
- GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O,
- 16),
- GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O,
- 18),
- GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M,
- 19),
- GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
- CK_INFRA_133M_MCK, 20),
- GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
- CK_INFRA_66M_MCK, 21),
- GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
- CK_INFRA_66M_MCK, 29),
- GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
- CK_INFRA_CK_F26M, 30),
- GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O,
- 31),
- GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
- CK_INFRA_CK_F26M, 0),
- GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1),
- GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
- CK_INFRA_66M_MCK, 3),
- GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
- CK_INFRA_66M_MCK, 4),
- GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
- CK_INFRA_66M_MCK, 5),
- GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
- CK_INFRA_MUX_UART0_SEL, 3),
- GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
- CK_INFRA_MUX_UART1_SEL, 4),
- GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
- CK_INFRA_MUX_UART2_SEL, 5),
- GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9),
- GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10),
- GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
- CK_INFRA_66M_MCK, 11),
- GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
- CK_INFRA_MUX_SPI0_SEL, 12),
- GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
- CK_INFRA_MUX_SPI1_SEL, 13),
- GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
- CK_INFRA_MUX_SPI2_SEL, 14),
- GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
- CK_INFRA_66M_MCK, 15),
- GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
- CK_INFRA_66M_MCK, 16),
- GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
- CK_INFRA_66M_MCK, 17),
- GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
- CK_INFRA_66M_MCK, 18),
- GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19),
- GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
- CK_INFRA_F26M_O1, 20),
- GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
- 21),
- GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O,
- 22),
- GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
- CK_INFRA_FMSDC2_HCK_OCC, 23),
- GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
- CK_INFRA_PERI_133M, 24),
- GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
- CK_INFRA_66M_PHCK, 25),
- GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
- CK_INFRA_133M_MCK, 26),
- GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O,
- 27),
- GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
- CK_INFRA_133M_MCK, 29),
- GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
- CK_INFRA_66M_PHCK, 31),
- GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
- CK_INFRA_133M_PHCK, 0),
- GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
- CK_INFRA_133M_PHCK, 1),
- GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
- CK_INFRA_66M_PHCK, 2),
- GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
- CK_INFRA_66M_PHCK, 3),
- GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4),
- GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
- CK_INFRA_USB_SYS_O_P1, 5),
- GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6),
- GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1,
- 7),
- GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
- CK_INFRA_USB_FRMCNT_O, 8),
- GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
- CK_INFRA_USB_FRMCNT_O_P1, 9),
- GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O,
- 10),
- GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
- CK_INFRA_USB_PIPE_O_P1, 11),
- GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O,
- 12),
- GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
- CK_INFRA_USB_UTMI_O_P1, 13),
- GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O,
- 14),
- GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
- CK_INFRA_USB_XHCI_O_P1, 15),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
- CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
- CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
- CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
- CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
- CK_INFRA_PCIE_PIPE_OCC_P0, 24),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
- CK_INFRA_PCIE_PIPE_OCC_P1, 25),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
- CK_INFRA_PCIE_PIPE_OCC_P2, 26),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
- CK_INFRA_PCIE_PIPE_OCC_P3, 27),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
- CK_INFRA_133M_PHCK, 28),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
- CK_INFRA_133M_PHCK, 29),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
- CK_INFRA_133M_PHCK, 30),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
- CK_INFRA_133M_PHCK, 31),
+ GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P0,
+ "infra_pcie_peri_ck_26m_ck_p0", CK_TOP_INFRA_F26M, 7),
+ GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P1,
+ "infra_pcie_peri_ck_26m_ck_p1", CK_TOP_INFRA_F26M, 8),
+ GATE_INFRA0_INFRA(CK_INFRA_PCIE_PERI_26M_CK_P2,
+ "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_PCIE_PERI_26M_CK_P3, 9),
+ GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P3,
+ "infra_pcie_peri_ck_26m_ck_p3", CK_TOP_INFRA_F26M, 10),
+ GATE_INFRA1_TOP(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
+ CK_TOP_SYSAXI, 0),
+ GATE_INFRA1_TOP(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
+ CK_TOP_SYSAXI, 1),
+ GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
+ CK_INFRA_PWM_SEL, 2),
+ GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
+ CK_INFRA_PWM_CK1_SEL, 3),
+ GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
+ CK_INFRA_PWM_CK2_SEL, 4),
+ GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
+ CK_INFRA_PWM_CK3_SEL, 5),
+ GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
+ CK_INFRA_PWM_CK4_SEL, 6),
+ GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
+ CK_INFRA_PWM_CK5_SEL, 7),
+ GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
+ CK_INFRA_PWM_CK6_SEL, 8),
+ GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
+ CK_INFRA_PWM_CK7_SEL, 9),
+ GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
+ CK_INFRA_PWM_CK8_SEL, 10),
+ GATE_INFRA1_TOP(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
+ CK_TOP_SYSAXI, 12),
+ GATE_INFRA1_TOP(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
+ CK_TOP_SYSAXI, 13),
+ GATE_INFRA1_TOP(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_TOP_INFRA_F26M_SEL, 14),
+ GATE_INFRA1_TOP(CK_INFRA_AUD_L, "infra_f_faud_l", CK_TOP_AUD_L, 15),
+ GATE_INFRA1_TOP(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_TOP_A1SYS,
+ 16),
+ GATE_INFRA1_TOP(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_TOP_A_TUNER,
+ 18),
+ GATE_INFRA1_TOP(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_TOP_INFRA_F26M_SEL,
+ 19),
+ GATE_INFRA1_TOP(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
+ CK_TOP_SYSAXI, 20),
+ GATE_INFRA1_TOP(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
+ CK_TOP_SYSAXI, 21),
+ GATE_INFRA1_TOP(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
+ CK_TOP_SYSAXI, 29),
+ GATE_INFRA1_TOP(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
+ CK_TOP_INFRA_F26M_SEL, 30),
+ GATE_INFRA1_TOP(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_TOP_SYSAXI,
+ 31),
+ GATE_INFRA2_TOP(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
+ CK_TOP_INFRA_F26M_SEL, 0),
+ GATE_INFRA2_TOP(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_TOP_I2C_BCK, 1),
+ GATE_INFRA2_TOP(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
+ CK_TOP_SYSAXI, 3),
+ GATE_INFRA2_TOP(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
+ CK_TOP_SYSAXI, 4),
+ GATE_INFRA2_TOP(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
+ CK_TOP_SYSAXI, 5),
+ GATE_INFRA2_INFRA(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
+ CK_INFRA_MUX_UART0_SEL, 3),
+ GATE_INFRA2_INFRA(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
+ CK_INFRA_MUX_UART1_SEL, 4),
+ GATE_INFRA2_INFRA(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
+ CK_INFRA_MUX_UART2_SEL, 5),
+ GATE_INFRA2_TOP(CK_INFRA_NFI, "infra_f_fnfi", CK_TOP_NFI1X, 9),
+ GATE_INFRA2_TOP(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_TOP_SPINFI_BCK, 10),
+ GATE_INFRA2_TOP(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
+ CK_TOP_SYSAXI, 11),
+ GATE_INFRA2_INFRA(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
+ CK_INFRA_MUX_SPI0_SEL, 12),
+ GATE_INFRA2_INFRA(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
+ CK_INFRA_MUX_SPI1_SEL, 13),
+ GATE_INFRA2_INFRA(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
+ CK_INFRA_MUX_SPI2_SEL, 14),
+ GATE_INFRA2_TOP(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
+ CK_TOP_SYSAXI, 15),
+ GATE_INFRA2_TOP(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
+ CK_TOP_SYSAXI, 16),
+ GATE_INFRA2_TOP(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
+ CK_TOP_SYSAXI, 17),
+ GATE_INFRA2_TOP(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
+ CK_TOP_SYSAXI, 18),
+ GATE_INFRA2_TOP(CK_INFRA_RTC, "infra_f_frtc", CK_TOP_CB_RTC_32K, 19),
+ GATE_INFRA2_TOP(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
+ CK_TOP_INFRA_F26M, 20),
+ GATE_INFRA2_INFRA(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
+ 21),
+ GATE_INFRA2_TOP(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_TOP_EMMC_400M,
+ 22),
+ GATE_INFRA2_TOP(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
+ CK_TOP_EMMC_250M, 23),
+ GATE_INFRA2_TOP(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
+ CK_TOP_SYSAXI, 24),
+ GATE_INFRA2_TOP(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
+ CK_TOP_SYSAXI, 25),
+ GATE_INFRA2_TOP(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
+ CK_TOP_SYSAXI, 26),
+ GATE_INFRA2_TOP(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_TOP_NFI1X,
+ 27),
+ GATE_INFRA2_TOP(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
+ CK_TOP_SYSAXI, 29),
+ GATE_INFRA2_TOP(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
+ CK_TOP_SYSAXI, 31),
+ GATE_INFRA3_TOP(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
+ CK_TOP_SYSAXI, 0),
+ GATE_INFRA3_TOP(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
+ CK_TOP_SYSAXI, 1),
+ GATE_INFRA3_TOP(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
+ CK_TOP_SYSAXI, 2),
+ GATE_INFRA3_TOP(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
+ CK_TOP_SYSAXI, 3),
+ GATE_INFRA3_TOP(CK_INFRA_USB_SYS, "infra_usb_sys", CK_TOP_USB_SYS, 4),
+ GATE_INFRA3_TOP(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
+ CK_TOP_USB_SYS_P1, 5),
+ GATE_INFRA3_TOP(CK_INFRA_USB_REF, "infra_usb_ref", CK_TOP_USB_REF, 6),
+ GATE_INFRA3_TOP(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_TOP_USB_CK_P1,
+ 7),
+ GATE_INFRA3_TOP(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
+ CK_TOP_USB_FRMCNT, 8),
+ GATE_INFRA3_TOP(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
+ CK_TOP_USB_FRMCNT_P1, 9),
+ GATE_INFRA3_XTAL(CK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL,
+ 10),
+ GATE_INFRA3_XTAL(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
+ CLK_XTAL, 11),
+ GATE_INFRA3_XTAL(CK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL,
+ 12),
+ GATE_INFRA3_XTAL(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
+ CLK_XTAL, 13),
+ GATE_INFRA3_TOP(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_TOP_USB_XHCI,
+ 14),
+ GATE_INFRA3_TOP(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
+ CK_TOP_USB_XHCI_P1, 15),
+ GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
+ CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
+ GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
+ CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
+ GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
+ CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
+ GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
+ CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
+ GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
+ CLK_XTAL, 24),
+ GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
+ CLK_XTAL, 25),
+ GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
+ CLK_XTAL, 26),
+ GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
+ CLK_XTAL, 27),
+ GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
+ CK_TOP_SYSAXI, 28),
+ GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
+ CK_TOP_SYSAXI, 29),
+ GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
+ CK_TOP_SYSAXI, 30),
+ GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
+ CK_TOP_SYSAXI, 31),
};
static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
@@ -823,9 +767,7 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
};
static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
- .fdivs_offs = CK_INFRA_CK_F26M,
.muxes_offs = CK_INFRA_MUX_UART0_SEL,
- .fdivs = infracfg_mtk_fixed_factor,
.muxes = infracfg_mtk_mux,
.flags = CLK_BYPASS_XTAL,
.xtal_rate = 40 * MHZ,
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 5c643b979b5..61691d58dda 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -8,77 +8,28 @@
#ifndef _DT_BINDINGS_CLK_MT7988_H
#define _DT_BINDINGS_CLK_MT7988_H
-/* INFRACFG */
-/* mtk_fixed_factor */
-#define CK_INFRA_CK_F26M 0
-#define CK_INFRA_PWM_O 1
-#define CK_INFRA_PCIE_OCC_P0 2
-#define CK_INFRA_PCIE_OCC_P1 3
-#define CK_INFRA_PCIE_OCC_P2 4
-#define CK_INFRA_PCIE_OCC_P3 5
-#define CK_INFRA_133M_HCK 6
-#define CK_INFRA_133M_PHCK 7
-#define CK_INFRA_66M_PHCK 8
-#define CK_INFRA_FAUD_L_O 9
-#define CK_INFRA_FAUD_AUD_O 10
-#define CK_INFRA_FAUD_EG2_O 11
-#define CK_INFRA_I2C_O 12
-#define CK_INFRA_UART_O0 13
-#define CK_INFRA_UART_O1 14
-#define CK_INFRA_UART_O2 15
-#define CK_INFRA_NFI_O 16
-#define CK_INFRA_SPINFI_O 17
-#define CK_INFRA_SPI0_O 18
-#define CK_INFRA_SPI1_O 19
-#define CK_INFRA_LB_MUX_FRTC 20
-#define CK_INFRA_FRTC 21
-#define CK_INFRA_FMSDC400_O 22
-#define CK_INFRA_FMSDC2_HCK_OCC 23
-#define CK_INFRA_PERI_133M 24
-#define CK_INFRA_USB_O 25
-#define CK_INFRA_USB_O_P1 26
-#define CK_INFRA_USB_FRMCNT_O 27
-#define CK_INFRA_USB_FRMCNT_O_P1 28
-#define CK_INFRA_USB_XHCI_O 29
-#define CK_INFRA_USB_XHCI_O_P1 30
-#define CK_INFRA_USB_PIPE_O 31
-#define CK_INFRA_USB_PIPE_O_P1 32
-#define CK_INFRA_USB_UTMI_O 33
-#define CK_INFRA_USB_UTMI_O_P1 34
-#define CK_INFRA_PCIE_PIPE_OCC_P0 35
-#define CK_INFRA_PCIE_PIPE_OCC_P1 36
-#define CK_INFRA_PCIE_PIPE_OCC_P2 37
-#define CK_INFRA_PCIE_PIPE_OCC_P3 38
-#define CK_INFRA_F26M_O0 39
-#define CK_INFRA_F26M_O1 40
-#define CK_INFRA_133M_MCK 41
-#define CK_INFRA_66M_MCK 42
-#define CK_INFRA_PERI_66M_O 43
-#define CK_INFRA_USB_SYS_O 44
-#define CK_INFRA_USB_SYS_O_P1 45
-
/* INFRACFG_AO */
#define GATE_OFFSET 65
/* mtk_mux */
-#define CK_INFRA_MUX_UART0_SEL 46 /* Linux CLK ID (0) */
-#define CK_INFRA_MUX_UART1_SEL 47 /* Linux CLK ID (1) */
-#define CK_INFRA_MUX_UART2_SEL 48 /* Linux CLK ID (2) */
-#define CK_INFRA_MUX_SPI0_SEL 49 /* Linux CLK ID (3) */
-#define CK_INFRA_MUX_SPI1_SEL 50 /* Linux CLK ID (4) */
-#define CK_INFRA_MUX_SPI2_SEL 51 /* Linux CLK ID (5) */
-#define CK_INFRA_PWM_SEL 52 /* Linux CLK ID (6) */
-#define CK_INFRA_PWM_CK1_SEL 53 /* Linux CLK ID (7) */
-#define CK_INFRA_PWM_CK2_SEL 54 /* Linux CLK ID (8) */
-#define CK_INFRA_PWM_CK3_SEL 55 /* Linux CLK ID (9) */
-#define CK_INFRA_PWM_CK4_SEL 56 /* Linux CLK ID (10) */
-#define CK_INFRA_PWM_CK5_SEL 57 /* Linux CLK ID (11) */
-#define CK_INFRA_PWM_CK6_SEL 58 /* Linux CLK ID (12) */
-#define CK_INFRA_PWM_CK7_SEL 59 /* Linux CLK ID (13) */
-#define CK_INFRA_PWM_CK8_SEL 60 /* Linux CLK ID (14) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */
+#define CK_INFRA_MUX_UART0_SEL 0 /* Linux CLK ID (0) */
+#define CK_INFRA_MUX_UART1_SEL 1 /* Linux CLK ID (1) */
+#define CK_INFRA_MUX_UART2_SEL 2 /* Linux CLK ID (2) */
+#define CK_INFRA_MUX_SPI0_SEL 3 /* Linux CLK ID (3) */
+#define CK_INFRA_MUX_SPI1_SEL 4 /* Linux CLK ID (4) */
+#define CK_INFRA_MUX_SPI2_SEL 5 /* Linux CLK ID (5) */
+#define CK_INFRA_PWM_SEL 6 /* Linux CLK ID (6) */
+#define CK_INFRA_PWM_CK1_SEL 7 /* Linux CLK ID (7) */
+#define CK_INFRA_PWM_CK2_SEL 8 /* Linux CLK ID (8) */
+#define CK_INFRA_PWM_CK3_SEL 9 /* Linux CLK ID (9) */
+#define CK_INFRA_PWM_CK4_SEL 10 /* Linux CLK ID (10) */
+#define CK_INFRA_PWM_CK5_SEL 11 /* Linux CLK ID (11) */
+#define CK_INFRA_PWM_CK6_SEL 12 /* Linux CLK ID (12) */
+#define CK_INFRA_PWM_CK7_SEL 13 /* Linux CLK ID (13) */
+#define CK_INFRA_PWM_CK8_SEL 14 /* Linux CLK ID (14) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 /* Linux CLK ID (15) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 /* Linux CLK ID (16) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 /* Linux CLK ID (17) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 /* Linux CLK ID (18) */
/* mtk_gate */
#define CK_INFRA_PCIE_PERI_26M_CK_P0 (65 - GATE_OFFSET) /* Linux CLK ID (99) */
#define CK_INFRA_PCIE_PERI_26M_CK_P1 \
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 07/13] clk: mediatek: mt7988: rename TOPCKGEN factor clock to upstream naming
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (5 preceding siblings ...)
2024-08-03 8:32 ` [PATCH 06/13] clk: mediatek: mt7988: drop 1/1 infracfg spurious factor Christian Marangi
@ 2024-08-03 8:32 ` Christian Marangi
2024-08-03 8:32 ` [PATCH 08/13] clk: mediatek: mt7988: reorder TOPCKGEN factor ID Christian Marangi
` (6 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Rename TOPCKGEN factor clock to upstream neaming.
Upstream kernel linux reference the factor clock for apmixedpll with the
"pll" suffix. Align the naming to the upstream naming format in
preparation for OF_UPSTREAM support.
Also rename rtc clock to drop the CB_ as upstream doesn't have that.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm/dts/mt7988.dtsi | 4 +-
drivers/clk/mediatek/clk-mt7988.c | 190 ++++++++++++-------------
include/dt-bindings/clock/mt7988-clk.h | 72 +++++-----
3 files changed, 133 insertions(+), 133 deletions(-)
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index e8ab5e625da..10d5c2a33c3 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -371,8 +371,8 @@
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
<&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
- <&topckgen CK_TOP_CB_M_D8>;
+ assigned-clock-parents = <&topckgen CK_TOP_MPLL_D8>,
+ <&topckgen CK_TOP_MPLL_D8>;
status = "disabled";
};
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 104f072cd0d..6bbc7045169 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -52,52 +52,52 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
XTAL_FACTOR(CK_TOP_XTAL, "xtal", CLK_XTAL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
- PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
- PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
- PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
- PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CK_TOP_CB_MPLL_416M, "cb_mpll_416m", CK_APMIXED_MPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CK_TOP_MPLL_D3_D2, "mpll_d3_d2", CK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CK_TOP_MPLL_D8, "mpll_d8", CK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CK_TOP_MPLL_D8_D2, "mpll_d8_d2", CK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CK_TOP_CB_MMPLL_720M, "cb_mmpll_720m", CK_APMIXED_MMPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_MMPLL_D2, "mmpll_d2", CK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CK_APMIXED_MMPLL, 1, 15),
+ PLL_FACTOR(CK_TOP_MMPLL_D4, "mmpll_d4", CK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CK_APMIXED_MMPLL, 1, 12),
+ PLL_FACTOR(CK_TOP_MMPLL_D8, "mmpll_d8", CK_APMIXED_MMPLL, 1, 8),
PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
1),
- PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
- PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
- PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
- PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
- PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
- PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1,
+ PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CK_TOP_NET1PLL_D4, "net1pll_d4", CK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CK_TOP_NET1PLL_D5, "net1pll_d5", CK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CK_TOP_NET1PLL_D8, "net1pll_d8", CK_APMIXED_NET1PLL, 1, 8),
+ PLL_FACTOR(CK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
+ PLL_FACTOR(CK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
+ PLL_FACTOR(CK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CK_APMIXED_NET1PLL, 1,
128),
- PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
+ PLL_FACTOR(CK_TOP_NET2PLL_800M, "cb_net2pll_800m", CK_APMIXED_NET2PLL, 1,
1),
- PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
- PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
- PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
+ PLL_FACTOR(CK_TOP_NET2PLL_D2, "net2pll_d2", CK_APMIXED_NET2PLL, 1, 2),
+ PLL_FACTOR(CK_TOP_NET2PLL_D4, "net2pll_d4", CK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
+ PLL_FACTOR(CK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
+ PLL_FACTOR(CK_TOP_NET2PLL_D6, "net2pll_d6", CK_APMIXED_NET2PLL, 1, 6),
+ PLL_FACTOR(CK_TOP_NET2PLL_D8, "net2pll_d8", CK_APMIXED_NET2PLL, 1, 8),
+ PLL_FACTOR(CK_TOP_CB_WEDMCUPLL_208M, "cb_wedmcupll_208m",
CK_APMIXED_WEDMCUPLL, 1, 1),
PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m",
+ PLL_FACTOR(CK_TOP_CB_NETSYSPLL_850M, "cb_netsyspll_850m",
CK_APMIXED_NETSYSPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1,
+ PLL_FACTOR(CK_TOP_CB_MSDCPLL_400M, "cb_msdcpll_400m", CK_APMIXED_MSDCPLL, 1,
1),
TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL, 1, 2),
- TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_XTAL, 1,
+ TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
1250),
- TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_XTAL, 1,
+ TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
1220),
- TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1,
+ TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_RTC_32P7K, 1,
1),
XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1),
TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
@@ -135,125 +135,125 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
};
/* TOPCKGEN MUX PARENTS */
-static const int netsys_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET2_D2,
- CK_TOP_CB_MM_D2 };
+static const int netsys_parents[] = { CK_TOP_XTAL, CK_TOP_NET2PLL_D2,
+ CK_TOP_MMPLL_D2 };
static const int netsys_500m_parents[] = { CK_TOP_XTAL,
- CK_TOP_CB_NET1_D5,
- CK_TOP_NET1_D5_D2 };
+ CK_TOP_NET1PLL_D5,
+ CK_TOP_NET1PLL_D5_D2 };
static const int netsys_2x_parents[] = { CK_TOP_XTAL,
- CK_TOP_CB_NET2_800M,
- CK_TOP_CB_MM_720M };
+ CK_TOP_NET2PLL_800M,
+ CK_TOP_CB_MMPLL_720M };
-static const int netsys_gsw_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET1_D4,
- CK_TOP_CB_NET1_D5 };
+static const int netsys_gsw_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D4,
+ CK_TOP_NET1PLL_D5 };
-static const int eth_gmii_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D4 };
+static const int eth_gmii_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D4 };
static const int netsys_mcu_parents[] = {
- CK_TOP_XTAL, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
- CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M
+ CK_TOP_XTAL, CK_TOP_NET2PLL_800M, CK_TOP_CB_MMPLL_720M,
+ CK_TOP_NET1PLL_D4, CK_TOP_NET1PLL_D5, CK_TOP_CB_MPLL_416M
};
static const int eip197_parents[] = {
- CK_TOP_XTAL, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
- CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5
+ CK_TOP_XTAL, CK_TOP_CB_NETSYSPLL_850M, CK_TOP_NET2PLL_800M,
+ CK_TOP_CB_MMPLL_720M, CK_TOP_NET1PLL_D4, CK_TOP_NET1PLL_D5
};
static const int axi_infra_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET1_D8_D2 };
+ CK_TOP_NET1PLL_D8_D2 };
-static const int uart_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D8,
- CK_TOP_M_D8_D2 };
+static const int uart_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D8,
+ CK_TOP_MPLL_D8_D2 };
-static const int emmc_250m_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D2,
- CK_TOP_CB_MM_D4 };
+static const int emmc_250m_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D2,
+ CK_TOP_MMPLL_D4 };
static const int emmc_400m_parents[] = {
- CK_TOP_XTAL, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
- CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2
+ CK_TOP_XTAL, CK_TOP_CB_MSDCPLL_400M, CK_TOP_MMPLL_D2,
+ CK_TOP_MPLL_D2, CK_TOP_MMPLL_D4, CK_TOP_NET1PLL_D8_D2
};
-static const int spi_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D2,
- CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const int spi_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D2,
+ CK_TOP_MMPLL_D4, CK_TOP_NET1PLL_D8_D2,
+ CK_TOP_NET2PLL_D6, CK_TOP_NET1PLL_D5_D4,
+ CK_TOP_MPLL_D4, CK_TOP_NET1PLL_D8_D4 };
-static const int nfi1x_parents[] = { CK_TOP_XTAL, CK_TOP_CB_MM_D4,
- CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
- CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
- CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
+static const int nfi1x_parents[] = { CK_TOP_XTAL, CK_TOP_MMPLL_D4,
+ CK_TOP_NET1PLL_D8_D2, CK_TOP_NET2PLL_D6,
+ CK_TOP_MPLL_D4, CK_TOP_MMPLL_D8,
+ CK_TOP_NET1PLL_D8_D4, CK_TOP_MPLL_D8 };
static const int spinfi_parents[] = { CK_TOP_XTAL_D2, CK_TOP_XTAL,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
- CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
+ CK_TOP_NET1PLL_D5_D4, CK_TOP_MPLL_D4,
+ CK_TOP_MMPLL_D8, CK_TOP_NET1PLL_D8_D4,
+ CK_TOP_MMPLL_D6_D2, CK_TOP_MPLL_D8 };
-static const int pwm_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D2,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+static const int pwm_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D8_D2,
+ CK_TOP_NET1PLL_D5_D4, CK_TOP_MPLL_D4,
+ CK_TOP_MPLL_D8_D2, CK_TOP_RTC_32K };
-static const int i2c_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const int i2c_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D4,
+ CK_TOP_MPLL_D4, CK_TOP_NET1PLL_D8_D4 };
static const int pcie_mbist_250m_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET1_D5_D2 };
+ CK_TOP_NET1PLL_D5_D2 };
static const int pextp_tl_ck_parents[] = { CK_TOP_XTAL,
- CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8,
- CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+ CK_TOP_NET2PLL_D6, CK_TOP_MMPLL_D8,
+ CK_TOP_MPLL_D8_D2, CK_TOP_RTC_32K };
static const int usb_frmcnt_parents[] = { CK_TOP_XTAL,
- CK_TOP_CB_MM_D3_D5 };
+ CK_TOP_MMPLL_D3_D5 };
static const int aud_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_196M };
-static const int a1sys_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_D4 };
+static const int a1sys_parents[] = { CK_TOP_XTAL, CK_TOP_APLL2_D4 };
static const int aud_l_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_196M,
- CK_TOP_M_D8_D2 };
+ CK_TOP_MPLL_D8_D2 };
-static const int sspxtp_parents[] = { CK_TOP_XTAL_D2, CK_TOP_M_D8_D2 };
+static const int sspxtp_parents[] = { CK_TOP_XTAL_D2, CK_TOP_MPLL_D8_D2 };
static const int usxgmii_sbus_0_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET1_D8_D4 };
+ CK_TOP_NET1PLL_D8_D4 };
static const int sgm_0_parents[] = { CK_TOP_XTAL, CK_TOP_CB_SGM_325M };
-static const int sysapb_parents[] = { CK_TOP_XTAL, CK_TOP_M_D3_D2 };
+static const int sysapb_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D3_D2 };
static const int eth_refck_50m_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET2_D4_D4 };
+ CK_TOP_NET2PLL_D4_D4 };
static const int eth_sys_200m_parents[] = { CK_TOP_XTAL,
- CK_TOP_CB_NET2_D4 };
+ CK_TOP_NET2PLL_D4 };
-static const int eth_xgmii_parents[] = { CK_TOP_XTAL_D2, CK_TOP_NET1_D8_D8,
- CK_TOP_NET1_D8_D16 };
+static const int eth_xgmii_parents[] = { CK_TOP_XTAL_D2, CK_TOP_NET1PLL_D8_D8,
+ CK_TOP_NET1PLL_D8_D16 };
-static const int bus_tops_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET1_D5,
- CK_TOP_CB_NET2_D2 };
+static const int bus_tops_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5,
+ CK_TOP_NET2PLL_D2 };
static const int npu_tops_parents[] = { CK_TOP_XTAL,
- CK_TOP_CB_NET2_800M };
+ CK_TOP_NET2PLL_800M };
-static const int dramc_md32_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D2,
- CK_TOP_CB_WEDMCU_208M };
+static const int dramc_md32_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D2,
+ CK_TOP_CB_WEDMCUPLL_208M };
static const int da_xtp_glb_p0_parents[] = { CK_TOP_XTAL,
- CK_TOP_CB_NET2_D8 };
+ CK_TOP_NET2PLL_D8 };
static const int mcusys_backup_625m_parents[] = { CK_TOP_XTAL,
- CK_TOP_CB_NET1_D4 };
+ CK_TOP_NET1PLL_D4 };
static const int macsec_parents[] = { CK_TOP_XTAL, CK_TOP_CB_SGM_325M,
- CK_TOP_CB_NET1_D8 };
+ CK_TOP_NET1PLL_D8 };
static const int netsys_tops_400m_parents[] = { CK_TOP_XTAL,
- CK_TOP_CB_NET2_D2 };
+ CK_TOP_NET2PLL_D2 };
-static const int eth_mii_parents[] = { CK_TOP_XTAL_D2, CK_TOP_NET2_D4_D8 };
+static const int eth_mii_parents[] = { CK_TOP_XTAL_D2, CK_TOP_NET2PLL_D4_D8 };
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd) \
@@ -674,7 +674,7 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
CK_TOP_SYSAXI, 17),
GATE_INFRA2_TOP(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
CK_TOP_SYSAXI, 18),
- GATE_INFRA2_TOP(CK_INFRA_RTC, "infra_f_frtc", CK_TOP_CB_RTC_32K, 19),
+ GATE_INFRA2_TOP(CK_INFRA_RTC, "infra_f_frtc", CK_TOP_RTC_32K, 19),
GATE_INFRA2_TOP(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
CK_TOP_INFRA_F26M, 20),
GATE_INFRA2_INFRA(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 61691d58dda..36a5f4818b2 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -122,43 +122,43 @@
/* TOPCKGEN */
/* mtk_fixed_factor */
#define CK_TOP_XTAL 0 /* Linux CLK ID (74) */
-#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */
-#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */
-#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */
-#define CK_TOP_CB_M_D4 4 /* Linux CLK ID (78) */
-#define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */
-#define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */
-#define CK_TOP_CB_MM_720M 7 /* Linux CLK ID (81) */
-#define CK_TOP_CB_MM_D2 8 /* Linux CLK ID (82) */
-#define CK_TOP_CB_MM_D3_D5 9 /* Linux CLK ID (83) */
-#define CK_TOP_CB_MM_D4 10 /* Linux CLK ID (84) */
-#define CK_TOP_MM_D6_D2 11 /* Linux CLK ID (85) */
-#define CK_TOP_CB_MM_D8 12 /* Linux CLK ID (86) */
+#define CK_TOP_CB_MPLL_416M 1 /* Linux CLK ID (75) */
+#define CK_TOP_MPLL_D2 2 /* Linux CLK ID (76) */
+#define CK_TOP_MPLL_D3_D2 3 /* Linux CLK ID (77) */
+#define CK_TOP_MPLL_D4 4 /* Linux CLK ID (78) */
+#define CK_TOP_MPLL_D8 5 /* Linux CLK ID (79) */
+#define CK_TOP_MPLL_D8_D2 6 /* Linux CLK ID (80) */
+#define CK_TOP_CB_MMPLL_720M 7 /* Linux CLK ID (81) */
+#define CK_TOP_MMPLL_D2 8 /* Linux CLK ID (82) */
+#define CK_TOP_MMPLL_D3_D5 9 /* Linux CLK ID (83) */
+#define CK_TOP_MMPLL_D4 10 /* Linux CLK ID (84) */
+#define CK_TOP_MMPLL_D6_D2 11 /* Linux CLK ID (85) */
+#define CK_TOP_MMPLL_D8 12 /* Linux CLK ID (86) */
#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */
-#define CK_TOP_CB_APLL2_D4 14 /* Linux CLK ID (88) */
-#define CK_TOP_CB_NET1_D4 15 /* Linux CLK ID (89) */
-#define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */
-#define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */
-#define CK_TOP_NET1_D5_D4 18 /* Linux CLK ID (92) */
-#define CK_TOP_CB_NET1_D8 19 /* Linux CLK ID (93) */
-#define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */
-#define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */
-#define CK_TOP_NET1_D8_D8 22 /* Linux CLK ID (96) */
-#define CK_TOP_NET1_D8_D16 23 /* Linux CLK ID (97) */
-#define CK_TOP_CB_NET2_800M 24 /* Linux CLK ID (98) */
-#define CK_TOP_CB_NET2_D2 25 /* Linux CLK ID (99) */
-#define CK_TOP_CB_NET2_D4 26 /* Linux CLK ID (100) */
-#define CK_TOP_NET2_D4_D4 27 /* Linux CLK ID (101) */
-#define CK_TOP_NET2_D4_D8 28 /* Linux CLK ID (102) */
-#define CK_TOP_CB_NET2_D6 29 /* Linux CLK ID (103) */
-#define CK_TOP_CB_NET2_D8 30 /* Linux CLK ID (104) */
-#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */
-#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */
-#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */
-#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */
-#define CK_TOP_XTAL_D2 35 /* Linux CLK ID (109) */
-#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */
-#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */
+#define CK_TOP_APLL2_D4 14 /* Linux CLK ID (88) */
+#define CK_TOP_NET1PLL_D4 15 /* Linux CLK ID (89) */
+#define CK_TOP_NET1PLL_D5 16 /* Linux CLK ID (90) */
+#define CK_TOP_NET1PLL_D5_D2 17 /* Linux CLK ID (91) */
+#define CK_TOP_NET1PLL_D5_D4 18 /* Linux CLK ID (92) */
+#define CK_TOP_NET1PLL_D8 19 /* Linux CLK ID (93) */
+#define CK_TOP_NET1PLL_D8_D2 20 /* Linux CLK ID (94) */
+#define CK_TOP_NET1PLL_D8_D4 21 /* Linux CLK ID (95) */
+#define CK_TOP_NET1PLL_D8_D8 22 /* Linux CLK ID (96) */
+#define CK_TOP_NET1PLL_D8_D16 23 /* Linux CLK ID (97) */
+#define CK_TOP_CB_NET2PLL_800M 24 /* Linux CLK ID (98) */
+#define CK_TOP_NET2PLL_D2 25 /* Linux CLK ID (99) */
+#define CK_TOP_NET2PLL_D4 26 /* Linux CLK ID (100) */
+#define CK_TOP_NET2PLL_D4_D4 27 /* Linux CLK ID (101) */
+#define CK_TOP_NET2PLL_D4_D8 28 /* Linux CLK ID (102) */
+#define CK_TOP_NET2PLL_D6 29 /* Linux CLK ID (103) */
+#define CK_TOP_NET2PLL_D8 30 /* Linux CLK ID (104) */
+#define CK_TOP_CB_WEDMCUPLL_208M 31 /* Linux CLK ID (105) */
+#define CK_TOP_CB_SGMPLL_325M 32 /* Linux CLK ID (106) */
+#define CK_TOP_CB_NETSYSPLL_850M 33 /* Linux CLK ID (107) */
+#define CK_TOP_CB_MSDCPLL_400M 34 /* Linux CLK ID (108) */
+#define CK_TOP_XTAL_D2 35 /* Linux CLK ID (109) */
+#define CK_TOP_RTC_32K 36 /* Linux CLK ID (110) */
+#define CK_TOP_RTC_32P7K 37 /* Linux CLK ID (111) */
#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */
#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */
#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 08/13] clk: mediatek: mt7988: reorder TOPCKGEN factor ID
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (6 preceding siblings ...)
2024-08-03 8:32 ` [PATCH 07/13] clk: mediatek: mt7988: rename TOPCKGEN factor clock to upstream naming Christian Marangi
@ 2024-08-03 8:32 ` Christian Marangi
2024-08-03 8:32 ` [PATCH 09/13] clk: mediatek: mt7988: drop 1/1 spurious factor for topckgen Christian Marangi
` (5 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Reorder TOPCKGEN factor ID to put TOP_FACTOR first and then PLL. This is
to match how it's done in upstream kernel linux and in preparation for
OF_UPSTREAM support.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/mediatek/clk-mt7988.c | 80 +++++++--------
include/dt-bindings/clock/mt7988-clk.h | 130 ++++++++++++-------------
2 files changed, 105 insertions(+), 105 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 6bbc7045169..24dc3299e11 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -52,46 +52,6 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
XTAL_FACTOR(CK_TOP_XTAL, "xtal", CLK_XTAL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MPLL_416M, "cb_mpll_416m", CK_APMIXED_MPLL, 1, 1),
- PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_MPLL_D3_D2, "mpll_d3_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
- PLL_FACTOR(CK_TOP_MPLL_D8, "mpll_d8", CK_APMIXED_MPLL, 1, 8),
- PLL_FACTOR(CK_TOP_MPLL_D8_D2, "mpll_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_MMPLL_720M, "cb_mmpll_720m", CK_APMIXED_MMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_MMPLL_D2, "mmpll_d2", CK_APMIXED_MMPLL, 1, 2),
- PLL_FACTOR(CK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CK_APMIXED_MMPLL, 1, 15),
- PLL_FACTOR(CK_TOP_MMPLL_D4, "mmpll_d4", CK_APMIXED_MMPLL, 1, 4),
- PLL_FACTOR(CK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CK_APMIXED_MMPLL, 1, 12),
- PLL_FACTOR(CK_TOP_MMPLL_D8, "mmpll_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
- 1),
- PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
- PLL_FACTOR(CK_TOP_NET1PLL_D4, "net1pll_d4", CK_APMIXED_NET1PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET1PLL_D5, "net1pll_d5", CK_APMIXED_NET1PLL, 1, 5),
- PLL_FACTOR(CK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
- PLL_FACTOR(CK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
- PLL_FACTOR(CK_TOP_NET1PLL_D8, "net1pll_d8", CK_APMIXED_NET1PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
- PLL_FACTOR(CK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
- PLL_FACTOR(CK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CK_APMIXED_NET1PLL, 1,
- 128),
- PLL_FACTOR(CK_TOP_NET2PLL_800M, "cb_net2pll_800m", CK_APMIXED_NET2PLL, 1,
- 1),
- PLL_FACTOR(CK_TOP_NET2PLL_D2, "net2pll_d2", CK_APMIXED_NET2PLL, 1, 2),
- PLL_FACTOR(CK_TOP_NET2PLL_D4, "net2pll_d4", CK_APMIXED_NET2PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
- PLL_FACTOR(CK_TOP_NET2PLL_D6, "net2pll_d6", CK_APMIXED_NET2PLL, 1, 6),
- PLL_FACTOR(CK_TOP_NET2PLL_D8, "net2pll_d8", CK_APMIXED_NET2PLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_WEDMCUPLL_208M, "cb_wedmcupll_208m",
- CK_APMIXED_WEDMCUPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_NETSYSPLL_850M, "cb_netsyspll_850m",
- CK_APMIXED_NETSYSPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MSDCPLL_400M, "cb_msdcpll_400m", CK_APMIXED_MSDCPLL, 1,
- 1),
TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL, 1, 2),
TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
1250),
@@ -132,6 +92,46 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
1, 1),
TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1),
TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1),
+ PLL_FACTOR(CK_TOP_CB_MPLL_416M, "cb_mpll_416m", CK_APMIXED_MPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CK_TOP_MPLL_D3_D2, "mpll_d3_d2", CK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CK_TOP_MPLL_D8, "mpll_d8", CK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CK_TOP_MPLL_D8_D2, "mpll_d8_d2", CK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CK_TOP_CB_MMPLL_720M, "cb_mmpll_720m", CK_APMIXED_MMPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_MMPLL_D2, "mmpll_d2", CK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CK_APMIXED_MMPLL, 1, 15),
+ PLL_FACTOR(CK_TOP_MMPLL_D4, "mmpll_d4", CK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CK_APMIXED_MMPLL, 1, 12),
+ PLL_FACTOR(CK_TOP_MMPLL_D8, "mmpll_d8", CK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
+ 1),
+ PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CK_TOP_NET1PLL_D4, "net1pll_d4", CK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CK_TOP_NET1PLL_D5, "net1pll_d5", CK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CK_TOP_NET1PLL_D8, "net1pll_d8", CK_APMIXED_NET1PLL, 1, 8),
+ PLL_FACTOR(CK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
+ PLL_FACTOR(CK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
+ PLL_FACTOR(CK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CK_APMIXED_NET1PLL, 1,
+ 128),
+ PLL_FACTOR(CK_TOP_NET2PLL_800M, "cb_net2pll_800m", CK_APMIXED_NET2PLL, 1,
+ 1),
+ PLL_FACTOR(CK_TOP_NET2PLL_D2, "net2pll_d2", CK_APMIXED_NET2PLL, 1, 2),
+ PLL_FACTOR(CK_TOP_NET2PLL_D4, "net2pll_d4", CK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
+ PLL_FACTOR(CK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
+ PLL_FACTOR(CK_TOP_NET2PLL_D6, "net2pll_d6", CK_APMIXED_NET2PLL, 1, 6),
+ PLL_FACTOR(CK_TOP_NET2PLL_D8, "net2pll_d8", CK_APMIXED_NET2PLL, 1, 8),
+ PLL_FACTOR(CK_TOP_CB_WEDMCUPLL_208M, "cb_wedmcupll_208m",
+ CK_APMIXED_WEDMCUPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_CB_NETSYSPLL_850M, "cb_netsyspll_850m",
+ CK_APMIXED_NETSYSPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_CB_MSDCPLL_400M, "cb_msdcpll_400m", CK_APMIXED_MSDCPLL, 1,
+ 1),
};
/* TOPCKGEN MUX PARENTS */
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 36a5f4818b2..47ea13c04b8 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -121,71 +121,71 @@
/* TOPCKGEN */
/* mtk_fixed_factor */
-#define CK_TOP_XTAL 0 /* Linux CLK ID (74) */
-#define CK_TOP_CB_MPLL_416M 1 /* Linux CLK ID (75) */
-#define CK_TOP_MPLL_D2 2 /* Linux CLK ID (76) */
-#define CK_TOP_MPLL_D3_D2 3 /* Linux CLK ID (77) */
-#define CK_TOP_MPLL_D4 4 /* Linux CLK ID (78) */
-#define CK_TOP_MPLL_D8 5 /* Linux CLK ID (79) */
-#define CK_TOP_MPLL_D8_D2 6 /* Linux CLK ID (80) */
-#define CK_TOP_CB_MMPLL_720M 7 /* Linux CLK ID (81) */
-#define CK_TOP_MMPLL_D2 8 /* Linux CLK ID (82) */
-#define CK_TOP_MMPLL_D3_D5 9 /* Linux CLK ID (83) */
-#define CK_TOP_MMPLL_D4 10 /* Linux CLK ID (84) */
-#define CK_TOP_MMPLL_D6_D2 11 /* Linux CLK ID (85) */
-#define CK_TOP_MMPLL_D8 12 /* Linux CLK ID (86) */
-#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */
-#define CK_TOP_APLL2_D4 14 /* Linux CLK ID (88) */
-#define CK_TOP_NET1PLL_D4 15 /* Linux CLK ID (89) */
-#define CK_TOP_NET1PLL_D5 16 /* Linux CLK ID (90) */
-#define CK_TOP_NET1PLL_D5_D2 17 /* Linux CLK ID (91) */
-#define CK_TOP_NET1PLL_D5_D4 18 /* Linux CLK ID (92) */
-#define CK_TOP_NET1PLL_D8 19 /* Linux CLK ID (93) */
-#define CK_TOP_NET1PLL_D8_D2 20 /* Linux CLK ID (94) */
-#define CK_TOP_NET1PLL_D8_D4 21 /* Linux CLK ID (95) */
-#define CK_TOP_NET1PLL_D8_D8 22 /* Linux CLK ID (96) */
-#define CK_TOP_NET1PLL_D8_D16 23 /* Linux CLK ID (97) */
-#define CK_TOP_CB_NET2PLL_800M 24 /* Linux CLK ID (98) */
-#define CK_TOP_NET2PLL_D2 25 /* Linux CLK ID (99) */
-#define CK_TOP_NET2PLL_D4 26 /* Linux CLK ID (100) */
-#define CK_TOP_NET2PLL_D4_D4 27 /* Linux CLK ID (101) */
-#define CK_TOP_NET2PLL_D4_D8 28 /* Linux CLK ID (102) */
-#define CK_TOP_NET2PLL_D6 29 /* Linux CLK ID (103) */
-#define CK_TOP_NET2PLL_D8 30 /* Linux CLK ID (104) */
-#define CK_TOP_CB_WEDMCUPLL_208M 31 /* Linux CLK ID (105) */
-#define CK_TOP_CB_SGMPLL_325M 32 /* Linux CLK ID (106) */
-#define CK_TOP_CB_NETSYSPLL_850M 33 /* Linux CLK ID (107) */
-#define CK_TOP_CB_MSDCPLL_400M 34 /* Linux CLK ID (108) */
-#define CK_TOP_XTAL_D2 35 /* Linux CLK ID (109) */
-#define CK_TOP_RTC_32K 36 /* Linux CLK ID (110) */
-#define CK_TOP_RTC_32P7K 37 /* Linux CLK ID (111) */
-#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */
-#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */
-#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */
-#define CK_TOP_NETSYS_GSW 41 /* Linux CLK ID (115) */
-#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */
-#define CK_TOP_EIP197 43 /* Linux CLK ID (117) */
-#define CK_TOP_EMMC_250M 44 /* Linux CLK ID (118) */
-#define CK_TOP_EMMC_400M 45 /* Linux CLK ID (119) */
-#define CK_TOP_SPI 46 /* Linux CLK ID (120) */
-#define CK_TOP_SPIM_MST 47 /* Linux CLK ID (121) */
-#define CK_TOP_NFI1X 48 /* Linux CLK ID (122) */
-#define CK_TOP_SPINFI_BCK 49 /* Linux CLK ID (123) */
-#define CK_TOP_I2C_BCK 50 /* Linux CLK ID (124) */
-#define CK_TOP_USB_SYS 51 /* Linux CLK ID (125) */
-#define CK_TOP_USB_SYS_P1 52 /* Linux CLK ID (126) */
-#define CK_TOP_USB_XHCI 53 /* Linux CLK ID (127) */
-#define CK_TOP_USB_XHCI_P1 54 /* Linux CLK ID (128) */
-#define CK_TOP_USB_FRMCNT 55 /* Linux CLK ID (129) */
-#define CK_TOP_USB_FRMCNT_P1 56 /* Linux CLK ID (130) */
-#define CK_TOP_AUD 57 /* Linux CLK ID (131) */
-#define CK_TOP_A1SYS 58 /* Linux CLK ID (132) */
-#define CK_TOP_AUD_L 59 /* Linux CLK ID (133) */
-#define CK_TOP_A_TUNER 60 /* Linux CLK ID (134) */
-#define CK_TOP_SYSAXI 61 /* Linux CLK ID (135) */
-#define CK_TOP_INFRA_F26M 62 /* Linux CLK ID (136) */
-#define CK_TOP_USB_REF 63 /* Linux CLK ID (137) */
-#define CK_TOP_USB_CK_P1 64 /* Linux CLK ID (138) */
+#define CK_TOP_XTAL_D2 0 /* Linux CLK ID (109) */
+#define CK_TOP_RTC_32K 1 /* Linux CLK ID (110) */
+#define CK_TOP_RTC_32P7K 2 /* Linux CLK ID (111) */
+#define CK_TOP_INFRA_F32K 3 /* Linux CLK ID (112) */
+#define CK_TOP_CKSQ_SRC 4 /* Linux CLK ID (113) */
+#define CK_TOP_NETSYS_2X 5 /* Linux CLK ID (114) */
+#define CK_TOP_NETSYS_GSW 6 /* Linux CLK ID (115) */
+#define CK_TOP_NETSYS_WED_MCU 7 /* Linux CLK ID (116) */
+#define CK_TOP_EIP197 8 /* Linux CLK ID (117) */
+#define CK_TOP_EMMC_250M 9 /* Linux CLK ID (118) */
+#define CK_TOP_EMMC_400M 10 /* Linux CLK ID (119) */
+#define CK_TOP_SPI 11 /* Linux CLK ID (120) */
+#define CK_TOP_SPIM_MST 12 /* Linux CLK ID (121) */
+#define CK_TOP_NFI1X 13 /* Linux CLK ID (122) */
+#define CK_TOP_SPINFI_BCK 14 /* Linux CLK ID (123) */
+#define CK_TOP_I2C_BCK 15 /* Linux CLK ID (124) */
+#define CK_TOP_USB_SYS 16 /* Linux CLK ID (125) */
+#define CK_TOP_USB_SYS_P1 17 /* Linux CLK ID (126) */
+#define CK_TOP_USB_XHCI 18 /* Linux CLK ID (127) */
+#define CK_TOP_USB_XHCI_P1 19 /* Linux CLK ID (128) */
+#define CK_TOP_USB_FRMCNT 20 /* Linux CLK ID (129) */
+#define CK_TOP_USB_FRMCNT_P1 21 /* Linux CLK ID (130) */
+#define CK_TOP_AUD 22 /* Linux CLK ID (131) */
+#define CK_TOP_A1SYS 23 /* Linux CLK ID (132) */
+#define CK_TOP_AUD_L 24 /* Linux CLK ID (133) */
+#define CK_TOP_A_TUNER 25 /* Linux CLK ID (134) */
+#define CK_TOP_SYSAXI 26 /* Linux CLK ID (135) */
+#define CK_TOP_INFRA_F26M 27 /* Linux CLK ID (136) */
+#define CK_TOP_USB_REF 28 /* Linux CLK ID (137) */
+#define CK_TOP_USB_CK_P1 29 /* Linux CLK ID (138) */
+#define CK_TOP_XTAL 30 /* Linux CLK ID (74) */
+#define CK_TOP_CB_MPLL_416M 31 /* Linux CLK ID (75) */
+#define CK_TOP_MPLL_D2 32 /* Linux CLK ID (76) */
+#define CK_TOP_MPLL_D3_D2 33 /* Linux CLK ID (77) */
+#define CK_TOP_MPLL_D4 35 /* Linux CLK ID (78) */
+#define CK_TOP_MPLL_D8 34 /* Linux CLK ID (79) */
+#define CK_TOP_MPLL_D8_D2 36 /* Linux CLK ID (80) */
+#define CK_TOP_CB_MMPLL_720M 37 /* Linux CLK ID (81) */
+#define CK_TOP_MMPLL_D2 38 /* Linux CLK ID (82) */
+#define CK_TOP_MMPLL_D3_D5 39 /* Linux CLK ID (83) */
+#define CK_TOP_MMPLL_D4 40 /* Linux CLK ID (84) */
+#define CK_TOP_MMPLL_D6_D2 41 /* Linux CLK ID (85) */
+#define CK_TOP_MMPLL_D8 42 /* Linux CLK ID (86) */
+#define CK_TOP_CB_APLL2_196M 43 /* Linux CLK ID (87) */
+#define CK_TOP_APLL2_D4 44 /* Linux CLK ID (88) */
+#define CK_TOP_NET1PLL_D4 45 /* Linux CLK ID (89) */
+#define CK_TOP_NET1PLL_D5 46 /* Linux CLK ID (90) */
+#define CK_TOP_NET1PLL_D5_D2 47 /* Linux CLK ID (91) */
+#define CK_TOP_NET1PLL_D5_D4 48 /* Linux CLK ID (92) */
+#define CK_TOP_NET1PLL_D8 49 /* Linux CLK ID (93) */
+#define CK_TOP_NET1PLL_D8_D2 50 /* Linux CLK ID (94) */
+#define CK_TOP_NET1PLL_D8_D4 51 /* Linux CLK ID (95) */
+#define CK_TOP_NET1PLL_D8_D8 52 /* Linux CLK ID (96) */
+#define CK_TOP_NET1PLL_D8_D16 53 /* Linux CLK ID (97) */
+#define CK_TOP_CB_NET2PLL_800M 54 /* Linux CLK ID (98) */
+#define CK_TOP_NET2PLL_D2 55 /* Linux CLK ID (99) */
+#define CK_TOP_NET2PLL_D4 56 /* Linux CLK ID (100) */
+#define CK_TOP_NET2PLL_D4_D4 57 /* Linux CLK ID (101) */
+#define CK_TOP_NET2PLL_D4_D8 58 /* Linux CLK ID (102) */
+#define CK_TOP_NET2PLL_D6 59 /* Linux CLK ID (103) */
+#define CK_TOP_NET2PLL_D8 60 /* Linux CLK ID (104) */
+#define CK_TOP_CB_WEDMCUPLL_208M 61 /* Linux CLK ID (105) */
+#define CK_TOP_CB_SGMPLL_325M 62 /* Linux CLK ID (106) */
+#define CK_TOP_CB_NETSYSPLL_850M 63 /* Linux CLK ID (107) */
+#define CK_TOP_CB_MSDCPLL_400M 64 /* Linux CLK ID (108) */
/* mtk_mux */
#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */
#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 09/13] clk: mediatek: mt7988: drop 1/1 spurious factor for topckgen
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (7 preceding siblings ...)
2024-08-03 8:32 ` [PATCH 08/13] clk: mediatek: mt7988: reorder TOPCKGEN factor ID Christian Marangi
@ 2024-08-03 8:32 ` Christian Marangi
2024-08-03 8:32 ` [PATCH 10/13] clk: mediatek: mt7988: comment out infracfg clk not defined Christian Marangi
` (4 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Now that we can have advanced parent handling for mux, we can drop
spurious topckgen 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7988.
Drop the factor entry from mt7988-clk.h and reference to them in
mt7988.dtsi. Muxes and gates are updated to reference the apmixed clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for apmixed and topckgen.
Also move TOP_XTAL to the fixed clock table following how it's done in
upstream linux kernel.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/mediatek/clk-mt7988.c | 412 +++++++++++++------------
include/dt-bindings/clock/mt7988-clk.h | 244 +++++++--------
2 files changed, 321 insertions(+), 335 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 24dc3299e11..4c94cda2b23 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -49,63 +49,28 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
};
+/* TOPCKGEN FIXED CLK */
+static const struct mtk_fixed_clk topckgen_mtk_fixed_clks[] = {
+ FIXED_CLK(CK_TOP_XTAL, CLK_XTAL, 40000000),
+};
+
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
- XTAL_FACTOR(CK_TOP_XTAL, "xtal", CLK_XTAL, 1, 1),
TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL, 1, 2),
TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
1250),
TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
1220),
- TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_RTC_32P7K, 1,
- 1),
- XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
- CK_TOP_NETSYS_MCU_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1",
- CK_TOP_USB_FRMCNT_P1_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL,
- 1, 1),
- TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1),
- TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MPLL_416M, "cb_mpll_416m", CK_APMIXED_MPLL, 1, 1),
PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
PLL_FACTOR(CK_TOP_MPLL_D3_D2, "mpll_d3_d2", CK_APMIXED_MPLL, 1, 2),
PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
PLL_FACTOR(CK_TOP_MPLL_D8, "mpll_d8", CK_APMIXED_MPLL, 1, 8),
PLL_FACTOR(CK_TOP_MPLL_D8_D2, "mpll_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_MMPLL_720M, "cb_mmpll_720m", CK_APMIXED_MMPLL, 1, 1),
PLL_FACTOR(CK_TOP_MMPLL_D2, "mmpll_d2", CK_APMIXED_MMPLL, 1, 2),
PLL_FACTOR(CK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CK_APMIXED_MMPLL, 1, 15),
PLL_FACTOR(CK_TOP_MMPLL_D4, "mmpll_d4", CK_APMIXED_MMPLL, 1, 4),
PLL_FACTOR(CK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CK_APMIXED_MMPLL, 1, 12),
PLL_FACTOR(CK_TOP_MMPLL_D8, "mmpll_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
- 1),
PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
PLL_FACTOR(CK_TOP_NET1PLL_D4, "net1pll_d4", CK_APMIXED_NET1PLL, 1, 4),
PLL_FACTOR(CK_TOP_NET1PLL_D5, "net1pll_d5", CK_APMIXED_NET1PLL, 1, 5),
@@ -117,143 +82,196 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
PLL_FACTOR(CK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
PLL_FACTOR(CK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CK_APMIXED_NET1PLL, 1,
128),
- PLL_FACTOR(CK_TOP_NET2PLL_800M, "cb_net2pll_800m", CK_APMIXED_NET2PLL, 1,
- 1),
PLL_FACTOR(CK_TOP_NET2PLL_D2, "net2pll_d2", CK_APMIXED_NET2PLL, 1, 2),
PLL_FACTOR(CK_TOP_NET2PLL_D4, "net2pll_d4", CK_APMIXED_NET2PLL, 1, 4),
PLL_FACTOR(CK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
PLL_FACTOR(CK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
PLL_FACTOR(CK_TOP_NET2PLL_D6, "net2pll_d6", CK_APMIXED_NET2PLL, 1, 6),
PLL_FACTOR(CK_TOP_NET2PLL_D8, "net2pll_d8", CK_APMIXED_NET2PLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_WEDMCUPLL_208M, "cb_wedmcupll_208m",
- CK_APMIXED_WEDMCUPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_NETSYSPLL_850M, "cb_netsyspll_850m",
- CK_APMIXED_NETSYSPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MSDCPLL_400M, "cb_msdcpll_400m", CK_APMIXED_MSDCPLL, 1,
- 1),
};
/* TOPCKGEN MUX PARENTS */
-static const int netsys_parents[] = { CK_TOP_XTAL, CK_TOP_NET2PLL_D2,
- CK_TOP_MMPLL_D2 };
+#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
-static const int netsys_500m_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET1PLL_D5,
- CK_TOP_NET1PLL_D5_D2 };
+static const struct mtk_parent netsys_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D2),
+ TOP_PARENT(CK_TOP_MMPLL_D2),
+};
-static const int netsys_2x_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET2PLL_800M,
- CK_TOP_CB_MMPLL_720M };
+static const struct mtk_parent netsys_500m_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5),
+ TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
+};
-static const int netsys_gsw_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D4,
- CK_TOP_NET1PLL_D5 };
+static const struct mtk_parent netsys_2x_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
+ APMIXED_PARENT(CK_APMIXED_MMPLL),
+};
-static const int eth_gmii_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D4 };
+static const struct mtk_parent netsys_gsw_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D4),
+ TOP_PARENT(CK_TOP_NET1PLL_D5),
+};
-static const int netsys_mcu_parents[] = {
- CK_TOP_XTAL, CK_TOP_NET2PLL_800M, CK_TOP_CB_MMPLL_720M,
- CK_TOP_NET1PLL_D4, CK_TOP_NET1PLL_D5, CK_TOP_CB_MPLL_416M
+static const struct mtk_parent eth_gmii_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
};
-static const int eip197_parents[] = {
- CK_TOP_XTAL, CK_TOP_CB_NETSYSPLL_850M, CK_TOP_NET2PLL_800M,
- CK_TOP_CB_MMPLL_720M, CK_TOP_NET1PLL_D4, CK_TOP_NET1PLL_D5
+static const struct mtk_parent netsys_mcu_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
+ APMIXED_PARENT(CK_APMIXED_MMPLL), TOP_PARENT(CK_TOP_NET1PLL_D4),
+ TOP_PARENT(CK_TOP_NET1PLL_D5), APMIXED_PARENT(CK_APMIXED_MPLL),
};
-static const int axi_infra_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET1PLL_D8_D2 };
+static const struct mtk_parent eip197_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NETSYSPLL),
+ APMIXED_PARENT(CK_APMIXED_NET2PLL), APMIXED_PARENT(CK_APMIXED_MMPLL),
+ TOP_PARENT(CK_TOP_NET1PLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D5),
+};
-static const int uart_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D8,
- CK_TOP_MPLL_D8_D2 };
+static const struct mtk_parent axi_infra_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
+};
-static const int emmc_250m_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D2,
- CK_TOP_MMPLL_D4 };
+static const struct mtk_parent uart_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D8),
+ TOP_PARENT(CK_TOP_MPLL_D8_D2),
+};
-static const int emmc_400m_parents[] = {
- CK_TOP_XTAL, CK_TOP_CB_MSDCPLL_400M, CK_TOP_MMPLL_D2,
- CK_TOP_MPLL_D2, CK_TOP_MMPLL_D4, CK_TOP_NET1PLL_D8_D2
+static const struct mtk_parent emmc_250m_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
+ TOP_PARENT(CK_TOP_MMPLL_D4),
};
-static const int spi_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D2,
- CK_TOP_MMPLL_D4, CK_TOP_NET1PLL_D8_D2,
- CK_TOP_NET2PLL_D6, CK_TOP_NET1PLL_D5_D4,
- CK_TOP_MPLL_D4, CK_TOP_NET1PLL_D8_D4 };
+static const struct mtk_parent emmc_400m_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_MSDCPLL),
+ TOP_PARENT(CK_TOP_MMPLL_D2), TOP_PARENT(CK_TOP_MPLL_D2),
+ TOP_PARENT(CK_TOP_MMPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
+};
-static const int nfi1x_parents[] = { CK_TOP_XTAL, CK_TOP_MMPLL_D4,
- CK_TOP_NET1PLL_D8_D2, CK_TOP_NET2PLL_D6,
- CK_TOP_MPLL_D4, CK_TOP_MMPLL_D8,
- CK_TOP_NET1PLL_D8_D4, CK_TOP_MPLL_D8 };
+static const struct mtk_parent spi_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
+ TOP_PARENT(CK_TOP_MMPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CK_TOP_NET2PLL_D6), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+};
-static const int spinfi_parents[] = { CK_TOP_XTAL_D2, CK_TOP_XTAL,
- CK_TOP_NET1PLL_D5_D4, CK_TOP_MPLL_D4,
- CK_TOP_MMPLL_D8, CK_TOP_NET1PLL_D8_D4,
- CK_TOP_MMPLL_D6_D2, CK_TOP_MPLL_D8 };
+static const struct mtk_parent nfi1x_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D4),
+ TOP_PARENT(CK_TOP_NET1PLL_D8_D2), TOP_PARENT(CK_TOP_NET2PLL_D6),
+ TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_MMPLL_D8),
+ TOP_PARENT(CK_TOP_NET1PLL_D8_D4), TOP_PARENT(CK_TOP_MPLL_D8),
+};
-static const int pwm_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D8_D2,
- CK_TOP_NET1PLL_D5_D4, CK_TOP_MPLL_D4,
- CK_TOP_MPLL_D8_D2, CK_TOP_RTC_32K };
+static const struct mtk_parent spinfi_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_XTAL),
+ TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
+ TOP_PARENT(CK_TOP_MMPLL_D8), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+ TOP_PARENT(CK_TOP_MMPLL_D6_D2), TOP_PARENT(CK_TOP_MPLL_D8),
+};
-static const int i2c_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D4,
- CK_TOP_MPLL_D4, CK_TOP_NET1PLL_D8_D4 };
+static const struct mtk_parent pwm_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
+ TOP_PARENT(CK_TOP_MPLL_D8_D2), TOP_PARENT(CK_TOP_RTC_32K),
+};
-static const int pcie_mbist_250m_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET1PLL_D5_D2 };
+static const struct mtk_parent i2c_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+};
-static const int pextp_tl_ck_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET2PLL_D6, CK_TOP_MMPLL_D8,
- CK_TOP_MPLL_D8_D2, CK_TOP_RTC_32K };
+static const struct mtk_parent pcie_mbist_250m_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
+};
+
+static const struct mtk_parent pextp_tl_ck_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D6),
+ TOP_PARENT(CK_TOP_MMPLL_D8), TOP_PARENT(CK_TOP_MPLL_D8_D2),
+ TOP_PARENT(CK_TOP_RTC_32K),
+};
-static const int usb_frmcnt_parents[] = { CK_TOP_XTAL,
- CK_TOP_MMPLL_D3_D5 };
+static const struct mtk_parent usb_frmcnt_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D3_D5),
+};
-static const int aud_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_196M };
+static const struct mtk_parent aud_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_APLL2),
+};
-static const int a1sys_parents[] = { CK_TOP_XTAL, CK_TOP_APLL2_D4 };
+static const struct mtk_parent a1sys_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_APLL2_D4),
+};
-static const int aud_l_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_196M,
- CK_TOP_MPLL_D8_D2 };
+static const struct mtk_parent aud_l_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_APLL2),
+ TOP_PARENT(CK_TOP_MPLL_D8_D2),
+};
-static const int sspxtp_parents[] = { CK_TOP_XTAL_D2, CK_TOP_MPLL_D8_D2 };
+static const struct mtk_parent sspxtp_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_MPLL_D8_D2),
+};
-static const int usxgmii_sbus_0_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET1PLL_D8_D4 };
+static const struct mtk_parent usxgmii_sbus_0_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+};
-static const int sgm_0_parents[] = { CK_TOP_XTAL, CK_TOP_CB_SGM_325M };
+static const struct mtk_parent sgm_0_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_SGMPLL),
+};
-static const int sysapb_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D3_D2 };
+static const struct mtk_parent sysapb_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D3_D2),
+};
-static const int eth_refck_50m_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET2PLL_D4_D4 };
+static const struct mtk_parent eth_refck_50m_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D4_D4),
+};
-static const int eth_sys_200m_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET2PLL_D4 };
+static const struct mtk_parent eth_sys_200m_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D4),
+};
-static const int eth_xgmii_parents[] = { CK_TOP_XTAL_D2, CK_TOP_NET1PLL_D8_D8,
- CK_TOP_NET1PLL_D8_D16 };
+static const struct mtk_parent eth_xgmii_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_NET1PLL_D8_D8),
+ TOP_PARENT(CK_TOP_NET1PLL_D8_D16),
+};
-static const int bus_tops_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5,
- CK_TOP_NET2PLL_D2 };
+static const struct mtk_parent bus_tops_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5),
+ TOP_PARENT(CK_TOP_NET2PLL_D2),
+};
-static const int npu_tops_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET2PLL_800M };
+static const struct mtk_parent npu_tops_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
+};
-static const int dramc_md32_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D2,
- CK_TOP_CB_WEDMCUPLL_208M };
+static const struct mtk_parent dramc_md32_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
+ APMIXED_PARENT(CK_APMIXED_WEDMCUPLL),
+};
-static const int da_xtp_glb_p0_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET2PLL_D8 };
+static const struct mtk_parent da_xtp_glb_p0_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D8),
+};
-static const int mcusys_backup_625m_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET1PLL_D4 };
+static const struct mtk_parent mcusys_backup_625m_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D4),
+};
-static const int macsec_parents[] = { CK_TOP_XTAL, CK_TOP_CB_SGM_325M,
- CK_TOP_NET1PLL_D8 };
+static const struct mtk_parent macsec_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_SGMPLL),
+ TOP_PARENT(CK_TOP_NET1PLL_D8),
+};
-static const int netsys_tops_400m_parents[] = { CK_TOP_XTAL,
- CK_TOP_NET2PLL_D2 };
+static const struct mtk_parent netsys_tops_400m_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D2),
+};
-static const int eth_mii_parents[] = { CK_TOP_XTAL_D2, CK_TOP_NET2PLL_D4_D8 };
+static const struct mtk_parent eth_mii_parents[] = {
+ TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_NET2PLL_D4_D8),
+};
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd) \
@@ -262,9 +280,9 @@ static const int eth_mii_parents[] = { CK_TOP_XTAL_D2, CK_TOP_NET2PLL_D4_D8 };
.mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
.upd_shift = _upd, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
- .gate_shift = _gate, .parent = _parents, \
+ .gate_shift = _gate, .parent_flags = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD, \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
/* TOPCKGEN MUX_GATE */
@@ -434,31 +452,31 @@ static const int infra_mux_uart1_parents[] = { CK_TOP_INFRA_F26M_SEL,
static const int infra_mux_uart2_parents[] = { CK_TOP_INFRA_F26M_SEL,
CK_TOP_UART_SEL };
-static const int infra_mux_spi0_parents[] = { CK_TOP_I2C_BCK, CK_TOP_SPI };
+static const int infra_mux_spi0_parents[] = { CK_TOP_I2C_SEL, CK_TOP_SPI_SEL };
-static const int infra_mux_spi1_parents[] = { CK_TOP_I2C_BCK, CK_TOP_SPIM_MST };
+static const int infra_mux_spi1_parents[] = { CK_TOP_I2C_SEL, CK_TOP_SPIM_MST_SEL };
-static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K,
- CK_TOP_INFRA_F26M_SEL, CK_TOP_SYSAXI,
+static const int infra_pwm_bck_parents[] = { CK_TOP_RTC_32P7K,
+ CK_TOP_INFRA_F26M_SEL, CK_TOP_SYSAXI_SEL,
CK_TOP_PWM_SEL };
static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
- CK_TOP_INFRA_F32K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
CK_TOP_PEXTP_TL_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
- CK_TOP_INFRA_F32K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
CK_TOP_PEXTP_TL_P1_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
- CK_TOP_INFRA_F32K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
CK_TOP_PEXTP_TL_P2_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
- CK_TOP_INFRA_F32K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
+ CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
CK_TOP_PEXTP_TL_P3_SEL
};
@@ -590,17 +608,17 @@ static const struct mtk_gate_regs infra_3_cg_regs = {
/* INFRA GATE */
static const struct mtk_gate infracfg_mtk_gates[] = {
GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P0,
- "infra_pcie_peri_ck_26m_ck_p0", CK_TOP_INFRA_F26M, 7),
+ "infra_pcie_peri_ck_26m_ck_p0", CK_TOP_INFRA_F26M_SEL, 7),
GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P1,
- "infra_pcie_peri_ck_26m_ck_p1", CK_TOP_INFRA_F26M, 8),
+ "infra_pcie_peri_ck_26m_ck_p1", CK_TOP_INFRA_F26M_SEL, 8),
GATE_INFRA0_INFRA(CK_INFRA_PCIE_PERI_26M_CK_P2,
"infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_PCIE_PERI_26M_CK_P3, 9),
GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P3,
- "infra_pcie_peri_ck_26m_ck_p3", CK_TOP_INFRA_F26M, 10),
+ "infra_pcie_peri_ck_26m_ck_p3", CK_TOP_INFRA_F26M_SEL, 10),
GATE_INFRA1_TOP(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
- CK_TOP_SYSAXI, 0),
+ CK_TOP_SYSAXI_SEL, 0),
GATE_INFRA1_TOP(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
- CK_TOP_SYSAXI, 1),
+ CK_TOP_SYSAXI_SEL, 1),
GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
CK_INFRA_PWM_SEL, 2),
GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
@@ -620,46 +638,46 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
CK_INFRA_PWM_CK8_SEL, 10),
GATE_INFRA1_TOP(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
- CK_TOP_SYSAXI, 12),
+ CK_TOP_SYSAXI_SEL, 12),
GATE_INFRA1_TOP(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
- CK_TOP_SYSAXI, 13),
+ CK_TOP_SYSAXI_SEL, 13),
GATE_INFRA1_TOP(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_TOP_INFRA_F26M_SEL, 14),
- GATE_INFRA1_TOP(CK_INFRA_AUD_L, "infra_f_faud_l", CK_TOP_AUD_L, 15),
- GATE_INFRA1_TOP(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_TOP_A1SYS,
+ GATE_INFRA1_TOP(CK_INFRA_AUD_L, "infra_f_faud_l", CK_TOP_AUD_L_SEL, 15),
+ GATE_INFRA1_TOP(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_TOP_A1SYS_SEL,
16),
- GATE_INFRA1_TOP(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_TOP_A_TUNER,
+ GATE_INFRA1_TOP(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_TOP_A_TUNER_SEL,
18),
GATE_INFRA1_TOP(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_TOP_INFRA_F26M_SEL,
19),
GATE_INFRA1_TOP(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
- CK_TOP_SYSAXI, 20),
+ CK_TOP_SYSAXI_SEL, 20),
GATE_INFRA1_TOP(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
- CK_TOP_SYSAXI, 21),
+ CK_TOP_SYSAXI_SEL, 21),
GATE_INFRA1_TOP(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
- CK_TOP_SYSAXI, 29),
+ CK_TOP_SYSAXI_SEL, 29),
GATE_INFRA1_TOP(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
CK_TOP_INFRA_F26M_SEL, 30),
- GATE_INFRA1_TOP(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_TOP_SYSAXI,
+ GATE_INFRA1_TOP(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_TOP_SYSAXI_SEL,
31),
GATE_INFRA2_TOP(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
CK_TOP_INFRA_F26M_SEL, 0),
- GATE_INFRA2_TOP(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_TOP_I2C_BCK, 1),
+ GATE_INFRA2_TOP(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_TOP_I2C_SEL, 1),
GATE_INFRA2_TOP(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
- CK_TOP_SYSAXI, 3),
+ CK_TOP_SYSAXI_SEL, 3),
GATE_INFRA2_TOP(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
- CK_TOP_SYSAXI, 4),
+ CK_TOP_SYSAXI_SEL, 4),
GATE_INFRA2_TOP(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
- CK_TOP_SYSAXI, 5),
+ CK_TOP_SYSAXI_SEL, 5),
GATE_INFRA2_INFRA(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
CK_INFRA_MUX_UART0_SEL, 3),
GATE_INFRA2_INFRA(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
CK_INFRA_MUX_UART1_SEL, 4),
GATE_INFRA2_INFRA(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
CK_INFRA_MUX_UART2_SEL, 5),
- GATE_INFRA2_TOP(CK_INFRA_NFI, "infra_f_fnfi", CK_TOP_NFI1X, 9),
- GATE_INFRA2_TOP(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_TOP_SPINFI_BCK, 10),
+ GATE_INFRA2_TOP(CK_INFRA_NFI, "infra_f_fnfi", CK_TOP_NFI1X_SEL, 9),
+ GATE_INFRA2_TOP(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_TOP_SPINFI_SEL, 10),
GATE_INFRA2_TOP(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
- CK_TOP_SYSAXI, 11),
+ CK_TOP_SYSAXI_SEL, 11),
GATE_INFRA2_INFRA(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
CK_INFRA_MUX_SPI0_SEL, 12),
GATE_INFRA2_INFRA(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
@@ -667,52 +685,52 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
GATE_INFRA2_INFRA(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
CK_INFRA_MUX_SPI2_SEL, 14),
GATE_INFRA2_TOP(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
- CK_TOP_SYSAXI, 15),
+ CK_TOP_SYSAXI_SEL, 15),
GATE_INFRA2_TOP(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
- CK_TOP_SYSAXI, 16),
+ CK_TOP_SYSAXI_SEL, 16),
GATE_INFRA2_TOP(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
- CK_TOP_SYSAXI, 17),
+ CK_TOP_SYSAXI_SEL, 17),
GATE_INFRA2_TOP(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
- CK_TOP_SYSAXI, 18),
+ CK_TOP_SYSAXI_SEL, 18),
GATE_INFRA2_TOP(CK_INFRA_RTC, "infra_f_frtc", CK_TOP_RTC_32K, 19),
GATE_INFRA2_TOP(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
- CK_TOP_INFRA_F26M, 20),
+ CK_TOP_INFRA_F26M_SEL, 20),
GATE_INFRA2_INFRA(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
21),
- GATE_INFRA2_TOP(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_TOP_EMMC_400M,
+ GATE_INFRA2_TOP(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_TOP_EMMC_400M_SEL,
22),
GATE_INFRA2_TOP(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
- CK_TOP_EMMC_250M, 23),
+ CK_TOP_EMMC_250M_SEL, 23),
GATE_INFRA2_TOP(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
- CK_TOP_SYSAXI, 24),
+ CK_TOP_SYSAXI_SEL, 24),
GATE_INFRA2_TOP(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
- CK_TOP_SYSAXI, 25),
+ CK_TOP_SYSAXI_SEL, 25),
GATE_INFRA2_TOP(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
- CK_TOP_SYSAXI, 26),
- GATE_INFRA2_TOP(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_TOP_NFI1X,
+ CK_TOP_SYSAXI_SEL, 26),
+ GATE_INFRA2_TOP(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_TOP_NFI1X_SEL,
27),
GATE_INFRA2_TOP(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
- CK_TOP_SYSAXI, 29),
+ CK_TOP_SYSAXI_SEL, 29),
GATE_INFRA2_TOP(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
- CK_TOP_SYSAXI, 31),
+ CK_TOP_SYSAXI_SEL, 31),
GATE_INFRA3_TOP(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
- CK_TOP_SYSAXI, 0),
+ CK_TOP_SYSAXI_SEL, 0),
GATE_INFRA3_TOP(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
- CK_TOP_SYSAXI, 1),
+ CK_TOP_SYSAXI_SEL, 1),
GATE_INFRA3_TOP(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
- CK_TOP_SYSAXI, 2),
+ CK_TOP_SYSAXI_SEL, 2),
GATE_INFRA3_TOP(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
- CK_TOP_SYSAXI, 3),
- GATE_INFRA3_TOP(CK_INFRA_USB_SYS, "infra_usb_sys", CK_TOP_USB_SYS, 4),
+ CK_TOP_SYSAXI_SEL, 3),
+ GATE_INFRA3_TOP(CK_INFRA_USB_SYS, "infra_usb_sys", CK_TOP_USB_SYS_SEL, 4),
GATE_INFRA3_TOP(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
- CK_TOP_USB_SYS_P1, 5),
- GATE_INFRA3_TOP(CK_INFRA_USB_REF, "infra_usb_ref", CK_TOP_USB_REF, 6),
- GATE_INFRA3_TOP(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_TOP_USB_CK_P1,
- 7),
+ CK_TOP_USB_SYS_P1_SEL, 5),
+ GATE_INFRA3_XTAL(CK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6),
+ GATE_INFRA3_XTAL(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL,
+ 7),
GATE_INFRA3_TOP(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
- CK_TOP_USB_FRMCNT, 8),
+ CK_TOP_USB_FRMCNT_SEL, 8),
GATE_INFRA3_TOP(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
- CK_TOP_USB_FRMCNT_P1, 9),
+ CK_TOP_USB_FRMCNT_P1_SEL, 9),
GATE_INFRA3_XTAL(CK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL,
10),
GATE_INFRA3_XTAL(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
@@ -721,10 +739,10 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
12),
GATE_INFRA3_XTAL(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
CLK_XTAL, 13),
- GATE_INFRA3_TOP(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_TOP_USB_XHCI,
+ GATE_INFRA3_TOP(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_TOP_USB_XHCI_SEL,
14),
GATE_INFRA3_TOP(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
- CK_TOP_USB_XHCI_P1, 15),
+ CK_TOP_USB_XHCI_P1_SEL, 15),
GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
@@ -742,27 +760,29 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
CLK_XTAL, 27),
GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
- CK_TOP_SYSAXI, 28),
+ CK_TOP_SYSAXI_SEL, 28),
GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
- CK_TOP_SYSAXI, 29),
+ CK_TOP_SYSAXI_SEL, 29),
GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
- CK_TOP_SYSAXI, 30),
+ CK_TOP_SYSAXI_SEL, 30),
GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
- CK_TOP_SYSAXI, 31),
+ CK_TOP_SYSAXI_SEL, 31),
};
static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
.fclks = apmixedsys_mtk_plls,
+ .flags = CLK_APMIXED,
.xtal_rate = 40 * MHZ,
};
static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
- .fdivs_offs = CK_TOP_XTAL,
+ .fdivs_offs = CK_TOP_XTAL_D2,
.muxes_offs = CK_TOP_NETSYS_SEL,
+ .fclks = topckgen_mtk_fixed_clks,
.fdivs = topckgen_mtk_fixed_factors,
.muxes = topckgen_mtk_muxes,
- .flags = CLK_BYPASS_XTAL,
+ .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
.xtal_rate = 40 * MHZ,
};
@@ -878,7 +898,7 @@ static const struct mtk_gate_regs ethdma_cg_regs = {
}
static const struct mtk_gate ethdma_mtk_gate[] = {
- GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6),
+ GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X_SEL, 6),
};
static int mt7988_ethdma_probe(struct udevice *dev)
@@ -1022,11 +1042,11 @@ static const struct mtk_gate_regs ethwarp_cg_regs = {
static const struct mtk_gate ethwarp_mtk_gate[] = {
GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
- CK_TOP_NETSYS_WED_MCU, 13),
+ CK_TOP_NETSYS_MCU_SEL, 13),
GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
- CK_TOP_NETSYS_WED_MCU, 14),
+ CK_TOP_NETSYS_MCU_SEL, 14),
GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
- CK_TOP_NETSYS_WED_MCU, 15),
+ CK_TOP_NETSYS_MCU_SEL, 15),
};
static int mt7988_ethwarp_probe(struct udevice *dev)
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 47ea13c04b8..b4b95a04087 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -120,147 +120,113 @@
#define CK_INFRA_133M_PCIE_CK_P3 (148 - GATE_OFFSET) /* Linux CLK ID (98) */
/* TOPCKGEN */
+/* mtk_fixed_clk */
+#define CK_TOP_XTAL 0 /* Linux CLK ID (109) */
/* mtk_fixed_factor */
-#define CK_TOP_XTAL_D2 0 /* Linux CLK ID (109) */
-#define CK_TOP_RTC_32K 1 /* Linux CLK ID (110) */
-#define CK_TOP_RTC_32P7K 2 /* Linux CLK ID (111) */
-#define CK_TOP_INFRA_F32K 3 /* Linux CLK ID (112) */
-#define CK_TOP_CKSQ_SRC 4 /* Linux CLK ID (113) */
-#define CK_TOP_NETSYS_2X 5 /* Linux CLK ID (114) */
-#define CK_TOP_NETSYS_GSW 6 /* Linux CLK ID (115) */
-#define CK_TOP_NETSYS_WED_MCU 7 /* Linux CLK ID (116) */
-#define CK_TOP_EIP197 8 /* Linux CLK ID (117) */
-#define CK_TOP_EMMC_250M 9 /* Linux CLK ID (118) */
-#define CK_TOP_EMMC_400M 10 /* Linux CLK ID (119) */
-#define CK_TOP_SPI 11 /* Linux CLK ID (120) */
-#define CK_TOP_SPIM_MST 12 /* Linux CLK ID (121) */
-#define CK_TOP_NFI1X 13 /* Linux CLK ID (122) */
-#define CK_TOP_SPINFI_BCK 14 /* Linux CLK ID (123) */
-#define CK_TOP_I2C_BCK 15 /* Linux CLK ID (124) */
-#define CK_TOP_USB_SYS 16 /* Linux CLK ID (125) */
-#define CK_TOP_USB_SYS_P1 17 /* Linux CLK ID (126) */
-#define CK_TOP_USB_XHCI 18 /* Linux CLK ID (127) */
-#define CK_TOP_USB_XHCI_P1 19 /* Linux CLK ID (128) */
-#define CK_TOP_USB_FRMCNT 20 /* Linux CLK ID (129) */
-#define CK_TOP_USB_FRMCNT_P1 21 /* Linux CLK ID (130) */
-#define CK_TOP_AUD 22 /* Linux CLK ID (131) */
-#define CK_TOP_A1SYS 23 /* Linux CLK ID (132) */
-#define CK_TOP_AUD_L 24 /* Linux CLK ID (133) */
-#define CK_TOP_A_TUNER 25 /* Linux CLK ID (134) */
-#define CK_TOP_SYSAXI 26 /* Linux CLK ID (135) */
-#define CK_TOP_INFRA_F26M 27 /* Linux CLK ID (136) */
-#define CK_TOP_USB_REF 28 /* Linux CLK ID (137) */
-#define CK_TOP_USB_CK_P1 29 /* Linux CLK ID (138) */
-#define CK_TOP_XTAL 30 /* Linux CLK ID (74) */
-#define CK_TOP_CB_MPLL_416M 31 /* Linux CLK ID (75) */
-#define CK_TOP_MPLL_D2 32 /* Linux CLK ID (76) */
-#define CK_TOP_MPLL_D3_D2 33 /* Linux CLK ID (77) */
-#define CK_TOP_MPLL_D4 35 /* Linux CLK ID (78) */
-#define CK_TOP_MPLL_D8 34 /* Linux CLK ID (79) */
-#define CK_TOP_MPLL_D8_D2 36 /* Linux CLK ID (80) */
-#define CK_TOP_CB_MMPLL_720M 37 /* Linux CLK ID (81) */
-#define CK_TOP_MMPLL_D2 38 /* Linux CLK ID (82) */
-#define CK_TOP_MMPLL_D3_D5 39 /* Linux CLK ID (83) */
-#define CK_TOP_MMPLL_D4 40 /* Linux CLK ID (84) */
-#define CK_TOP_MMPLL_D6_D2 41 /* Linux CLK ID (85) */
-#define CK_TOP_MMPLL_D8 42 /* Linux CLK ID (86) */
-#define CK_TOP_CB_APLL2_196M 43 /* Linux CLK ID (87) */
-#define CK_TOP_APLL2_D4 44 /* Linux CLK ID (88) */
-#define CK_TOP_NET1PLL_D4 45 /* Linux CLK ID (89) */
-#define CK_TOP_NET1PLL_D5 46 /* Linux CLK ID (90) */
-#define CK_TOP_NET1PLL_D5_D2 47 /* Linux CLK ID (91) */
-#define CK_TOP_NET1PLL_D5_D4 48 /* Linux CLK ID (92) */
-#define CK_TOP_NET1PLL_D8 49 /* Linux CLK ID (93) */
-#define CK_TOP_NET1PLL_D8_D2 50 /* Linux CLK ID (94) */
-#define CK_TOP_NET1PLL_D8_D4 51 /* Linux CLK ID (95) */
-#define CK_TOP_NET1PLL_D8_D8 52 /* Linux CLK ID (96) */
-#define CK_TOP_NET1PLL_D8_D16 53 /* Linux CLK ID (97) */
-#define CK_TOP_CB_NET2PLL_800M 54 /* Linux CLK ID (98) */
-#define CK_TOP_NET2PLL_D2 55 /* Linux CLK ID (99) */
-#define CK_TOP_NET2PLL_D4 56 /* Linux CLK ID (100) */
-#define CK_TOP_NET2PLL_D4_D4 57 /* Linux CLK ID (101) */
-#define CK_TOP_NET2PLL_D4_D8 58 /* Linux CLK ID (102) */
-#define CK_TOP_NET2PLL_D6 59 /* Linux CLK ID (103) */
-#define CK_TOP_NET2PLL_D8 60 /* Linux CLK ID (104) */
-#define CK_TOP_CB_WEDMCUPLL_208M 61 /* Linux CLK ID (105) */
-#define CK_TOP_CB_SGMPLL_325M 62 /* Linux CLK ID (106) */
-#define CK_TOP_CB_NETSYSPLL_850M 63 /* Linux CLK ID (107) */
-#define CK_TOP_CB_MSDCPLL_400M 64 /* Linux CLK ID (108) */
+#define CK_TOP_XTAL_D2 1 /* Linux CLK ID (109) */
+#define CK_TOP_RTC_32K 2 /* Linux CLK ID (110) */
+#define CK_TOP_RTC_32P7K 3 /* Linux CLK ID (111) */
+#define CK_TOP_MPLL_D2 4 /* Linux CLK ID (76) */
+#define CK_TOP_MPLL_D3_D2 5 /* Linux CLK ID (77) */
+#define CK_TOP_MPLL_D4 6 /* Linux CLK ID (78) */
+#define CK_TOP_MPLL_D8 7 /* Linux CLK ID (79) */
+#define CK_TOP_MPLL_D8_D2 8 /* Linux CLK ID (80) */
+#define CK_TOP_MMPLL_D2 9 /* Linux CLK ID (82) */
+#define CK_TOP_MMPLL_D3_D5 10 /* Linux CLK ID (83) */
+#define CK_TOP_MMPLL_D4 11 /* Linux CLK ID (84) */
+#define CK_TOP_MMPLL_D6_D2 12 /* Linux CLK ID (85) */
+#define CK_TOP_MMPLL_D8 13 /* Linux CLK ID (86) */
+#define CK_TOP_APLL2_D4 14 /* Linux CLK ID (88) */
+#define CK_TOP_NET1PLL_D4 15 /* Linux CLK ID (89) */
+#define CK_TOP_NET1PLL_D5 16 /* Linux CLK ID (90) */
+#define CK_TOP_NET1PLL_D5_D2 17 /* Linux CLK ID (91) */
+#define CK_TOP_NET1PLL_D5_D4 18 /* Linux CLK ID (92) */
+#define CK_TOP_NET1PLL_D8 19 /* Linux CLK ID (93) */
+#define CK_TOP_NET1PLL_D8_D2 20 /* Linux CLK ID (94) */
+#define CK_TOP_NET1PLL_D8_D4 21 /* Linux CLK ID (95) */
+#define CK_TOP_NET1PLL_D8_D8 22 /* Linux CLK ID (96) */
+#define CK_TOP_NET1PLL_D8_D16 23 /* Linux CLK ID (97) */
+#define CK_TOP_NET2PLL_D2 24 /* Linux CLK ID (99) */
+#define CK_TOP_NET2PLL_D4 25 /* Linux CLK ID (100) */
+#define CK_TOP_NET2PLL_D4_D4 26 /* Linux CLK ID (101) */
+#define CK_TOP_NET2PLL_D4_D8 27 /* Linux CLK ID (102) */
+#define CK_TOP_NET2PLL_D6 28 /* Linux CLK ID (103) */
+#define CK_TOP_NET2PLL_D8 29 /* Linux CLK ID (104) */
/* mtk_mux */
-#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */
-#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */
-#define CK_TOP_NETSYS_2X_SEL 67 /* Linux CLK ID (2) */
-#define CK_TOP_NETSYS_GSW_SEL 68 /* Linux CLK ID (3) */
-#define CK_TOP_ETH_GMII_SEL 69 /* Linux CLK ID (4) */
-#define CK_TOP_NETSYS_MCU_SEL 70 /* Linux CLK ID (5) */
-#define CK_TOP_NETSYS_PAO_2X_SEL 71 /* Linux CLK ID (6) */
-#define CK_TOP_EIP197_SEL 72 /* Linux CLK ID (7) */
-#define CK_TOP_AXI_INFRA_SEL 73 /* Linux CLK ID (8) */
-#define CK_TOP_UART_SEL 74 /* Linux CLK ID (9) */
-#define CK_TOP_EMMC_250M_SEL 75 /* Linux CLK ID (10) */
-#define CK_TOP_EMMC_400M_SEL 76 /* Linux CLK ID (11) */
-#define CK_TOP_SPI_SEL 77 /* Linux CLK ID (12) */
-#define CK_TOP_SPIM_MST_SEL 78 /* Linux CLK ID (13) */
-#define CK_TOP_NFI1X_SEL 79 /* Linux CLK ID (14) */
-#define CK_TOP_SPINFI_SEL 80 /* Linux CLK ID (15) */
-#define CK_TOP_PWM_SEL 81 /* Linux CLK ID (16) */
-#define CK_TOP_I2C_SEL 82 /* Linux CLK ID (17) */
-#define CK_TOP_PCIE_MBIST_250M_SEL 83 /* Linux CLK ID (18) */
-#define CK_TOP_PEXTP_TL_SEL 84 /* Linux CLK ID (19) */
-#define CK_TOP_PEXTP_TL_P1_SEL 85 /* Linux CLK ID (20) */
-#define CK_TOP_PEXTP_TL_P2_SEL 86 /* Linux CLK ID (21) */
-#define CK_TOP_PEXTP_TL_P3_SEL 87 /* Linux CLK ID (22) */
-#define CK_TOP_USB_SYS_SEL 88 /* Linux CLK ID (23) */
-#define CK_TOP_USB_SYS_P1_SEL 89 /* Linux CLK ID (24) */
-#define CK_TOP_USB_XHCI_SEL 90 /* Linux CLK ID (25) */
-#define CK_TOP_USB_XHCI_P1_SEL 91 /* Linux CLK ID (26) */
-#define CK_TOP_USB_FRMCNT_SEL 92 /* Linux CLK ID (27) */
-#define CK_TOP_USB_FRMCNT_P1_SEL 93 /* Linux CLK ID (28) */
-#define CK_TOP_AUD_SEL 94 /* Linux CLK ID (29) */
-#define CK_TOP_A1SYS_SEL 95 /* Linux CLK ID (30) */
-#define CK_TOP_AUD_L_SEL 96 /* Linux CLK ID (31) */
-#define CK_TOP_A_TUNER_SEL 97 /* Linux CLK ID (32) */
-#define CK_TOP_SSPXTP_SEL 98 /* Linux CLK ID (33) */
-#define CK_TOP_USB_PHY_SEL 99 /* Linux CLK ID (34) */
-#define CK_TOP_USXGMII_SBUS_0_SEL 100 /* Linux CLK ID (35) */
-#define CK_TOP_USXGMII_SBUS_1_SEL 101 /* Linux CLK ID (36) */
-#define CK_TOP_SGM_0_SEL 102 /* Linux CLK ID (37) */
-#define CK_TOP_SGM_SBUS_0_SEL 103 /* Linux CLK ID (38) */
-#define CK_TOP_SGM_1_SEL 104 /* Linux CLK ID (39) */
-#define CK_TOP_SGM_SBUS_1_SEL 105 /* Linux CLK ID (40) */
-#define CK_TOP_XFI_PHY_0_XTAL_SEL 106 /* Linux CLK ID (41) */
-#define CK_TOP_XFI_PHY_1_XTAL_SEL 107 /* Linux CLK ID (42) */
-#define CK_TOP_SYSAXI_SEL 108 /* Linux CLK ID (43) */
-#define CK_TOP_SYSAPB_SEL 109 /* Linux CLK ID (44) */
-#define CK_TOP_ETH_REFCK_50M_SEL 110 /* Linux CLK ID (45) */
-#define CK_TOP_ETH_SYS_200M_SEL 111 /* Linux CLK ID (46) */
-#define CK_TOP_ETH_SYS_SEL 112 /* Linux CLK ID (47) */
-#define CK_TOP_ETH_XGMII_SEL 113 /* Linux CLK ID (48) */
-#define CK_TOP_BUS_TOPS_SEL 114 /* Linux CLK ID (49) */
-#define CK_TOP_NPU_TOPS_SEL 115 /* Linux CLK ID (50) */
-#define CK_TOP_DRAMC_SEL 116 /* Linux CLK ID (51) */
-#define CK_TOP_DRAMC_MD32_SEL 117 /* Linux CLK ID (52) */
-#define CK_TOP_INFRA_F26M_SEL 118 /* Linux CLK ID (53) */
-#define CK_TOP_PEXTP_P0_SEL 119 /* Linux CLK ID (54) */
-#define CK_TOP_PEXTP_P1_SEL 120 /* Linux CLK ID (55) */
-#define CK_TOP_PEXTP_P2_SEL 121 /* Linux CLK ID (56) */
-#define CK_TOP_PEXTP_P3_SEL 122 /* Linux CLK ID (57) */
-#define CK_TOP_DA_XTP_GLB_P0_SEL 123 /* Linux CLK ID (58) */
-#define CK_TOP_DA_XTP_GLB_P1_SEL 124 /* Linux CLK ID (59) */
-#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */
-#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */
-#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */
-#define CK_TOP_DA_SEL 128 /* Linux CLK ID (63) */
-#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */
-#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */
-#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */
-#define CK_TOP_NETSYS_SYNC_250M_SEL 132 /* Linux CLK ID (67) */
-#define CK_TOP_MACSEC_SEL 133 /* Linux CLK ID (68) */
-#define CK_TOP_NETSYS_TOPS_400M_SEL 134 /* Linux CLK ID (69) */
-#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */
-#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */
-#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */
-#define CK_TOP_NPU_SEL 138 /* Linux CLK ID (73) */
+#define CK_TOP_NETSYS_SEL 30 /* Linux CLK ID (0) */
+#define CK_TOP_NETSYS_500M_SEL 31 /* Linux CLK ID (1) */
+#define CK_TOP_NETSYS_2X_SEL 32 /* Linux CLK ID (2) */
+#define CK_TOP_NETSYS_GSW_SEL 33 /* Linux CLK ID (3) */
+#define CK_TOP_ETH_GMII_SEL 34 /* Linux CLK ID (4) */
+#define CK_TOP_NETSYS_MCU_SEL 35 /* Linux CLK ID (5) */
+#define CK_TOP_NETSYS_PAO_2X_SEL 36 /* Linux CLK ID (6) */
+#define CK_TOP_EIP197_SEL 37 /* Linux CLK ID (7) */
+#define CK_TOP_AXI_INFRA_SEL 38 /* Linux CLK ID (8) */
+#define CK_TOP_UART_SEL 39 /* Linux CLK ID (9) */
+#define CK_TOP_EMMC_250M_SEL 40 /* Linux CLK ID (10) */
+#define CK_TOP_EMMC_400M_SEL 41 /* Linux CLK ID (11) */
+#define CK_TOP_SPI_SEL 42 /* Linux CLK ID (12) */
+#define CK_TOP_SPIM_MST_SEL 43 /* Linux CLK ID (13) */
+#define CK_TOP_NFI1X_SEL 44 /* Linux CLK ID (14) */
+#define CK_TOP_SPINFI_SEL 45 /* Linux CLK ID (15) */
+#define CK_TOP_PWM_SEL 46 /* Linux CLK ID (16) */
+#define CK_TOP_I2C_SEL 47 /* Linux CLK ID (17) */
+#define CK_TOP_PCIE_MBIST_250M_SEL 48 /* Linux CLK ID (18) */
+#define CK_TOP_PEXTP_TL_SEL 49 /* Linux CLK ID (19) */
+#define CK_TOP_PEXTP_TL_P1_SEL 50 /* Linux CLK ID (20) */
+#define CK_TOP_PEXTP_TL_P2_SEL 51 /* Linux CLK ID (21) */
+#define CK_TOP_PEXTP_TL_P3_SEL 52 /* Linux CLK ID (22) */
+#define CK_TOP_USB_SYS_SEL 53 /* Linux CLK ID (23) */
+#define CK_TOP_USB_SYS_P1_SEL 54 /* Linux CLK ID (24) */
+#define CK_TOP_USB_XHCI_SEL 55 /* Linux CLK ID (25) */
+#define CK_TOP_USB_XHCI_P1_SEL 56 /* Linux CLK ID (26) */
+#define CK_TOP_USB_FRMCNT_SEL 57 /* Linux CLK ID (27) */
+#define CK_TOP_USB_FRMCNT_P1_SEL 58 /* Linux CLK ID (28) */
+#define CK_TOP_AUD_SEL 59 /* Linux CLK ID (29) */
+#define CK_TOP_A1SYS_SEL 60 /* Linux CLK ID (30) */
+#define CK_TOP_AUD_L_SEL 61 /* Linux CLK ID (31) */
+#define CK_TOP_A_TUNER_SEL 62 /* Linux CLK ID (32) */
+#define CK_TOP_SSPXTP_SEL 63 /* Linux CLK ID (33) */
+#define CK_TOP_USB_PHY_SEL 64 /* Linux CLK ID (34) */
+#define CK_TOP_USXGMII_SBUS_0_SEL 65 /* Linux CLK ID (35) */
+#define CK_TOP_USXGMII_SBUS_1_SEL 66 /* Linux CLK ID (36) */
+#define CK_TOP_SGM_0_SEL 67 /* Linux CLK ID (37) */
+#define CK_TOP_SGM_SBUS_0_SEL 68 /* Linux CLK ID (38) */
+#define CK_TOP_SGM_1_SEL 69 /* Linux CLK ID (39) */
+#define CK_TOP_SGM_SBUS_1_SEL 70 /* Linux CLK ID (40) */
+#define CK_TOP_XFI_PHY_0_XTAL_SEL 71 /* Linux CLK ID (41) */
+#define CK_TOP_XFI_PHY_1_XTAL_SEL 72 /* Linux CLK ID (42) */
+#define CK_TOP_SYSAXI_SEL 73 /* Linux CLK ID (43) */
+#define CK_TOP_SYSAPB_SEL 74 /* Linux CLK ID (44) */
+#define CK_TOP_ETH_REFCK_50M_SEL 75 /* Linux CLK ID (45) */
+#define CK_TOP_ETH_SYS_200M_SEL 76 /* Linux CLK ID (46) */
+#define CK_TOP_ETH_SYS_SEL 77 /* Linux CLK ID (47) */
+#define CK_TOP_ETH_XGMII_SEL 78 /* Linux CLK ID (48) */
+#define CK_TOP_BUS_TOPS_SEL 79 /* Linux CLK ID (49) */
+#define CK_TOP_NPU_TOPS_SEL 80 /* Linux CLK ID (50) */
+#define CK_TOP_DRAMC_SEL 81 /* Linux CLK ID (51) */
+#define CK_TOP_DRAMC_MD32_SEL 82 /* Linux CLK ID (52) */
+#define CK_TOP_INFRA_F26M_SEL 83 /* Linux CLK ID (53) */
+#define CK_TOP_PEXTP_P0_SEL 84 /* Linux CLK ID (54) */
+#define CK_TOP_PEXTP_P1_SEL 85 /* Linux CLK ID (55) */
+#define CK_TOP_PEXTP_P2_SEL 86 /* Linux CLK ID (56) */
+#define CK_TOP_PEXTP_P3_SEL 87 /* Linux CLK ID (57) */
+#define CK_TOP_DA_XTP_GLB_P0_SEL 88 /* Linux CLK ID (58) */
+#define CK_TOP_DA_XTP_GLB_P1_SEL 89 /* Linux CLK ID (59) */
+#define CK_TOP_DA_XTP_GLB_P2_SEL 90 /* Linux CLK ID (60) */
+#define CK_TOP_DA_XTP_GLB_P3_SEL 91 /* Linux CLK ID (61) */
+#define CK_TOP_CKM_SEL 92 /* Linux CLK ID (62) */
+#define CK_TOP_DA_SEL 93 /* Linux CLK ID (63) */
+#define CK_TOP_PEXTP_SEL 94 /* Linux CLK ID (64) */
+#define CK_TOP_TOPS_P2_26M_SEL 95 /* Linux CLK ID (65) */
+#define CK_TOP_MCUSYS_BACKUP_625M_SEL 96 /* Linux CLK ID (66) */
+#define CK_TOP_NETSYS_SYNC_250M_SEL 97 /* Linux CLK ID (67) */
+#define CK_TOP_MACSEC_SEL 98 /* Linux CLK ID (68) */
+#define CK_TOP_NETSYS_TOPS_400M_SEL 99 /* Linux CLK ID (69) */
+#define CK_TOP_NETSYS_PPEFB_250M_SEL 100 /* Linux CLK ID (70) */
+#define CK_TOP_NETSYS_WARP_SEL 101 /* Linux CLK ID (71) */
+#define CK_TOP_ETH_MII_SEL 102 /* Linux CLK ID (72) */
+#define CK_TOP_NPU_SEL 103 /* Linux CLK ID (73) */
/* APMIXEDSYS */
/* mtk_pll_data */
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 10/13] clk: mediatek: mt7988: comment out infracfg clk not defined
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (8 preceding siblings ...)
2024-08-03 8:32 ` [PATCH 09/13] clk: mediatek: mt7988: drop 1/1 spurious factor for topckgen Christian Marangi
@ 2024-08-03 8:32 ` Christian Marangi
2024-08-03 8:33 ` [PATCH 11/13] clk: mediatek: mt7988: replace clock ID with upstream linux Christian Marangi
` (3 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:32 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Comment out infracfg clk not defined in upstream kernel linux clock ID
include. These clock are not used and can be safely commented. Keep them
just to have a reference of their existence.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/mediatek/clk-mt7988.c | 16 ++--
include/dt-bindings/clock/mt7988-clk.h | 116 ++++++++++++-------------
2 files changed, 66 insertions(+), 66 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 4c94cda2b23..b46ca9f4601 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -657,17 +657,17 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
CK_TOP_SYSAXI_SEL, 29),
GATE_INFRA1_TOP(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
CK_TOP_INFRA_F26M_SEL, 30),
- GATE_INFRA1_TOP(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_TOP_SYSAXI_SEL,
- 31),
+ /* GATE_INFRA1_TOP(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_TOP_SYSAXI_SEL,
+ 31), */
GATE_INFRA2_TOP(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
CK_TOP_INFRA_F26M_SEL, 0),
GATE_INFRA2_TOP(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_TOP_I2C_SEL, 1),
- GATE_INFRA2_TOP(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
- CK_TOP_SYSAXI_SEL, 3),
- GATE_INFRA2_TOP(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
- CK_TOP_SYSAXI_SEL, 4),
- GATE_INFRA2_TOP(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
- CK_TOP_SYSAXI_SEL, 5),
+ /* GATE_INFRA2_TOP(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
+ CK_TOP_SYSAXI_SEL, 3), */
+ /* GATE_INFRA2_TOP(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
+ CK_TOP_SYSAXI_SEL, 4), */
+ /* GATE_INFRA2_TOP(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
+ CK_TOP_SYSAXI_SEL, 5), */
GATE_INFRA2_INFRA(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
CK_INFRA_MUX_UART0_SEL, 3),
GATE_INFRA2_INFRA(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index b4b95a04087..653fd8f6d29 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -60,64 +60,64 @@
#define CK_INFRA_66M_AP_DMA_BCK (88 - GATE_OFFSET) /* Linux CLK ID (38) */
#define CK_INFRA_66M_SEJ_BCK (89 - GATE_OFFSET) /* Linux CLK ID (39) */
#define CK_INFRA_PRE_CK_SEJ_F13M (90 - GATE_OFFSET) /* Linux CLK ID (40) */
-#define CK_INFRA_66M_TRNG (91 - GATE_OFFSET) /* Linux CLK ID (41) */
-#define CK_INFRA_26M_THERM_SYSTEM (92 - GATE_OFFSET) /* Linux CLK ID (42) */
-#define CK_INFRA_I2C_BCK (93 - GATE_OFFSET) /* Linux CLK ID (43) */
-#define CK_INFRA_66M_UART0_PCK (94 - GATE_OFFSET) /* Linux CLK ID (44) */
-#define CK_INFRA_66M_UART1_PCK (95 - GATE_OFFSET) /* Linux CLK ID (45) */
-#define CK_INFRA_66M_UART2_PCK (96 - GATE_OFFSET) /* Linux CLK ID (46) */
-#define CK_INFRA_52M_UART0_CK (97 - GATE_OFFSET) /* Linux CLK ID (47) */
-#define CK_INFRA_52M_UART1_CK (98 - GATE_OFFSET) /* Linux CLK ID (48) */
-#define CK_INFRA_52M_UART2_CK (99 - GATE_OFFSET) /* Linux CLK ID (49) */
-#define CK_INFRA_NFI (100 - GATE_OFFSET) /* Linux CLK ID (50) */
-#define CK_INFRA_SPINFI (101 - GATE_OFFSET) /* Linux CLK ID (51) */
-#define CK_INFRA_66M_NFI_HCK (102 - GATE_OFFSET) /* Linux CLK ID (52) */
-#define CK_INFRA_104M_SPI0 (103 - GATE_OFFSET) /* Linux CLK ID (53) */
-#define CK_INFRA_104M_SPI1 (104 - GATE_OFFSET) /* Linux CLK ID (54) */
-#define CK_INFRA_104M_SPI2_BCK (105 - GATE_OFFSET) /* Linux CLK ID (55) */
-#define CK_INFRA_66M_SPI0_HCK (106 - GATE_OFFSET) /* Linux CLK ID (56) */
-#define CK_INFRA_66M_SPI1_HCK (107 - GATE_OFFSET) /* Linux CLK ID (57) */
-#define CK_INFRA_66M_SPI2_HCK (108 - GATE_OFFSET) /* Linux CLK ID (58) */
-#define CK_INFRA_66M_FLASHIF_AXI (109 - GATE_OFFSET) /* Linux CLK ID (59) */
-#define CK_INFRA_RTC (110 - GATE_OFFSET) /* Linux CLK ID (60) */
-#define CK_INFRA_26M_ADC_BCK (111 - GATE_OFFSET) /* Linux CLK ID (61) */
-#define CK_INFRA_RC_ADC (112 - GATE_OFFSET) /* Linux CLK ID (62) */
-#define CK_INFRA_MSDC400 (113 - GATE_OFFSET) /* Linux CLK ID (63) */
-#define CK_INFRA_MSDC2_HCK (114 - GATE_OFFSET) /* Linux CLK ID (64) */
-#define CK_INFRA_133M_MSDC_0_HCK (115 - GATE_OFFSET) /* Linux CLK ID (65) */
-#define CK_INFRA_66M_MSDC_0_HCK (116 - GATE_OFFSET) /* Linux CLK ID (66) */
-#define CK_INFRA_133M_CPUM_BCK (117 - GATE_OFFSET) /* Linux CLK ID (67) */
-#define CK_INFRA_BIST2FPC (118 - GATE_OFFSET) /* Linux CLK ID (68) */
-#define CK_INFRA_I2C_X16W_MCK_CK_P1 (119 - GATE_OFFSET) /* Linux CLK ID (69) */
-#define CK_INFRA_I2C_X16W_PCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (70) */
-#define CK_INFRA_133M_USB_HCK (121 - GATE_OFFSET) /* Linux CLK ID (71) */
-#define CK_INFRA_133M_USB_HCK_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (72) */
-#define CK_INFRA_66M_USB_HCK (123 - GATE_OFFSET) /* Linux CLK ID (73) */
-#define CK_INFRA_66M_USB_HCK_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (74) */
-#define CK_INFRA_USB_SYS (125 - GATE_OFFSET) /* Linux CLK ID (75) */
-#define CK_INFRA_USB_SYS_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (76) */
-#define CK_INFRA_USB_REF (127 - GATE_OFFSET) /* Linux CLK ID (77) */
-#define CK_INFRA_USB_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (78) */
-#define CK_INFRA_USB_FRMCNT (129 - GATE_OFFSET) /* Linux CLK ID (79) */
-#define CK_INFRA_USB_FRMCNT_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (80) */
-#define CK_INFRA_USB_PIPE (131 - GATE_OFFSET) /* Linux CLK ID (81) */
-#define CK_INFRA_USB_PIPE_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (82) */
-#define CK_INFRA_USB_UTMI (133 - GATE_OFFSET) /* Linux CLK ID (83) */
-#define CK_INFRA_USB_UTMI_CK_P1 (134 - GATE_OFFSET) /* Linux CLK ID (84) */
-#define CK_INFRA_USB_XHCI (135 - GATE_OFFSET) /* Linux CLK ID (85) */
-#define CK_INFRA_USB_XHCI_CK_P1 (136 - GATE_OFFSET) /* Linux CLK ID (86) */
-#define CK_INFRA_PCIE_GFMUX_TL_P0 (137 - GATE_OFFSET) /* Linux CLK ID (87) */
-#define CK_INFRA_PCIE_GFMUX_TL_P1 (138 - GATE_OFFSET) /* Linux CLK ID (88) */
-#define CK_INFRA_PCIE_GFMUX_TL_P2 (139 - GATE_OFFSET) /* Linux CLK ID (89) */
-#define CK_INFRA_PCIE_GFMUX_TL_P3 (140 - GATE_OFFSET) /* Linux CLK ID (90) */
-#define CK_INFRA_PCIE_PIPE_P0 (141 - GATE_OFFSET) /* Linux CLK ID (91) */
-#define CK_INFRA_PCIE_PIPE_P1 (142 - GATE_OFFSET) /* Linux CLK ID (92) */
-#define CK_INFRA_PCIE_PIPE_P2 (143 - GATE_OFFSET) /* Linux CLK ID (93) */
-#define CK_INFRA_PCIE_PIPE_P3 (144 - GATE_OFFSET) /* Linux CLK ID (94) */
-#define CK_INFRA_133M_PCIE_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (95) */
-#define CK_INFRA_133M_PCIE_CK_P1 (146 - GATE_OFFSET) /* Linux CLK ID (96) */
-#define CK_INFRA_133M_PCIE_CK_P2 (147 - GATE_OFFSET) /* Linux CLK ID (97) */
-#define CK_INFRA_133M_PCIE_CK_P3 (148 - GATE_OFFSET) /* Linux CLK ID (98) */
+/* #define CK_INFRA_66M_TRNG (91 - GATE_OFFSET) NOT DEFINED */
+#define CK_INFRA_26M_THERM_SYSTEM (91 - GATE_OFFSET) /* Linux CLK ID (42) */
+#define CK_INFRA_I2C_BCK (92 - GATE_OFFSET) /* Linux CLK ID (43) */
+/* #define CK_INFRA_66M_UART0_PCK (94 - GATE_OFFSET) NOT DEFINED */
+/* #define CK_INFRA_66M_UART1_PCK (95 - GATE_OFFSET) NOT DEFINED */
+/* #define CK_INFRA_66M_UART2_PCK (96 - GATE_OFFSET) NOT DEFINED */
+#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */
+#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */
+#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */
+#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */
+#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */
+#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */
+#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */
+#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */
+#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */
+#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */
+#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */
+#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */
+#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */
+#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */
+#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */
+#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */
+#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */
+#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */
+#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */
+#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */
+#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */
+#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */
+#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */
+#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */
+#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */
+#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */
+#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */
+#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */
+#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */
+#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */
+#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */
+#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */
+#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */
+#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */
+#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */
+#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */
+#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */
+#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */
+#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */
+#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */
+#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */
+#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */
+#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */
+#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */
+#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */
+#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */
+#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */
+#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */
+#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */
+#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */
+#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */
+#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */
/* TOPCKGEN */
/* mtk_fixed_clk */
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 11/13] clk: mediatek: mt7988: replace clock ID with upstream linux
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (9 preceding siblings ...)
2024-08-03 8:32 ` [PATCH 10/13] clk: mediatek: mt7988: comment out infracfg clk not defined Christian Marangi
@ 2024-08-03 8:33 ` Christian Marangi
2024-08-03 8:33 ` [PATCH 12/13] clk: mediatek: mt7988: convert to unified infracfg gates + muxes Christian Marangi
` (2 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:33 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Replace infracfg clk ID with upstream linux version.
The same format is used here with the factor first, then mux and then
gates.
To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.
Drop any comment that reference the clock ID as we now have a 1:1 match
with upstream kernel linux.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/mediatek/clk-mt7988.c | 1 +
include/dt-bindings/clock/mt7988-clk.h | 420 ++++++++++++-------------
2 files changed, 210 insertions(+), 211 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index b46ca9f4601..7ef03941e24 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -788,6 +788,7 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
.muxes_offs = CK_INFRA_MUX_UART0_SEL,
+ .gates_offs = CK_INFRA_PCIE_PERI_26M_CK_P0,
.muxes = infracfg_mtk_mux,
.flags = CLK_BYPASS_XTAL,
.xtal_rate = 40 * MHZ,
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 653fd8f6d29..7c64f5f3d03 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -9,224 +9,222 @@
#define _DT_BINDINGS_CLK_MT7988_H
/* INFRACFG_AO */
-#define GATE_OFFSET 65
/* mtk_mux */
-#define CK_INFRA_MUX_UART0_SEL 0 /* Linux CLK ID (0) */
-#define CK_INFRA_MUX_UART1_SEL 1 /* Linux CLK ID (1) */
-#define CK_INFRA_MUX_UART2_SEL 2 /* Linux CLK ID (2) */
-#define CK_INFRA_MUX_SPI0_SEL 3 /* Linux CLK ID (3) */
-#define CK_INFRA_MUX_SPI1_SEL 4 /* Linux CLK ID (4) */
-#define CK_INFRA_MUX_SPI2_SEL 5 /* Linux CLK ID (5) */
-#define CK_INFRA_PWM_SEL 6 /* Linux CLK ID (6) */
-#define CK_INFRA_PWM_CK1_SEL 7 /* Linux CLK ID (7) */
-#define CK_INFRA_PWM_CK2_SEL 8 /* Linux CLK ID (8) */
-#define CK_INFRA_PWM_CK3_SEL 9 /* Linux CLK ID (9) */
-#define CK_INFRA_PWM_CK4_SEL 10 /* Linux CLK ID (10) */
-#define CK_INFRA_PWM_CK5_SEL 11 /* Linux CLK ID (11) */
-#define CK_INFRA_PWM_CK6_SEL 12 /* Linux CLK ID (12) */
-#define CK_INFRA_PWM_CK7_SEL 13 /* Linux CLK ID (13) */
-#define CK_INFRA_PWM_CK8_SEL 14 /* Linux CLK ID (14) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 /* Linux CLK ID (15) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 /* Linux CLK ID (16) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 /* Linux CLK ID (17) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 /* Linux CLK ID (18) */
+#define CK_INFRA_MUX_UART0_SEL 0
+#define CK_INFRA_MUX_UART1_SEL 1
+#define CK_INFRA_MUX_UART2_SEL 2
+#define CK_INFRA_MUX_SPI0_SEL 3
+#define CK_INFRA_MUX_SPI1_SEL 4
+#define CK_INFRA_MUX_SPI2_SEL 5
+#define CK_INFRA_PWM_SEL 6
+#define CK_INFRA_PWM_CK1_SEL 7
+#define CK_INFRA_PWM_CK2_SEL 8
+#define CK_INFRA_PWM_CK3_SEL 9
+#define CK_INFRA_PWM_CK4_SEL 10
+#define CK_INFRA_PWM_CK5_SEL 11
+#define CK_INFRA_PWM_CK6_SEL 12
+#define CK_INFRA_PWM_CK7_SEL 13
+#define CK_INFRA_PWM_CK8_SEL 14
+#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
+#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
+#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
+#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
+
+/* INFRACFG */
/* mtk_gate */
-#define CK_INFRA_PCIE_PERI_26M_CK_P0 (65 - GATE_OFFSET) /* Linux CLK ID (99) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P1 \
- (66 - GATE_OFFSET) /* Linux CLK ID (100) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P2 \
- (67 - GATE_OFFSET) /* Linux CLK ID (101) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P3 \
- (68 - GATE_OFFSET) /* Linux CLK ID (102) */
-#define CK_INFRA_66M_GPT_BCK (69 - GATE_OFFSET) /* Linux CLK ID (19) */
-#define CK_INFRA_66M_PWM_HCK (70 - GATE_OFFSET) /* Linux CLK ID (20) */
-#define CK_INFRA_66M_PWM_BCK (71 - GATE_OFFSET) /* Linux CLK ID (21) */
-#define CK_INFRA_66M_PWM_CK1 (72 - GATE_OFFSET) /* Linux CLK ID (22) */
-#define CK_INFRA_66M_PWM_CK2 (73 - GATE_OFFSET) /* Linux CLK ID (23) */
-#define CK_INFRA_66M_PWM_CK3 (74 - GATE_OFFSET) /* Linux CLK ID (24) */
-#define CK_INFRA_66M_PWM_CK4 (75 - GATE_OFFSET) /* Linux CLK ID (25) */
-#define CK_INFRA_66M_PWM_CK5 (76 - GATE_OFFSET) /* Linux CLK ID (26) */
-#define CK_INFRA_66M_PWM_CK6 (77 - GATE_OFFSET) /* Linux CLK ID (27) */
-#define CK_INFRA_66M_PWM_CK7 (78 - GATE_OFFSET) /* Linux CLK ID (28) */
-#define CK_INFRA_66M_PWM_CK8 (79 - GATE_OFFSET) /* Linux CLK ID (29) */
-#define CK_INFRA_133M_CQDMA_BCK (80 - GATE_OFFSET) /* Linux CLK ID (30) */
-#define CK_INFRA_66M_AUD_SLV_BCK (81 - GATE_OFFSET) /* Linux CLK ID (31) */
-#define CK_INFRA_AUD_26M (82 - GATE_OFFSET) /* Linux CLK ID (32) */
-#define CK_INFRA_AUD_L (83 - GATE_OFFSET) /* Linux CLK ID (33) */
-#define CK_INFRA_AUD_AUD (84 - GATE_OFFSET) /* Linux CLK ID (34) */
-#define CK_INFRA_AUD_EG2 (85 - GATE_OFFSET) /* Linux CLK ID (35) */
-#define CK_INFRA_DRAMC_F26M (86 - GATE_OFFSET) /* Linux CLK ID (36) */
-#define CK_INFRA_133M_DBG_ACKM (87 - GATE_OFFSET) /* Linux CLK ID (37) */
-#define CK_INFRA_66M_AP_DMA_BCK (88 - GATE_OFFSET) /* Linux CLK ID (38) */
-#define CK_INFRA_66M_SEJ_BCK (89 - GATE_OFFSET) /* Linux CLK ID (39) */
-#define CK_INFRA_PRE_CK_SEJ_F13M (90 - GATE_OFFSET) /* Linux CLK ID (40) */
-/* #define CK_INFRA_66M_TRNG (91 - GATE_OFFSET) NOT DEFINED */
-#define CK_INFRA_26M_THERM_SYSTEM (91 - GATE_OFFSET) /* Linux CLK ID (42) */
-#define CK_INFRA_I2C_BCK (92 - GATE_OFFSET) /* Linux CLK ID (43) */
-/* #define CK_INFRA_66M_UART0_PCK (94 - GATE_OFFSET) NOT DEFINED */
-/* #define CK_INFRA_66M_UART1_PCK (95 - GATE_OFFSET) NOT DEFINED */
-/* #define CK_INFRA_66M_UART2_PCK (96 - GATE_OFFSET) NOT DEFINED */
-#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */
-#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */
-#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */
-#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */
-#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */
-#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */
-#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */
-#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */
-#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */
-#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */
-#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */
-#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */
-#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */
-#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */
-#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */
-#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */
-#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */
-#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */
-#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */
-#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */
-#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */
-#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */
-#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */
-#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */
-#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */
-#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */
-#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */
-#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */
-#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */
-#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */
-#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */
-#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */
-#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */
-#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */
-#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */
-#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */
-#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */
-#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */
-#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */
-#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */
-#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */
-#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */
-#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */
-#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */
-#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */
-#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */
-#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */
-#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */
-#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */
-#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */
-#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */
-#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */
+#define CK_INFRA_PCIE_PERI_26M_CK_P0 19
+#define CK_INFRA_PCIE_PERI_26M_CK_P1 20
+#define CK_INFRA_PCIE_PERI_26M_CK_P2 21
+#define CK_INFRA_PCIE_PERI_26M_CK_P3 22
+#define CK_INFRA_66M_GPT_BCK 23
+#define CK_INFRA_66M_PWM_HCK 24
+#define CK_INFRA_66M_PWM_BCK 25
+#define CK_INFRA_66M_PWM_CK1 26
+#define CK_INFRA_66M_PWM_CK2 27
+#define CK_INFRA_66M_PWM_CK3 28
+#define CK_INFRA_66M_PWM_CK4 29
+#define CK_INFRA_66M_PWM_CK5 30
+#define CK_INFRA_66M_PWM_CK6 31
+#define CK_INFRA_66M_PWM_CK7 32
+#define CK_INFRA_66M_PWM_CK8 33
+#define CK_INFRA_133M_CQDMA_BCK 34
+#define CK_INFRA_66M_AUD_SLV_BCK 35
+#define CK_INFRA_AUD_26M 36
+#define CK_INFRA_AUD_L 37
+#define CK_INFRA_AUD_AUD 38
+#define CK_INFRA_AUD_EG2 39
+#define CK_INFRA_DRAMC_F26M 40
+#define CK_INFRA_133M_DBG_ACKM 41
+#define CK_INFRA_66M_AP_DMA_BCK 42
+#define CK_INFRA_66M_SEJ_BCK 43
+#define CK_INFRA_PRE_CK_SEJ_F13M 44
+/* #define CK_INFRA_66M_TRNG 44 */
+#define CLK_INFRA_26M_THERM_SYSTEM 45
+#define CLK_INFRA_I2C_BCK 46
+/* #define CK_INFRA_66M_UART0_PCK 46 */
+/* #define CK_INFRA_66M_UART1_PCK 47 */
+/* #define CK_INFRA_66M_UART2_PCK 48 */
+#define CK_INFRA_52M_UART0_CK 47
+#define CK_INFRA_52M_UART1_CK 48
+#define CK_INFRA_52M_UART2_CK 49
+#define CK_INFRA_NFI 50
+#define CK_INFRA_SPINFI 51
+#define CK_INFRA_66M_NFI_HCK 52
+#define CK_INFRA_104M_SPI0 53
+#define CK_INFRA_104M_SPI1 54
+#define CK_INFRA_104M_SPI2_BCK 55
+#define CK_INFRA_66M_SPI0_HCK 56
+#define CK_INFRA_66M_SPI1_HCK 57
+#define CK_INFRA_66M_SPI2_HCK 58
+#define CK_INFRA_66M_FLASHIF_AXI 59
+#define CK_INFRA_RTC 60
+#define CK_INFRA_26M_ADC_BCK 61
+#define CK_INFRA_RC_ADC 62
+#define CK_INFRA_MSDC400 63
+#define CK_INFRA_MSDC2_HCK 64
+#define CK_INFRA_133M_MSDC_0_HCK 65
+#define CK_INFRA_66M_MSDC_0_HCK 66
+#define CK_INFRA_133M_CPUM_BCK 67
+#define CK_INFRA_BIST2FPC 68
+#define CK_INFRA_I2C_X16W_MCK_CK_P1 69
+#define CK_INFRA_I2C_X16W_PCK_CK_P1 70
+#define CK_INFRA_133M_USB_HCK 71
+#define CK_INFRA_133M_USB_HCK_CK_P1 72
+#define CK_INFRA_66M_USB_HCK 73
+#define CK_INFRA_66M_USB_HCK_CK_P1 74
+#define CK_INFRA_USB_SYS 75
+#define CK_INFRA_USB_SYS_CK_P1 76
+#define CK_INFRA_USB_REF 77
+#define CK_INFRA_USB_CK_P1 78
+#define CK_INFRA_USB_FRMCNT 79
+#define CK_INFRA_USB_FRMCNT_CK_P1 80
+#define CK_INFRA_USB_PIPE 81
+#define CK_INFRA_USB_PIPE_CK_P1 82
+#define CK_INFRA_USB_UTMI 83
+#define CK_INFRA_USB_UTMI_CK_P1 84
+#define CK_INFRA_USB_XHCI 85
+#define CK_INFRA_USB_XHCI_CK_P1 86
+#define CK_INFRA_PCIE_GFMUX_TL_P0 87
+#define CK_INFRA_PCIE_GFMUX_TL_P1 88
+#define CK_INFRA_PCIE_GFMUX_TL_P2 89
+#define CK_INFRA_PCIE_GFMUX_TL_P3 90
+#define CK_INFRA_PCIE_PIPE_P0 91
+#define CK_INFRA_PCIE_PIPE_P1 92
+#define CK_INFRA_PCIE_PIPE_P2 93
+#define CK_INFRA_PCIE_PIPE_P3 94
+#define CK_INFRA_133M_PCIE_CK_P0 95
+#define CK_INFRA_133M_PCIE_CK_P1 96
+#define CK_INFRA_133M_PCIE_CK_P2 97
+#define CK_INFRA_133M_PCIE_CK_P3 98
/* TOPCKGEN */
/* mtk_fixed_clk */
-#define CK_TOP_XTAL 0 /* Linux CLK ID (109) */
+#define CK_TOP_XTAL 0
/* mtk_fixed_factor */
-#define CK_TOP_XTAL_D2 1 /* Linux CLK ID (109) */
-#define CK_TOP_RTC_32K 2 /* Linux CLK ID (110) */
-#define CK_TOP_RTC_32P7K 3 /* Linux CLK ID (111) */
-#define CK_TOP_MPLL_D2 4 /* Linux CLK ID (76) */
-#define CK_TOP_MPLL_D3_D2 5 /* Linux CLK ID (77) */
-#define CK_TOP_MPLL_D4 6 /* Linux CLK ID (78) */
-#define CK_TOP_MPLL_D8 7 /* Linux CLK ID (79) */
-#define CK_TOP_MPLL_D8_D2 8 /* Linux CLK ID (80) */
-#define CK_TOP_MMPLL_D2 9 /* Linux CLK ID (82) */
-#define CK_TOP_MMPLL_D3_D5 10 /* Linux CLK ID (83) */
-#define CK_TOP_MMPLL_D4 11 /* Linux CLK ID (84) */
-#define CK_TOP_MMPLL_D6_D2 12 /* Linux CLK ID (85) */
-#define CK_TOP_MMPLL_D8 13 /* Linux CLK ID (86) */
-#define CK_TOP_APLL2_D4 14 /* Linux CLK ID (88) */
-#define CK_TOP_NET1PLL_D4 15 /* Linux CLK ID (89) */
-#define CK_TOP_NET1PLL_D5 16 /* Linux CLK ID (90) */
-#define CK_TOP_NET1PLL_D5_D2 17 /* Linux CLK ID (91) */
-#define CK_TOP_NET1PLL_D5_D4 18 /* Linux CLK ID (92) */
-#define CK_TOP_NET1PLL_D8 19 /* Linux CLK ID (93) */
-#define CK_TOP_NET1PLL_D8_D2 20 /* Linux CLK ID (94) */
-#define CK_TOP_NET1PLL_D8_D4 21 /* Linux CLK ID (95) */
-#define CK_TOP_NET1PLL_D8_D8 22 /* Linux CLK ID (96) */
-#define CK_TOP_NET1PLL_D8_D16 23 /* Linux CLK ID (97) */
-#define CK_TOP_NET2PLL_D2 24 /* Linux CLK ID (99) */
-#define CK_TOP_NET2PLL_D4 25 /* Linux CLK ID (100) */
-#define CK_TOP_NET2PLL_D4_D4 26 /* Linux CLK ID (101) */
-#define CK_TOP_NET2PLL_D4_D8 27 /* Linux CLK ID (102) */
-#define CK_TOP_NET2PLL_D6 28 /* Linux CLK ID (103) */
-#define CK_TOP_NET2PLL_D8 29 /* Linux CLK ID (104) */
+#define CK_TOP_XTAL_D2 1
+#define CK_TOP_RTC_32K 2
+#define CK_TOP_RTC_32P7K 3
+#define CK_TOP_MPLL_D2 4
+#define CK_TOP_MPLL_D3_D2 5
+#define CK_TOP_MPLL_D4 6
+#define CK_TOP_MPLL_D8 7
+#define CK_TOP_MPLL_D8_D2 8
+#define CK_TOP_MMPLL_D2 9
+#define CK_TOP_MMPLL_D3_D5 10
+#define CK_TOP_MMPLL_D4 11
+#define CK_TOP_MMPLL_D6_D2 12
+#define CK_TOP_MMPLL_D8 13
+#define CK_TOP_APLL2_D4 14
+#define CK_TOP_NET1PLL_D4 15
+#define CK_TOP_NET1PLL_D5 16
+#define CK_TOP_NET1PLL_D5_D2 17
+#define CK_TOP_NET1PLL_D5_D4 18
+#define CK_TOP_NET1PLL_D8 19
+#define CK_TOP_NET1PLL_D8_D2 20
+#define CK_TOP_NET1PLL_D8_D4 21
+#define CK_TOP_NET1PLL_D8_D8 22
+#define CK_TOP_NET1PLL_D8_D16 23
+#define CK_TOP_NET2PLL_D2 24
+#define CK_TOP_NET2PLL_D4 25
+#define CK_TOP_NET2PLL_D4_D4 26
+#define CK_TOP_NET2PLL_D4_D8 27
+#define CK_TOP_NET2PLL_D6 28
+#define CK_TOP_NET2PLL_D8 29
/* mtk_mux */
-#define CK_TOP_NETSYS_SEL 30 /* Linux CLK ID (0) */
-#define CK_TOP_NETSYS_500M_SEL 31 /* Linux CLK ID (1) */
-#define CK_TOP_NETSYS_2X_SEL 32 /* Linux CLK ID (2) */
-#define CK_TOP_NETSYS_GSW_SEL 33 /* Linux CLK ID (3) */
-#define CK_TOP_ETH_GMII_SEL 34 /* Linux CLK ID (4) */
-#define CK_TOP_NETSYS_MCU_SEL 35 /* Linux CLK ID (5) */
-#define CK_TOP_NETSYS_PAO_2X_SEL 36 /* Linux CLK ID (6) */
-#define CK_TOP_EIP197_SEL 37 /* Linux CLK ID (7) */
-#define CK_TOP_AXI_INFRA_SEL 38 /* Linux CLK ID (8) */
-#define CK_TOP_UART_SEL 39 /* Linux CLK ID (9) */
-#define CK_TOP_EMMC_250M_SEL 40 /* Linux CLK ID (10) */
-#define CK_TOP_EMMC_400M_SEL 41 /* Linux CLK ID (11) */
-#define CK_TOP_SPI_SEL 42 /* Linux CLK ID (12) */
-#define CK_TOP_SPIM_MST_SEL 43 /* Linux CLK ID (13) */
-#define CK_TOP_NFI1X_SEL 44 /* Linux CLK ID (14) */
-#define CK_TOP_SPINFI_SEL 45 /* Linux CLK ID (15) */
-#define CK_TOP_PWM_SEL 46 /* Linux CLK ID (16) */
-#define CK_TOP_I2C_SEL 47 /* Linux CLK ID (17) */
-#define CK_TOP_PCIE_MBIST_250M_SEL 48 /* Linux CLK ID (18) */
-#define CK_TOP_PEXTP_TL_SEL 49 /* Linux CLK ID (19) */
-#define CK_TOP_PEXTP_TL_P1_SEL 50 /* Linux CLK ID (20) */
-#define CK_TOP_PEXTP_TL_P2_SEL 51 /* Linux CLK ID (21) */
-#define CK_TOP_PEXTP_TL_P3_SEL 52 /* Linux CLK ID (22) */
-#define CK_TOP_USB_SYS_SEL 53 /* Linux CLK ID (23) */
-#define CK_TOP_USB_SYS_P1_SEL 54 /* Linux CLK ID (24) */
-#define CK_TOP_USB_XHCI_SEL 55 /* Linux CLK ID (25) */
-#define CK_TOP_USB_XHCI_P1_SEL 56 /* Linux CLK ID (26) */
-#define CK_TOP_USB_FRMCNT_SEL 57 /* Linux CLK ID (27) */
-#define CK_TOP_USB_FRMCNT_P1_SEL 58 /* Linux CLK ID (28) */
-#define CK_TOP_AUD_SEL 59 /* Linux CLK ID (29) */
-#define CK_TOP_A1SYS_SEL 60 /* Linux CLK ID (30) */
-#define CK_TOP_AUD_L_SEL 61 /* Linux CLK ID (31) */
-#define CK_TOP_A_TUNER_SEL 62 /* Linux CLK ID (32) */
-#define CK_TOP_SSPXTP_SEL 63 /* Linux CLK ID (33) */
-#define CK_TOP_USB_PHY_SEL 64 /* Linux CLK ID (34) */
-#define CK_TOP_USXGMII_SBUS_0_SEL 65 /* Linux CLK ID (35) */
-#define CK_TOP_USXGMII_SBUS_1_SEL 66 /* Linux CLK ID (36) */
-#define CK_TOP_SGM_0_SEL 67 /* Linux CLK ID (37) */
-#define CK_TOP_SGM_SBUS_0_SEL 68 /* Linux CLK ID (38) */
-#define CK_TOP_SGM_1_SEL 69 /* Linux CLK ID (39) */
-#define CK_TOP_SGM_SBUS_1_SEL 70 /* Linux CLK ID (40) */
-#define CK_TOP_XFI_PHY_0_XTAL_SEL 71 /* Linux CLK ID (41) */
-#define CK_TOP_XFI_PHY_1_XTAL_SEL 72 /* Linux CLK ID (42) */
-#define CK_TOP_SYSAXI_SEL 73 /* Linux CLK ID (43) */
-#define CK_TOP_SYSAPB_SEL 74 /* Linux CLK ID (44) */
-#define CK_TOP_ETH_REFCK_50M_SEL 75 /* Linux CLK ID (45) */
-#define CK_TOP_ETH_SYS_200M_SEL 76 /* Linux CLK ID (46) */
-#define CK_TOP_ETH_SYS_SEL 77 /* Linux CLK ID (47) */
-#define CK_TOP_ETH_XGMII_SEL 78 /* Linux CLK ID (48) */
-#define CK_TOP_BUS_TOPS_SEL 79 /* Linux CLK ID (49) */
-#define CK_TOP_NPU_TOPS_SEL 80 /* Linux CLK ID (50) */
-#define CK_TOP_DRAMC_SEL 81 /* Linux CLK ID (51) */
-#define CK_TOP_DRAMC_MD32_SEL 82 /* Linux CLK ID (52) */
-#define CK_TOP_INFRA_F26M_SEL 83 /* Linux CLK ID (53) */
-#define CK_TOP_PEXTP_P0_SEL 84 /* Linux CLK ID (54) */
-#define CK_TOP_PEXTP_P1_SEL 85 /* Linux CLK ID (55) */
-#define CK_TOP_PEXTP_P2_SEL 86 /* Linux CLK ID (56) */
-#define CK_TOP_PEXTP_P3_SEL 87 /* Linux CLK ID (57) */
-#define CK_TOP_DA_XTP_GLB_P0_SEL 88 /* Linux CLK ID (58) */
-#define CK_TOP_DA_XTP_GLB_P1_SEL 89 /* Linux CLK ID (59) */
-#define CK_TOP_DA_XTP_GLB_P2_SEL 90 /* Linux CLK ID (60) */
-#define CK_TOP_DA_XTP_GLB_P3_SEL 91 /* Linux CLK ID (61) */
-#define CK_TOP_CKM_SEL 92 /* Linux CLK ID (62) */
-#define CK_TOP_DA_SEL 93 /* Linux CLK ID (63) */
-#define CK_TOP_PEXTP_SEL 94 /* Linux CLK ID (64) */
-#define CK_TOP_TOPS_P2_26M_SEL 95 /* Linux CLK ID (65) */
-#define CK_TOP_MCUSYS_BACKUP_625M_SEL 96 /* Linux CLK ID (66) */
-#define CK_TOP_NETSYS_SYNC_250M_SEL 97 /* Linux CLK ID (67) */
-#define CK_TOP_MACSEC_SEL 98 /* Linux CLK ID (68) */
-#define CK_TOP_NETSYS_TOPS_400M_SEL 99 /* Linux CLK ID (69) */
-#define CK_TOP_NETSYS_PPEFB_250M_SEL 100 /* Linux CLK ID (70) */
-#define CK_TOP_NETSYS_WARP_SEL 101 /* Linux CLK ID (71) */
-#define CK_TOP_ETH_MII_SEL 102 /* Linux CLK ID (72) */
-#define CK_TOP_NPU_SEL 103 /* Linux CLK ID (73) */
+#define CK_TOP_NETSYS_SEL 30
+#define CK_TOP_NETSYS_500M_SEL 31
+#define CK_TOP_NETSYS_2X_SEL 32
+#define CK_TOP_NETSYS_GSW_SEL 33
+#define CK_TOP_ETH_GMII_SEL 34
+#define CK_TOP_NETSYS_MCU_SEL 35
+#define CK_TOP_NETSYS_PAO_2X_SEL 36
+#define CK_TOP_EIP197_SEL 37
+#define CK_TOP_AXI_INFRA_SEL 38
+#define CK_TOP_UART_SEL 39
+#define CK_TOP_EMMC_250M_SEL 40
+#define CK_TOP_EMMC_400M_SEL 41
+#define CK_TOP_SPI_SEL 42
+#define CK_TOP_SPIM_MST_SEL 43
+#define CK_TOP_NFI1X_SEL 44
+#define CK_TOP_SPINFI_SEL 45
+#define CK_TOP_PWM_SEL 46
+#define CK_TOP_I2C_SEL 47
+#define CK_TOP_PCIE_MBIST_250M_SEL 48
+#define CK_TOP_PEXTP_TL_SEL 49
+#define CK_TOP_PEXTP_TL_P1_SEL 50
+#define CK_TOP_PEXTP_TL_P2_SEL 51
+#define CK_TOP_PEXTP_TL_P3_SEL 52
+#define CK_TOP_USB_SYS_SEL 53
+#define CK_TOP_USB_SYS_P1_SEL 54
+#define CK_TOP_USB_XHCI_SEL 55
+#define CK_TOP_USB_XHCI_P1_SEL 56
+#define CK_TOP_USB_FRMCNT_SEL 57
+#define CK_TOP_USB_FRMCNT_P1_SEL 58
+#define CK_TOP_AUD_SEL 59
+#define CK_TOP_A1SYS_SEL 60
+#define CK_TOP_AUD_L_SEL 61
+#define CK_TOP_A_TUNER_SEL 62
+#define CK_TOP_SSPXTP_SEL 63
+#define CK_TOP_USB_PHY_SEL 64
+#define CK_TOP_USXGMII_SBUS_0_SEL 65
+#define CK_TOP_USXGMII_SBUS_1_SEL 66
+#define CK_TOP_SGM_0_SEL 67
+#define CK_TOP_SGM_SBUS_0_SEL 68
+#define CK_TOP_SGM_1_SEL 69
+#define CK_TOP_SGM_SBUS_1_SEL 70
+#define CK_TOP_XFI_PHY_0_XTAL_SEL 71
+#define CK_TOP_XFI_PHY_1_XTAL_SEL 72
+#define CK_TOP_SYSAXI_SEL 73
+#define CK_TOP_SYSAPB_SEL 74
+#define CK_TOP_ETH_REFCK_50M_SEL 75
+#define CK_TOP_ETH_SYS_200M_SEL 76
+#define CK_TOP_ETH_SYS_SEL 77
+#define CK_TOP_ETH_XGMII_SEL 78
+#define CK_TOP_BUS_TOPS_SEL 79
+#define CK_TOP_NPU_TOPS_SEL 80
+#define CK_TOP_DRAMC_SEL 81
+#define CK_TOP_DRAMC_MD32_SEL 82
+#define CK_TOP_INFRA_F26M_SEL 83
+#define CK_TOP_PEXTP_P0_SEL 84
+#define CK_TOP_PEXTP_P1_SEL 85
+#define CK_TOP_PEXTP_P2_SEL 86
+#define CK_TOP_PEXTP_P3_SEL 87
+#define CK_TOP_DA_XTP_GLB_P0_SEL 88
+#define CK_TOP_DA_XTP_GLB_P1_SEL 89
+#define CK_TOP_DA_XTP_GLB_P2_SEL 90
+#define CK_TOP_DA_XTP_GLB_P3_SEL 91
+#define CK_TOP_CKM_SEL 92
+#define CK_TOP_DA_SEL 93
+#define CK_TOP_PEXTP_SEL 94
+#define CK_TOP_TOPS_P2_26M_SEL 95
+#define CK_TOP_MCUSYS_BACKUP_625M_SEL 96
+#define CK_TOP_NETSYS_SYNC_250M_SEL 97
+#define CK_TOP_MACSEC_SEL 98
+#define CK_TOP_NETSYS_TOPS_400M_SEL 99
+#define CK_TOP_NETSYS_PPEFB_250M_SEL 100
+#define CK_TOP_NETSYS_WARP_SEL 101
+#define CK_TOP_ETH_MII_SEL 102
+#define CK_TOP_NPU_SEL 103
/* APMIXEDSYS */
/* mtk_pll_data */
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 12/13] clk: mediatek: mt7988: convert to unified infracfg gates + muxes
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (10 preceding siblings ...)
2024-08-03 8:33 ` [PATCH 11/13] clk: mediatek: mt7988: replace clock ID with upstream linux Christian Marangi
@ 2024-08-03 8:33 ` Christian Marangi
2024-08-03 8:33 ` [PATCH 13/13] clk: mediatek: mt7988: rename CK to CLK Christian Marangi
2024-08-20 0:29 ` [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Tom Rini
13 siblings, 0 replies; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:33 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Convert to infracfg gates + muxes implementation now that it's
supported.
Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm/dts/mt7988.dtsi | 67 ++++++++++++++-----------------
drivers/clk/mediatek/clk-mt7988.c | 24 +----------
2 files changed, 32 insertions(+), 59 deletions(-)
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index 10d5c2a33c3..4695e1db1ad 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -97,13 +97,6 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
- compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
- reg = <0 0x10001000 0 0x1000>;
- clock-parent = <&infracfg_ao>;
- #clock-cells = <1>;
- };
-
apmixedsys: apmixedsys@1001e000 {
compatible = "mediatek,mt7988-fixed-plls", "syscon";
reg = <0 0x1001e000 0 0x1000>;
@@ -251,7 +244,7 @@
#clock-cells = <1>;
};
- infracfg_ao: infracfg@10001000 {
+ infracfg: infracfg@10001000 {
compatible = "mediatek,mt7988-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
clock-parent = <&topckgen>;
@@ -262,9 +255,9 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000000 0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
+ clocks = <&infracfg CK_INFRA_52M_UART0_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
+ <&infracfg CK_INFRA_MUX_UART0_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
<&topckgen CK_TOP_UART_SEL>;
status = "disabled";
@@ -274,9 +267,9 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000100 0 0x100>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
+ clocks = <&infracfg CK_INFRA_52M_UART1_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
+ <&infracfg CK_INFRA_MUX_UART1_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
<&topckgen CK_TOP_UART_SEL>;
status = "disabled";
@@ -286,9 +279,9 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000200 0 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
+ clocks = <&infracfg CK_INFRA_52M_UART2_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
+ <&infracfg CK_INFRA_MUX_UART2_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
<&topckgen CK_TOP_UART_SEL>;
status = "disabled";
@@ -301,8 +294,8 @@
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CK_INFRA_I2C_BCK>,
+ <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -316,8 +309,8 @@
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CK_INFRA_I2C_BCK>,
+ <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -331,8 +324,8 @@
<0 0x10217180 0 0x80>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CK_INFRA_I2C_BCK>,
+ <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -343,16 +336,16 @@
compatible = "mediatek,mt7988-pwm";
reg = <0 0x10048000 0 0x1000>;
#pwm-cells = <2>;
- clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
- <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
+ clocks = <&infracfg CK_INFRA_66M_PWM_BCK>,
+ <&infracfg CK_INFRA_66M_PWM_HCK>,
+ <&infracfg CK_INFRA_66M_PWM_CK1>,
+ <&infracfg CK_INFRA_66M_PWM_CK2>,
+ <&infracfg CK_INFRA_66M_PWM_CK3>,
+ <&infracfg CK_INFRA_66M_PWM_CK4>,
+ <&infracfg CK_INFRA_66M_PWM_CK5>,
+ <&infracfg CK_INFRA_66M_PWM_CK6>,
+ <&infracfg CK_INFRA_66M_PWM_CK7>,
+ <&infracfg CK_INFRA_66M_PWM_CK8>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
"pwm4","pwm5","pwm6","pwm7","pwm8";
status = "disabled";
@@ -365,9 +358,9 @@
<0 0x11002000 0 0x1000>;
reg-names = "nfi", "ecc";
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_SPINFI>,
- <&infracfg_ao CK_INFRA_NFI>,
- <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
+ clocks = <&infracfg CK_INFRA_SPINFI>,
+ <&infracfg CK_INFRA_NFI>,
+ <&infracfg CK_INFRA_66M_NFI_HCK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
<&topckgen CK_TOP_NFI1X_SEL>;
@@ -408,10 +401,10 @@
"mediatek,mt7986-mmc";
reg = <0 0x11230000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
- <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
- <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
- <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
+ clocks = <&infracfg CK_INFRA_MSDC400>,
+ <&infracfg CK_INFRA_MSDC2_HCK>,
+ <&infracfg CK_INFRA_133M_MSDC_0_HCK>,
+ <&infracfg CK_INFRA_66M_MSDC_0_HCK>;
clock-names = "source", "hclk", "source_cg", "axi_cg";
status = "disabled";
};
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 7ef03941e24..a8d278816bb 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -790,6 +790,7 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
.muxes_offs = CK_INFRA_MUX_UART0_SEL,
.gates_offs = CK_INFRA_PCIE_PERI_26M_CK_P0,
.muxes = infracfg_mtk_mux,
+ .gates = infracfg_mtk_gates,
.flags = CLK_BYPASS_XTAL,
.xtal_rate = 40 * MHZ,
};
@@ -847,20 +848,9 @@ static const struct udevice_id mt7988_infracfg_compat[] = {
{}
};
-static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = {
- { .compatible = "mediatek,mt7988-infracfg_ao_cgs" },
- {}
-};
-
static int mt7988_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
-}
-
-static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev)
-{
- return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree,
- infracfg_mtk_gates);
+ return mtk_common_clk_infrasys_init(dev, &mt7988_infracfg_clk_tree);
}
U_BOOT_DRIVER(mtk_clk_infracfg) = {
@@ -873,16 +863,6 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
.flags = DM_FLAG_PRE_RELOC,
};
-U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = {
- .name = "mt7988-clock-infracfg_ao_cgs",
- .id = UCLASS_CLK,
- .of_match = mt7988_infracfg_ao_cgs_compat,
- .probe = mt7988_infracfg_ao_cgs_probe,
- .priv_auto = sizeof(struct mtk_cg_priv),
- .ops = &mtk_clk_gate_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
-
/* ETHDMA */
static const struct mtk_gate_regs ethdma_cg_regs = {
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 13/13] clk: mediatek: mt7988: rename CK to CLK
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (11 preceding siblings ...)
2024-08-03 8:33 ` [PATCH 12/13] clk: mediatek: mt7988: convert to unified infracfg gates + muxes Christian Marangi
@ 2024-08-03 8:33 ` Christian Marangi
2024-08-10 18:46 ` Aw: " Frank Wunderlich
2024-08-20 0:29 ` [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Tom Rini
13 siblings, 1 reply; 16+ messages in thread
From: Christian Marangi @ 2024-08-03 8:33 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Frank Wunderlich, Dong Huang, u-boot
Rename each entry from CK to CLK to match the include in upstream kernel
linux.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm/dts/mt7988.dtsi | 84 +--
drivers/clk/mediatek/clk-mt7988.c | 768 ++++++++++++-------------
include/dt-bindings/clock/mt7988-clk.h | 450 +++++++--------
3 files changed, 651 insertions(+), 651 deletions(-)
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index 4695e1db1ad..e120e5084ce 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -255,11 +255,11 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000000 0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_52M_UART0_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg CK_INFRA_MUX_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
- <&topckgen CK_TOP_UART_SEL>;
+ clocks = <&infracfg CLK_INFRA_52M_UART0_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
@@ -267,11 +267,11 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000100 0 0x100>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_52M_UART1_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg CK_INFRA_MUX_UART1_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
- <&topckgen CK_TOP_UART_SEL>;
+ clocks = <&infracfg CLK_INFRA_52M_UART1_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
@@ -279,11 +279,11 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000200 0 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_52M_UART2_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg CK_INFRA_MUX_UART2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
- <&topckgen CK_TOP_UART_SEL>;
+ clocks = <&infracfg CLK_INFRA_52M_UART2_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
@@ -294,8 +294,8 @@
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg CK_INFRA_I2C_BCK>,
- <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -309,8 +309,8 @@
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg CK_INFRA_I2C_BCK>,
- <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -324,8 +324,8 @@
<0 0x10217180 0 0x80>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg CK_INFRA_I2C_BCK>,
- <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -336,16 +336,16 @@
compatible = "mediatek,mt7988-pwm";
reg = <0 0x10048000 0 0x1000>;
#pwm-cells = <2>;
- clocks = <&infracfg CK_INFRA_66M_PWM_BCK>,
- <&infracfg CK_INFRA_66M_PWM_HCK>,
- <&infracfg CK_INFRA_66M_PWM_CK1>,
- <&infracfg CK_INFRA_66M_PWM_CK2>,
- <&infracfg CK_INFRA_66M_PWM_CK3>,
- <&infracfg CK_INFRA_66M_PWM_CK4>,
- <&infracfg CK_INFRA_66M_PWM_CK5>,
- <&infracfg CK_INFRA_66M_PWM_CK6>,
- <&infracfg CK_INFRA_66M_PWM_CK7>,
- <&infracfg CK_INFRA_66M_PWM_CK8>;
+ clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
+ <&infracfg CLK_INFRA_66M_PWM_HCK>,
+ <&infracfg CLK_INFRA_66M_PWM_CK1>,
+ <&infracfg CLK_INFRA_66M_PWM_CK2>,
+ <&infracfg CLK_INFRA_66M_PWM_CK3>,
+ <&infracfg CLK_INFRA_66M_PWM_CK4>,
+ <&infracfg CLK_INFRA_66M_PWM_CK5>,
+ <&infracfg CLK_INFRA_66M_PWM_CK6>,
+ <&infracfg CLK_INFRA_66M_PWM_CK7>,
+ <&infracfg CLK_INFRA_66M_PWM_CK8>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
"pwm4","pwm5","pwm6","pwm7","pwm8";
status = "disabled";
@@ -358,14 +358,14 @@
<0 0x11002000 0 0x1000>;
reg-names = "nfi", "ecc";
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_SPINFI>,
- <&infracfg CK_INFRA_NFI>,
- <&infracfg CK_INFRA_66M_NFI_HCK>;
+ clocks = <&infracfg CLK_INFRA_SPINFI>,
+ <&infracfg CLK_INFRA_NFI>,
+ <&infracfg CLK_INFRA_66M_NFI_HCK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_MPLL_D8>,
- <&topckgen CK_TOP_MPLL_D8>;
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
+ <&topckgen CLK_TOP_MPLL_D8>;
status = "disabled";
};
@@ -401,10 +401,10 @@
"mediatek,mt7986-mmc";
reg = <0 0x11230000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_MSDC400>,
- <&infracfg CK_INFRA_MSDC2_HCK>,
- <&infracfg CK_INFRA_133M_MSDC_0_HCK>,
- <&infracfg CK_INFRA_66M_MSDC_0_HCK>;
+ clocks = <&infracfg CLK_INFRA_MSDC400>,
+ <&infracfg CLK_INFRA_MSDC2_HCK>,
+ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
+ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
clock-names = "source", "hclk", "source_cg", "axi_cg";
status = "disabled";
};
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index a8d278816bb..8f4e8f4e8c9 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -35,59 +35,59 @@
/* FIXED PLLS */
static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
- FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
- FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
- FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
- FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
- FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
- FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
- FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
- FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
- FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
- FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
- FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
- FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
+ FIXED_CLK(CLK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
+ FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
+ FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),
+ FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
+ FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+ FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+ FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
+ FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+ FIXED_CLK(CLK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
+ FIXED_CLK(CLK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
+ FIXED_CLK(CLK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
+ FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
};
/* TOPCKGEN FIXED CLK */
static const struct mtk_fixed_clk topckgen_mtk_fixed_clks[] = {
- FIXED_CLK(CK_TOP_XTAL, CLK_XTAL, 40000000),
+ FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),
};
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
- TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL, 1, 2),
- TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
+ TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL, 1, 2),
+ TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1,
1250),
- TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
+ TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1,
1220),
- PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_MPLL_D3_D2, "mpll_d3_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
- PLL_FACTOR(CK_TOP_MPLL_D8, "mpll_d8", CK_APMIXED_MPLL, 1, 8),
- PLL_FACTOR(CK_TOP_MPLL_D8_D2, "mpll_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_MMPLL_D2, "mmpll_d2", CK_APMIXED_MMPLL, 1, 2),
- PLL_FACTOR(CK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CK_APMIXED_MMPLL, 1, 15),
- PLL_FACTOR(CK_TOP_MMPLL_D4, "mmpll_d4", CK_APMIXED_MMPLL, 1, 4),
- PLL_FACTOR(CK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CK_APMIXED_MMPLL, 1, 12),
- PLL_FACTOR(CK_TOP_MMPLL_D8, "mmpll_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
- PLL_FACTOR(CK_TOP_NET1PLL_D4, "net1pll_d4", CK_APMIXED_NET1PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET1PLL_D5, "net1pll_d5", CK_APMIXED_NET1PLL, 1, 5),
- PLL_FACTOR(CK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
- PLL_FACTOR(CK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
- PLL_FACTOR(CK_TOP_NET1PLL_D8, "net1pll_d8", CK_APMIXED_NET1PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
- PLL_FACTOR(CK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
- PLL_FACTOR(CK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CK_APMIXED_NET1PLL, 1,
+ PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CLK_APMIXED_MMPLL, 1, 15),
+ PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CLK_APMIXED_MMPLL, 1, 12),
+ PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", CLK_APMIXED_NET1PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CLK_APMIXED_NET1PLL, 1, 64),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CLK_APMIXED_NET1PLL, 1,
128),
- PLL_FACTOR(CK_TOP_NET2PLL_D2, "net2pll_d2", CK_APMIXED_NET2PLL, 1, 2),
- PLL_FACTOR(CK_TOP_NET2PLL_D4, "net2pll_d4", CK_APMIXED_NET2PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
- PLL_FACTOR(CK_TOP_NET2PLL_D6, "net2pll_d6", CK_APMIXED_NET2PLL, 1, 6),
- PLL_FACTOR(CK_TOP_NET2PLL_D8, "net2pll_d8", CK_APMIXED_NET2PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", CLK_APMIXED_NET2PLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CLK_APMIXED_NET2PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CLK_APMIXED_NET2PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", CLK_APMIXED_NET2PLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", CLK_APMIXED_NET2PLL, 1, 8),
};
/* TOPCKGEN MUX PARENTS */
@@ -95,182 +95,182 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
static const struct mtk_parent netsys_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D2),
- TOP_PARENT(CK_TOP_MMPLL_D2),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D2),
};
static const struct mtk_parent netsys_500m_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5),
- TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
};
static const struct mtk_parent netsys_2x_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
- APMIXED_PARENT(CK_APMIXED_MMPLL),
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+ APMIXED_PARENT(CLK_APMIXED_MMPLL),
};
static const struct mtk_parent netsys_gsw_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D4),
- TOP_PARENT(CK_TOP_NET1PLL_D5),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5),
};
static const struct mtk_parent eth_gmii_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
};
static const struct mtk_parent netsys_mcu_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
- APMIXED_PARENT(CK_APMIXED_MMPLL), TOP_PARENT(CK_TOP_NET1PLL_D4),
- TOP_PARENT(CK_TOP_NET1PLL_D5), APMIXED_PARENT(CK_APMIXED_MPLL),
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+ APMIXED_PARENT(CLK_APMIXED_MMPLL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5), APMIXED_PARENT(CLK_APMIXED_MPLL),
};
static const struct mtk_parent eip197_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NETSYSPLL),
- APMIXED_PARENT(CK_APMIXED_NET2PLL), APMIXED_PARENT(CK_APMIXED_MMPLL),
- TOP_PARENT(CK_TOP_NET1PLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D5),
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NETSYSPLL),
+ APMIXED_PARENT(CLK_APMIXED_NET2PLL), APMIXED_PARENT(CLK_APMIXED_MMPLL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D5),
};
static const struct mtk_parent axi_infra_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
};
static const struct mtk_parent uart_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D8),
- TOP_PARENT(CK_TOP_MPLL_D8_D2),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
};
static const struct mtk_parent emmc_250m_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
- TOP_PARENT(CK_TOP_MMPLL_D4),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D4),
};
static const struct mtk_parent emmc_400m_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_MSDCPLL),
- TOP_PARENT(CK_TOP_MMPLL_D2), TOP_PARENT(CK_TOP_MPLL_D2),
- TOP_PARENT(CK_TOP_MMPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MSDCPLL),
+ TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_MPLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
};
static const struct mtk_parent spi_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
- TOP_PARENT(CK_TOP_MMPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
- TOP_PARENT(CK_TOP_NET2PLL_D6), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
- TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET2PLL_D6), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
};
static const struct mtk_parent nfi1x_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D4),
- TOP_PARENT(CK_TOP_NET1PLL_D8_D2), TOP_PARENT(CK_TOP_NET2PLL_D6),
- TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_MMPLL_D8),
- TOP_PARENT(CK_TOP_NET1PLL_D8_D4), TOP_PARENT(CK_TOP_MPLL_D8),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D6),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), TOP_PARENT(CLK_TOP_MPLL_D8),
};
static const struct mtk_parent spinfi_parents[] = {
- TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_XTAL),
- TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
- TOP_PARENT(CK_TOP_MMPLL_D8), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
- TOP_PARENT(CK_TOP_MMPLL_D6_D2), TOP_PARENT(CK_TOP_MPLL_D8),
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+ TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+ TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_MPLL_D8),
};
static const struct mtk_parent pwm_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
- TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
- TOP_PARENT(CK_TOP_MPLL_D8_D2), TOP_PARENT(CK_TOP_RTC_32K),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2), TOP_PARENT(CLK_TOP_RTC_32K),
};
static const struct mtk_parent i2c_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
- TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
};
static const struct mtk_parent pcie_mbist_250m_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
};
static const struct mtk_parent pextp_tl_ck_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D6),
- TOP_PARENT(CK_TOP_MMPLL_D8), TOP_PARENT(CK_TOP_MPLL_D8_D2),
- TOP_PARENT(CK_TOP_RTC_32K),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D6),
+ TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+ TOP_PARENT(CLK_TOP_RTC_32K),
};
static const struct mtk_parent usb_frmcnt_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D3_D5),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D3_D5),
};
static const struct mtk_parent aud_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_APLL2),
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
};
static const struct mtk_parent a1sys_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_APLL2_D4),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
};
static const struct mtk_parent aud_l_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_APLL2),
- TOP_PARENT(CK_TOP_MPLL_D8_D2),
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
};
static const struct mtk_parent sspxtp_parents[] = {
- TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_MPLL_D8_D2),
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
};
static const struct mtk_parent usxgmii_sbus_0_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
};
static const struct mtk_parent sgm_0_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_SGMPLL),
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
};
static const struct mtk_parent sysapb_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D3_D2),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2),
};
static const struct mtk_parent eth_refck_50m_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D4_D4),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4_D4),
};
static const struct mtk_parent eth_sys_200m_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D4),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4),
};
static const struct mtk_parent eth_xgmii_parents[] = {
- TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_NET1PLL_D8_D8),
- TOP_PARENT(CK_TOP_NET1PLL_D8_D16),
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D8_D8),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D16),
};
static const struct mtk_parent bus_tops_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5),
- TOP_PARENT(CK_TOP_NET2PLL_D2),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
+ TOP_PARENT(CLK_TOP_NET2PLL_D2),
};
static const struct mtk_parent npu_tops_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
};
static const struct mtk_parent dramc_md32_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
- APMIXED_PARENT(CK_APMIXED_WEDMCUPLL),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+ APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL),
};
static const struct mtk_parent da_xtp_glb_p0_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D8),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D8),
};
static const struct mtk_parent mcusys_backup_625m_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D4),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
};
static const struct mtk_parent macsec_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_SGMPLL),
- TOP_PARENT(CK_TOP_NET1PLL_D8),
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8),
};
static const struct mtk_parent netsys_tops_400m_parents[] = {
- TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D2),
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2),
};
static const struct mtk_parent eth_mii_parents[] = {
- TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_NET2PLL_D4_D8),
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET2PLL_D4_D8),
};
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
@@ -287,197 +287,197 @@ static const struct mtk_parent eth_mii_parents[] = {
/* TOPCKGEN MUX_GATE */
static const struct mtk_composite topckgen_mtk_muxes[] = {
- TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
+ TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
0, 2, 7, 0x1c0, 0),
- TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+ TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1),
- TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
+ TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
0x4, 0x8, 16, 2, 23, 0x1c0, 2),
- TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
+ TOP_MUX(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3),
- TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
+ TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
0x14, 0x18, 0, 1, 7, 0x1c0, 4),
- TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+ TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5),
- TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
+ TOP_MUX(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6),
- TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
+ TOP_MUX(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
0x18, 24, 3, 31, 0x1c0, 7),
- TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
+ TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
0x24, 0x28, 0, 1, 7, 0x1c0, 8),
- TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
+ TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
2, 15, 0x1c0, 9),
- TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
0x24, 0x28, 16, 2, 23, 0x1c0, 10),
- TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
0x24, 0x28, 24, 3, 31, 0x1c0, 11),
- TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
+ TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
7, 0x1c0, 12),
- TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
0x38, 8, 3, 15, 0x1c0, 13),
- TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
+ TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
16, 3, 23, 0x1c0, 14),
- TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
0x38, 24, 3, 31, 0x1c0, 15),
- TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
+ TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
7, 0x1c0, 16),
- TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
+ TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
15, 0x1c0, 17),
- TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
+ TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0,
18),
- TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+ TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
- TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
+ TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20),
- TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
+ TOP_MUX(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21),
- TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
+ TOP_MUX(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22),
- TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
+ TOP_MUX(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
0x58, 24, 1, 31, 0x1c0, 23),
- TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
+ TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
0x64, 0x68, 0, 1, 7, 0x1c0, 24),
- TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
+ TOP_MUX(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
0x64, 0x68, 8, 1, 15, 0x1c0, 25),
- TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
+ TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26),
- TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
+ TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27),
- TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
+ TOP_MUX(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28),
- TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
+ TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
15, 0x1c0, 29),
- TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
+ TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
16, 1, 23, 0x1c0, 30),
- TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
+ TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
24, 2, 31, 0x1c4, 0),
- TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
+ TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
0x88, 0, 1, 7, 0x1c4, 1),
- TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
+ TOP_MUX(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
0x88, 8, 1, 15, 0x1c4, 2),
- TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
+ TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
0x88, 16, 1, 23, 0x1c4, 3),
- TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
+ TOP_MUX(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4),
- TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
+ TOP_MUX(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5),
- TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
+ TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
8, 1, 15, 0x1c4, 6),
- TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
+ TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7),
- TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
+ TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
24, 1, 31, 0x1c4, 8),
- TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
+ TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9),
- TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10),
- TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11),
- TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
+ TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
0xa8, 24, 1, 31, 0x1c4, 12),
- TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
+ TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
0xb8, 0, 1, 7, 0x1c4, 13),
- TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
+ TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14),
- TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
+ TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15),
- TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
+ TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16),
- TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
+ TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
0xc4, 0xc8, 0, 2, 7, 0x1c4, 17),
- TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
+ TOP_MUX(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
0xc4, 0xc8, 8, 2, 15, 0x1c4, 18),
- TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
+ TOP_MUX(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
0xc4, 0xc8, 16, 1, 23, 0x1c4, 19),
- TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
+ TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
24, 1, 31, 0x1c4, 20),
- TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+ TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21),
- TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22),
- TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
+ TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
0xd8, 16, 1, 23, 0x1c4, 23),
- TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
+ TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
0xd8, 24, 1, 31, 0x1c4, 24),
- TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
+ TOP_MUX(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
0xe8, 0, 1, 7, 0x1c4, 25),
- TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
+ TOP_MUX(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
0xe8, 8, 1, 15, 0x1c4, 26),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
- TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
+ TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
1, 23, 0x1c8, 0),
- TOP_MUX(CK_TOP_DA_SEL, "da_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents,
0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
- TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
+ TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
0x108, 0, 1, 7, 0x1c8, 2),
- TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3),
- TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
+ TOP_MUX(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23,
0x1c8, 4),
- TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
+ TOP_MUX(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8,
5),
- TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
+ TOP_MUX(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
0x118, 0, 2, 7, 0x1c8, 6),
- TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
+ TOP_MUX(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8,
7),
- TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
+ TOP_MUX(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8,
8),
- TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
+ TOP_MUX(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
- TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
+ TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
0x124, 0x128, 0, 1, 7, 0x1c8, 10),
- TOP_MUX(CK_TOP_NPU_SEL, "ck_npu_sel",
+ TOP_MUX(CLK_TOP_NPU_SEL, "ck_npu_sel",
netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
};
/* INFRASYS MUX PARENTS */
-static const int infra_mux_uart0_parents[] = { CK_TOP_INFRA_F26M_SEL,
- CK_TOP_UART_SEL };
+static const int infra_mux_uart0_parents[] = { CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL };
-static const int infra_mux_uart1_parents[] = { CK_TOP_INFRA_F26M_SEL,
- CK_TOP_UART_SEL };
+static const int infra_mux_uart1_parents[] = { CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL };
-static const int infra_mux_uart2_parents[] = { CK_TOP_INFRA_F26M_SEL,
- CK_TOP_UART_SEL };
+static const int infra_mux_uart2_parents[] = { CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL };
-static const int infra_mux_spi0_parents[] = { CK_TOP_I2C_SEL, CK_TOP_SPI_SEL };
+static const int infra_mux_spi0_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPI_SEL };
-static const int infra_mux_spi1_parents[] = { CK_TOP_I2C_SEL, CK_TOP_SPIM_MST_SEL };
+static const int infra_mux_spi1_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPIM_MST_SEL };
-static const int infra_pwm_bck_parents[] = { CK_TOP_RTC_32P7K,
- CK_TOP_INFRA_F26M_SEL, CK_TOP_SYSAXI_SEL,
- CK_TOP_PWM_SEL };
+static const int infra_pwm_bck_parents[] = { CLK_TOP_RTC_32P7K,
+ CLK_TOP_INFRA_F26M_SEL, CLK_TOP_SYSAXI_SEL,
+ CLK_TOP_PWM_SEL };
static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
- CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
- CK_TOP_PEXTP_TL_SEL
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
- CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
- CK_TOP_PEXTP_TL_P1_SEL
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_P1_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
- CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
- CK_TOP_PEXTP_TL_P2_SEL
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_P2_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
- CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
- CK_TOP_PEXTP_TL_P3_SEL
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_P3_SEL
};
#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
@@ -491,46 +491,46 @@ static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
/* INFRA MUX */
static const struct mtk_composite infracfg_mtk_mux[] = {
- INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
+ INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
infra_mux_uart0_parents, 0x10, 0, 1),
- INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
+ INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
infra_mux_uart1_parents, 0x10, 1, 1),
- INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
+ INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
infra_mux_uart2_parents, 0x10, 2, 1),
- INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
+ INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
infra_mux_spi0_parents, 0x10, 4, 1),
- INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
+ INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
infra_mux_spi1_parents, 0x10, 5, 1),
- INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
+ INFRA_MUX(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
infra_mux_spi0_parents, 0x10, 6, 1),
- INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
+ INFRA_MUX(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
0x10, 14, 2),
- INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
infra_pwm_bck_parents, 0x10, 16, 2),
- INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
infra_pwm_bck_parents, 0x10, 18, 2),
- INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
infra_pwm_bck_parents, 0x10, 20, 2),
- INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
infra_pwm_bck_parents, 0x10, 22, 2),
- INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
infra_pwm_bck_parents, 0x10, 24, 2),
- INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
infra_pwm_bck_parents, 0x10, 26, 2),
- INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
infra_pwm_bck_parents, 0x10, 28, 2),
- INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
infra_pwm_bck_parents, 0x10, 30, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
"infra_pcie_gfmux_tl_o_p0_sel",
infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
"infra_pcie_gfmux_tl_o_p1_sel",
infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
"infra_pcie_gfmux_tl_o_p2_sel",
infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
"infra_pcie_gfmux_tl_o_p3_sel",
infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2),
};
@@ -607,166 +607,166 @@ static const struct mtk_gate_regs infra_3_cg_regs = {
/* INFRA GATE */
static const struct mtk_gate infracfg_mtk_gates[] = {
- GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P0,
- "infra_pcie_peri_ck_26m_ck_p0", CK_TOP_INFRA_F26M_SEL, 7),
- GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P1,
- "infra_pcie_peri_ck_26m_ck_p1", CK_TOP_INFRA_F26M_SEL, 8),
- GATE_INFRA0_INFRA(CK_INFRA_PCIE_PERI_26M_CK_P2,
- "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_PCIE_PERI_26M_CK_P3, 9),
- GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P3,
- "infra_pcie_peri_ck_26m_ck_p3", CK_TOP_INFRA_F26M_SEL, 10),
- GATE_INFRA1_TOP(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
- CK_TOP_SYSAXI_SEL, 0),
- GATE_INFRA1_TOP(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
- CK_TOP_SYSAXI_SEL, 1),
- GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
- CK_INFRA_PWM_SEL, 2),
- GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
- CK_INFRA_PWM_CK1_SEL, 3),
- GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
- CK_INFRA_PWM_CK2_SEL, 4),
- GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
- CK_INFRA_PWM_CK3_SEL, 5),
- GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
- CK_INFRA_PWM_CK4_SEL, 6),
- GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
- CK_INFRA_PWM_CK5_SEL, 7),
- GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
- CK_INFRA_PWM_CK6_SEL, 8),
- GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
- CK_INFRA_PWM_CK7_SEL, 9),
- GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
- CK_INFRA_PWM_CK8_SEL, 10),
- GATE_INFRA1_TOP(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
- CK_TOP_SYSAXI_SEL, 12),
- GATE_INFRA1_TOP(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
- CK_TOP_SYSAXI_SEL, 13),
- GATE_INFRA1_TOP(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_TOP_INFRA_F26M_SEL, 14),
- GATE_INFRA1_TOP(CK_INFRA_AUD_L, "infra_f_faud_l", CK_TOP_AUD_L_SEL, 15),
- GATE_INFRA1_TOP(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_TOP_A1SYS_SEL,
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0,
+ "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7),
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1,
+ "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8),
+ GATE_INFRA0_INFRA(CLK_INFRA_PCIE_PERI_26M_CK_P2,
+ "infra_pcie_peri_ck_26m_ck_p2", CLK_INFRA_PCIE_PERI_26M_CK_P3, 9),
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P3,
+ "infra_pcie_peri_ck_26m_ck_p3", CLK_TOP_INFRA_F26M_SEL, 10),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
+ CLK_TOP_SYSAXI_SEL, 0),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
+ CLK_TOP_SYSAXI_SEL, 1),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
+ CLK_INFRA_PWM_SEL, 2),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
+ CLK_INFRA_PWM_CK1_SEL, 3),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
+ CLK_INFRA_PWM_CK2_SEL, 4),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
+ CLK_INFRA_PWM_CK3_SEL, 5),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
+ CLK_INFRA_PWM_CK4_SEL, 6),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
+ CLK_INFRA_PWM_CK5_SEL, 7),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
+ CLK_INFRA_PWM_CK6_SEL, 8),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
+ CLK_INFRA_PWM_CK7_SEL, 9),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
+ CLK_INFRA_PWM_CK8_SEL, 10),
+ GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
+ CLK_TOP_SYSAXI_SEL, 12),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
+ CLK_TOP_SYSAXI_SEL, 13),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m", CLK_TOP_INFRA_F26M_SEL, 14),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL,
16),
- GATE_INFRA1_TOP(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_TOP_A_TUNER_SEL,
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", CLK_TOP_A_TUNER_SEL,
18),
- GATE_INFRA1_TOP(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_TOP_INFRA_F26M_SEL,
+ GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CLK_TOP_INFRA_F26M_SEL,
19),
- GATE_INFRA1_TOP(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
- CK_TOP_SYSAXI_SEL, 20),
- GATE_INFRA1_TOP(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
- CK_TOP_SYSAXI_SEL, 21),
- GATE_INFRA1_TOP(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
- CK_TOP_SYSAXI_SEL, 29),
- GATE_INFRA1_TOP(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
- CK_TOP_INFRA_F26M_SEL, 30),
- /* GATE_INFRA1_TOP(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_TOP_SYSAXI_SEL,
+ GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
+ CLK_TOP_SYSAXI_SEL, 20),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
+ CLK_TOP_SYSAXI_SEL, 21),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
+ CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
+ CLK_TOP_INFRA_F26M_SEL, 30),
+ /* GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", CLK_TOP_SYSAXI_SEL,
31), */
- GATE_INFRA2_TOP(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
- CK_TOP_INFRA_F26M_SEL, 0),
- GATE_INFRA2_TOP(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_TOP_I2C_SEL, 1),
- /* GATE_INFRA2_TOP(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
- CK_TOP_SYSAXI_SEL, 3), */
- /* GATE_INFRA2_TOP(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
- CK_TOP_SYSAXI_SEL, 4), */
- /* GATE_INFRA2_TOP(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
- CK_TOP_SYSAXI_SEL, 5), */
- GATE_INFRA2_INFRA(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
- CK_INFRA_MUX_UART0_SEL, 3),
- GATE_INFRA2_INFRA(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
- CK_INFRA_MUX_UART1_SEL, 4),
- GATE_INFRA2_INFRA(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
- CK_INFRA_MUX_UART2_SEL, 5),
- GATE_INFRA2_TOP(CK_INFRA_NFI, "infra_f_fnfi", CK_TOP_NFI1X_SEL, 9),
- GATE_INFRA2_TOP(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_TOP_SPINFI_SEL, 10),
- GATE_INFRA2_TOP(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
- CK_TOP_SYSAXI_SEL, 11),
- GATE_INFRA2_INFRA(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
- CK_INFRA_MUX_SPI0_SEL, 12),
- GATE_INFRA2_INFRA(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
- CK_INFRA_MUX_SPI1_SEL, 13),
- GATE_INFRA2_INFRA(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
- CK_INFRA_MUX_SPI2_SEL, 14),
- GATE_INFRA2_TOP(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
- CK_TOP_SYSAXI_SEL, 15),
- GATE_INFRA2_TOP(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
- CK_TOP_SYSAXI_SEL, 16),
- GATE_INFRA2_TOP(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
- CK_TOP_SYSAXI_SEL, 17),
- GATE_INFRA2_TOP(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
- CK_TOP_SYSAXI_SEL, 18),
- GATE_INFRA2_TOP(CK_INFRA_RTC, "infra_f_frtc", CK_TOP_RTC_32K, 19),
- GATE_INFRA2_TOP(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
- CK_TOP_INFRA_F26M_SEL, 20),
- GATE_INFRA2_INFRA(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
+ GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
+ CLK_TOP_INFRA_F26M_SEL, 0),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1),
+ /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
+ CLK_TOP_SYSAXI_SEL, 3), */
+ /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
+ CLK_TOP_SYSAXI_SEL, 4), */
+ /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
+ CLK_TOP_SYSAXI_SEL, 5), */
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
+ CLK_INFRA_MUX_UART0_SEL, 3),
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
+ CLK_INFRA_MUX_UART1_SEL, 4),
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
+ CLK_INFRA_MUX_UART2_SEL, 5),
+ GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI1X_SEL, 9),
+ GATE_INFRA2_TOP(CLK_INFRA_SPINFI, "infra_f_fspinfi", CLK_TOP_SPINFI_SEL, 10),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
+ CLK_TOP_SYSAXI_SEL, 11),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
+ CLK_INFRA_MUX_SPI0_SEL, 12),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
+ CLK_INFRA_MUX_SPI1_SEL, 13),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
+ CLK_INFRA_MUX_SPI2_SEL, 14),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
+ CLK_TOP_SYSAXI_SEL, 15),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
+ CLK_TOP_SYSAXI_SEL, 16),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
+ CLK_TOP_SYSAXI_SEL, 17),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
+ CLK_TOP_SYSAXI_SEL, 18),
+ GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_RTC_32K, 19),
+ GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
+ CLK_TOP_INFRA_F26M_SEL, 20),
+ GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc", CLK_INFRA_26M_ADC_BCK,
21),
- GATE_INFRA2_TOP(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_TOP_EMMC_400M_SEL,
+ GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400", CLK_TOP_EMMC_400M_SEL,
22),
- GATE_INFRA2_TOP(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
- CK_TOP_EMMC_250M_SEL, 23),
- GATE_INFRA2_TOP(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
- CK_TOP_SYSAXI_SEL, 24),
- GATE_INFRA2_TOP(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
- CK_TOP_SYSAXI_SEL, 25),
- GATE_INFRA2_TOP(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
- CK_TOP_SYSAXI_SEL, 26),
- GATE_INFRA2_TOP(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_TOP_NFI1X_SEL,
+ GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
+ CLK_TOP_EMMC_250M_SEL, 23),
+ GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
+ CLK_TOP_SYSAXI_SEL, 24),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
+ CLK_TOP_SYSAXI_SEL, 25),
+ GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
+ CLK_TOP_SYSAXI_SEL, 26),
+ GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CLK_TOP_NFI1X_SEL,
27),
- GATE_INFRA2_TOP(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
- CK_TOP_SYSAXI_SEL, 29),
- GATE_INFRA2_TOP(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
- CK_TOP_SYSAXI_SEL, 31),
- GATE_INFRA3_TOP(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
- CK_TOP_SYSAXI_SEL, 0),
- GATE_INFRA3_TOP(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
- CK_TOP_SYSAXI_SEL, 1),
- GATE_INFRA3_TOP(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
- CK_TOP_SYSAXI_SEL, 2),
- GATE_INFRA3_TOP(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
- CK_TOP_SYSAXI_SEL, 3),
- GATE_INFRA3_TOP(CK_INFRA_USB_SYS, "infra_usb_sys", CK_TOP_USB_SYS_SEL, 4),
- GATE_INFRA3_TOP(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
- CK_TOP_USB_SYS_P1_SEL, 5),
- GATE_INFRA3_XTAL(CK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6),
- GATE_INFRA3_XTAL(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL,
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 31),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
+ CLK_TOP_SYSAXI_SEL, 0),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 1),
+ GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
+ CLK_TOP_SYSAXI_SEL, 2),
+ GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 3),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_SYS, "infra_usb_sys", CLK_TOP_USB_SYS_SEL, 4),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
+ CLK_TOP_USB_SYS_P1_SEL, 5),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL,
7),
- GATE_INFRA3_TOP(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
- CK_TOP_USB_FRMCNT_SEL, 8),
- GATE_INFRA3_TOP(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
- CK_TOP_USB_FRMCNT_P1_SEL, 9),
- GATE_INFRA3_XTAL(CK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL,
+ GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
+ CLK_TOP_USB_FRMCNT_SEL, 8),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
+ CLK_TOP_USB_FRMCNT_P1_SEL, 9),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL,
10),
- GATE_INFRA3_XTAL(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
CLK_XTAL, 11),
- GATE_INFRA3_XTAL(CK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL,
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL,
12),
- GATE_INFRA3_XTAL(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
CLK_XTAL, 13),
- GATE_INFRA3_TOP(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_TOP_USB_XHCI_SEL,
+ GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI, "infra_usb_xhci", CLK_TOP_USB_XHCI_SEL,
14),
- GATE_INFRA3_TOP(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
- CK_TOP_USB_XHCI_P1_SEL, 15),
- GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
- CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
- GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
- CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
- GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
- CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
- GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
- CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
- GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
+ GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
+ CLK_TOP_USB_XHCI_P1_SEL, 15),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
CLK_XTAL, 24),
- GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
CLK_XTAL, 25),
- GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
CLK_XTAL, 26),
- GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
CLK_XTAL, 27),
- GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
- CK_TOP_SYSAXI_SEL, 28),
- GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
- CK_TOP_SYSAXI_SEL, 29),
- GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
- CK_TOP_SYSAXI_SEL, 30),
- GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
- CK_TOP_SYSAXI_SEL, 31),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
+ CLK_TOP_SYSAXI_SEL, 28),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
+ CLK_TOP_SYSAXI_SEL, 30),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
+ CLK_TOP_SYSAXI_SEL, 31),
};
static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
@@ -777,8 +777,8 @@ static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
};
static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
- .fdivs_offs = CK_TOP_XTAL_D2,
- .muxes_offs = CK_TOP_NETSYS_SEL,
+ .fdivs_offs = CLK_TOP_XTAL_D2,
+ .muxes_offs = CLK_TOP_NETSYS_SEL,
.fclks = topckgen_mtk_fixed_clks,
.fdivs = topckgen_mtk_fixed_factors,
.muxes = topckgen_mtk_muxes,
@@ -787,8 +787,8 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
};
static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
- .muxes_offs = CK_INFRA_MUX_UART0_SEL,
- .gates_offs = CK_INFRA_PCIE_PERI_26M_CK_P0,
+ .muxes_offs = CLK_INFRA_MUX_UART0_SEL,
+ .gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0,
.muxes = infracfg_mtk_mux,
.gates = infracfg_mtk_gates,
.flags = CLK_BYPASS_XTAL,
@@ -879,7 +879,7 @@ static const struct mtk_gate_regs ethdma_cg_regs = {
}
static const struct mtk_gate ethdma_mtk_gate[] = {
- GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X_SEL, 6),
+ GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6),
};
static int mt7988_ethdma_probe(struct udevice *dev)
@@ -934,10 +934,10 @@ static const struct mtk_gate_regs sgmii0_cg_regs = {
}
static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
- /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
- GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_XTAL, 2),
- /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
- GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_XTAL, 3),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_XTAL, 2),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_XTAL, 3),
};
static int mt7988_sgmiisys_0_probe(struct udevice *dev)
@@ -978,10 +978,10 @@ static const struct mtk_gate_regs sgmii1_cg_regs = {
}
static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
- /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
- GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_XTAL, 2),
- /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
- GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_XTAL, 3),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_XTAL, 2),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_XTAL, 3),
};
static int mt7988_sgmiisys_1_probe(struct udevice *dev)
@@ -1022,12 +1022,12 @@ static const struct mtk_gate_regs ethwarp_cg_regs = {
}
static const struct mtk_gate ethwarp_mtk_gate[] = {
- GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
- CK_TOP_NETSYS_MCU_SEL, 13),
- GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
- CK_TOP_NETSYS_MCU_SEL, 14),
- GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
- CK_TOP_NETSYS_MCU_SEL, 15),
+ GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
+ CLK_TOP_NETSYS_MCU_SEL, 13),
+ GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
+ CLK_TOP_NETSYS_MCU_SEL, 14),
+ GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
+ CLK_TOP_NETSYS_MCU_SEL, 15),
};
static int mt7988_ethwarp_probe(struct udevice *dev)
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 7c64f5f3d03..e6e6978809d 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -10,255 +10,255 @@
/* INFRACFG_AO */
/* mtk_mux */
-#define CK_INFRA_MUX_UART0_SEL 0
-#define CK_INFRA_MUX_UART1_SEL 1
-#define CK_INFRA_MUX_UART2_SEL 2
-#define CK_INFRA_MUX_SPI0_SEL 3
-#define CK_INFRA_MUX_SPI1_SEL 4
-#define CK_INFRA_MUX_SPI2_SEL 5
-#define CK_INFRA_PWM_SEL 6
-#define CK_INFRA_PWM_CK1_SEL 7
-#define CK_INFRA_PWM_CK2_SEL 8
-#define CK_INFRA_PWM_CK3_SEL 9
-#define CK_INFRA_PWM_CK4_SEL 10
-#define CK_INFRA_PWM_CK5_SEL 11
-#define CK_INFRA_PWM_CK6_SEL 12
-#define CK_INFRA_PWM_CK7_SEL 13
-#define CK_INFRA_PWM_CK8_SEL 14
-#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
-#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
-#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
-#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
+#define CLK_INFRA_MUX_UART0_SEL 0
+#define CLK_INFRA_MUX_UART1_SEL 1
+#define CLK_INFRA_MUX_UART2_SEL 2
+#define CLK_INFRA_MUX_SPI0_SEL 3
+#define CLK_INFRA_MUX_SPI1_SEL 4
+#define CLK_INFRA_MUX_SPI2_SEL 5
+#define CLK_INFRA_PWM_SEL 6
+#define CLK_INFRA_PWM_CK1_SEL 7
+#define CLK_INFRA_PWM_CK2_SEL 8
+#define CLK_INFRA_PWM_CK3_SEL 9
+#define CLK_INFRA_PWM_CK4_SEL 10
+#define CLK_INFRA_PWM_CK5_SEL 11
+#define CLK_INFRA_PWM_CK6_SEL 12
+#define CLK_INFRA_PWM_CK7_SEL 13
+#define CLK_INFRA_PWM_CK8_SEL 14
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
/* INFRACFG */
/* mtk_gate */
-#define CK_INFRA_PCIE_PERI_26M_CK_P0 19
-#define CK_INFRA_PCIE_PERI_26M_CK_P1 20
-#define CK_INFRA_PCIE_PERI_26M_CK_P2 21
-#define CK_INFRA_PCIE_PERI_26M_CK_P3 22
-#define CK_INFRA_66M_GPT_BCK 23
-#define CK_INFRA_66M_PWM_HCK 24
-#define CK_INFRA_66M_PWM_BCK 25
-#define CK_INFRA_66M_PWM_CK1 26
-#define CK_INFRA_66M_PWM_CK2 27
-#define CK_INFRA_66M_PWM_CK3 28
-#define CK_INFRA_66M_PWM_CK4 29
-#define CK_INFRA_66M_PWM_CK5 30
-#define CK_INFRA_66M_PWM_CK6 31
-#define CK_INFRA_66M_PWM_CK7 32
-#define CK_INFRA_66M_PWM_CK8 33
-#define CK_INFRA_133M_CQDMA_BCK 34
-#define CK_INFRA_66M_AUD_SLV_BCK 35
-#define CK_INFRA_AUD_26M 36
-#define CK_INFRA_AUD_L 37
-#define CK_INFRA_AUD_AUD 38
-#define CK_INFRA_AUD_EG2 39
-#define CK_INFRA_DRAMC_F26M 40
-#define CK_INFRA_133M_DBG_ACKM 41
-#define CK_INFRA_66M_AP_DMA_BCK 42
-#define CK_INFRA_66M_SEJ_BCK 43
-#define CK_INFRA_PRE_CK_SEJ_F13M 44
-/* #define CK_INFRA_66M_TRNG 44 */
+#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
+#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
+#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
+#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
+#define CLK_INFRA_66M_GPT_BCK 23
+#define CLK_INFRA_66M_PWM_HCK 24
+#define CLK_INFRA_66M_PWM_BCK 25
+#define CLK_INFRA_66M_PWM_CK1 26
+#define CLK_INFRA_66M_PWM_CK2 27
+#define CLK_INFRA_66M_PWM_CK3 28
+#define CLK_INFRA_66M_PWM_CK4 29
+#define CLK_INFRA_66M_PWM_CK5 30
+#define CLK_INFRA_66M_PWM_CK6 31
+#define CLK_INFRA_66M_PWM_CK7 32
+#define CLK_INFRA_66M_PWM_CK8 33
+#define CLK_INFRA_133M_CQDMA_BCK 34
+#define CLK_INFRA_66M_AUD_SLV_BCK 35
+#define CLK_INFRA_AUD_26M 36
+#define CLK_INFRA_AUD_L 37
+#define CLK_INFRA_AUD_AUD 38
+#define CLK_INFRA_AUD_EG2 39
+#define CLK_INFRA_DRAMC_F26M 40
+#define CLK_INFRA_133M_DBG_ACKM 41
+#define CLK_INFRA_66M_AP_DMA_BCK 42
+#define CLK_INFRA_66M_SEJ_BCK 43
+#define CLK_INFRA_PRE_CK_SEJ_F13M 44
+/* #define CLK_INFRA_66M_TRNG 44 */
#define CLK_INFRA_26M_THERM_SYSTEM 45
#define CLK_INFRA_I2C_BCK 46
-/* #define CK_INFRA_66M_UART0_PCK 46 */
-/* #define CK_INFRA_66M_UART1_PCK 47 */
-/* #define CK_INFRA_66M_UART2_PCK 48 */
-#define CK_INFRA_52M_UART0_CK 47
-#define CK_INFRA_52M_UART1_CK 48
-#define CK_INFRA_52M_UART2_CK 49
-#define CK_INFRA_NFI 50
-#define CK_INFRA_SPINFI 51
-#define CK_INFRA_66M_NFI_HCK 52
-#define CK_INFRA_104M_SPI0 53
-#define CK_INFRA_104M_SPI1 54
-#define CK_INFRA_104M_SPI2_BCK 55
-#define CK_INFRA_66M_SPI0_HCK 56
-#define CK_INFRA_66M_SPI1_HCK 57
-#define CK_INFRA_66M_SPI2_HCK 58
-#define CK_INFRA_66M_FLASHIF_AXI 59
-#define CK_INFRA_RTC 60
-#define CK_INFRA_26M_ADC_BCK 61
-#define CK_INFRA_RC_ADC 62
-#define CK_INFRA_MSDC400 63
-#define CK_INFRA_MSDC2_HCK 64
-#define CK_INFRA_133M_MSDC_0_HCK 65
-#define CK_INFRA_66M_MSDC_0_HCK 66
-#define CK_INFRA_133M_CPUM_BCK 67
-#define CK_INFRA_BIST2FPC 68
-#define CK_INFRA_I2C_X16W_MCK_CK_P1 69
-#define CK_INFRA_I2C_X16W_PCK_CK_P1 70
-#define CK_INFRA_133M_USB_HCK 71
-#define CK_INFRA_133M_USB_HCK_CK_P1 72
-#define CK_INFRA_66M_USB_HCK 73
-#define CK_INFRA_66M_USB_HCK_CK_P1 74
-#define CK_INFRA_USB_SYS 75
-#define CK_INFRA_USB_SYS_CK_P1 76
-#define CK_INFRA_USB_REF 77
-#define CK_INFRA_USB_CK_P1 78
-#define CK_INFRA_USB_FRMCNT 79
-#define CK_INFRA_USB_FRMCNT_CK_P1 80
-#define CK_INFRA_USB_PIPE 81
-#define CK_INFRA_USB_PIPE_CK_P1 82
-#define CK_INFRA_USB_UTMI 83
-#define CK_INFRA_USB_UTMI_CK_P1 84
-#define CK_INFRA_USB_XHCI 85
-#define CK_INFRA_USB_XHCI_CK_P1 86
-#define CK_INFRA_PCIE_GFMUX_TL_P0 87
-#define CK_INFRA_PCIE_GFMUX_TL_P1 88
-#define CK_INFRA_PCIE_GFMUX_TL_P2 89
-#define CK_INFRA_PCIE_GFMUX_TL_P3 90
-#define CK_INFRA_PCIE_PIPE_P0 91
-#define CK_INFRA_PCIE_PIPE_P1 92
-#define CK_INFRA_PCIE_PIPE_P2 93
-#define CK_INFRA_PCIE_PIPE_P3 94
-#define CK_INFRA_133M_PCIE_CK_P0 95
-#define CK_INFRA_133M_PCIE_CK_P1 96
-#define CK_INFRA_133M_PCIE_CK_P2 97
-#define CK_INFRA_133M_PCIE_CK_P3 98
+/* #define CLK_INFRA_66M_UART0_PCK 46 */
+/* #define CLK_INFRA_66M_UART1_PCK 47 */
+/* #define CLK_INFRA_66M_UART2_PCK 48 */
+#define CLK_INFRA_52M_UART0_CK 47
+#define CLK_INFRA_52M_UART1_CK 48
+#define CLK_INFRA_52M_UART2_CK 49
+#define CLK_INFRA_NFI 50
+#define CLK_INFRA_SPINFI 51
+#define CLK_INFRA_66M_NFI_HCK 52
+#define CLK_INFRA_104M_SPI0 53
+#define CLK_INFRA_104M_SPI1 54
+#define CLK_INFRA_104M_SPI2_BCK 55
+#define CLK_INFRA_66M_SPI0_HCK 56
+#define CLK_INFRA_66M_SPI1_HCK 57
+#define CLK_INFRA_66M_SPI2_HCK 58
+#define CLK_INFRA_66M_FLASHIF_AXI 59
+#define CLK_INFRA_RTC 60
+#define CLK_INFRA_26M_ADC_BCK 61
+#define CLK_INFRA_RC_ADC 62
+#define CLK_INFRA_MSDC400 63
+#define CLK_INFRA_MSDC2_HCK 64
+#define CLK_INFRA_133M_MSDC_0_HCK 65
+#define CLK_INFRA_66M_MSDC_0_HCK 66
+#define CLK_INFRA_133M_CPUM_BCK 67
+#define CLK_INFRA_BIST2FPC 68
+#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
+#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
+#define CLK_INFRA_133M_USB_HCK 71
+#define CLK_INFRA_133M_USB_HCK_CK_P1 72
+#define CLK_INFRA_66M_USB_HCK 73
+#define CLK_INFRA_66M_USB_HCK_CK_P1 74
+#define CLK_INFRA_USB_SYS 75
+#define CLK_INFRA_USB_SYS_CK_P1 76
+#define CLK_INFRA_USB_REF 77
+#define CLK_INFRA_USB_CK_P1 78
+#define CLK_INFRA_USB_FRMCNT 79
+#define CLK_INFRA_USB_FRMCNT_CK_P1 80
+#define CLK_INFRA_USB_PIPE 81
+#define CLK_INFRA_USB_PIPE_CK_P1 82
+#define CLK_INFRA_USB_UTMI 83
+#define CLK_INFRA_USB_UTMI_CK_P1 84
+#define CLK_INFRA_USB_XHCI 85
+#define CLK_INFRA_USB_XHCI_CK_P1 86
+#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
+#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
+#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
+#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
+#define CLK_INFRA_PCIE_PIPE_P0 91
+#define CLK_INFRA_PCIE_PIPE_P1 92
+#define CLK_INFRA_PCIE_PIPE_P2 93
+#define CLK_INFRA_PCIE_PIPE_P3 94
+#define CLK_INFRA_133M_PCIE_CK_P0 95
+#define CLK_INFRA_133M_PCIE_CK_P1 96
+#define CLK_INFRA_133M_PCIE_CK_P2 97
+#define CLK_INFRA_133M_PCIE_CK_P3 98
/* TOPCKGEN */
/* mtk_fixed_clk */
-#define CK_TOP_XTAL 0
+#define CLK_TOP_XTAL 0
/* mtk_fixed_factor */
-#define CK_TOP_XTAL_D2 1
-#define CK_TOP_RTC_32K 2
-#define CK_TOP_RTC_32P7K 3
-#define CK_TOP_MPLL_D2 4
-#define CK_TOP_MPLL_D3_D2 5
-#define CK_TOP_MPLL_D4 6
-#define CK_TOP_MPLL_D8 7
-#define CK_TOP_MPLL_D8_D2 8
-#define CK_TOP_MMPLL_D2 9
-#define CK_TOP_MMPLL_D3_D5 10
-#define CK_TOP_MMPLL_D4 11
-#define CK_TOP_MMPLL_D6_D2 12
-#define CK_TOP_MMPLL_D8 13
-#define CK_TOP_APLL2_D4 14
-#define CK_TOP_NET1PLL_D4 15
-#define CK_TOP_NET1PLL_D5 16
-#define CK_TOP_NET1PLL_D5_D2 17
-#define CK_TOP_NET1PLL_D5_D4 18
-#define CK_TOP_NET1PLL_D8 19
-#define CK_TOP_NET1PLL_D8_D2 20
-#define CK_TOP_NET1PLL_D8_D4 21
-#define CK_TOP_NET1PLL_D8_D8 22
-#define CK_TOP_NET1PLL_D8_D16 23
-#define CK_TOP_NET2PLL_D2 24
-#define CK_TOP_NET2PLL_D4 25
-#define CK_TOP_NET2PLL_D4_D4 26
-#define CK_TOP_NET2PLL_D4_D8 27
-#define CK_TOP_NET2PLL_D6 28
-#define CK_TOP_NET2PLL_D8 29
+#define CLK_TOP_XTAL_D2 1
+#define CLK_TOP_RTC_32K 2
+#define CLK_TOP_RTC_32P7K 3
+#define CLK_TOP_MPLL_D2 4
+#define CLK_TOP_MPLL_D3_D2 5
+#define CLK_TOP_MPLL_D4 6
+#define CLK_TOP_MPLL_D8 7
+#define CLK_TOP_MPLL_D8_D2 8
+#define CLK_TOP_MMPLL_D2 9
+#define CLK_TOP_MMPLL_D3_D5 10
+#define CLK_TOP_MMPLL_D4 11
+#define CLK_TOP_MMPLL_D6_D2 12
+#define CLK_TOP_MMPLL_D8 13
+#define CLK_TOP_APLL2_D4 14
+#define CLK_TOP_NET1PLL_D4 15
+#define CLK_TOP_NET1PLL_D5 16
+#define CLK_TOP_NET1PLL_D5_D2 17
+#define CLK_TOP_NET1PLL_D5_D4 18
+#define CLK_TOP_NET1PLL_D8 19
+#define CLK_TOP_NET1PLL_D8_D2 20
+#define CLK_TOP_NET1PLL_D8_D4 21
+#define CLK_TOP_NET1PLL_D8_D8 22
+#define CLK_TOP_NET1PLL_D8_D16 23
+#define CLK_TOP_NET2PLL_D2 24
+#define CLK_TOP_NET2PLL_D4 25
+#define CLK_TOP_NET2PLL_D4_D4 26
+#define CLK_TOP_NET2PLL_D4_D8 27
+#define CLK_TOP_NET2PLL_D6 28
+#define CLK_TOP_NET2PLL_D8 29
/* mtk_mux */
-#define CK_TOP_NETSYS_SEL 30
-#define CK_TOP_NETSYS_500M_SEL 31
-#define CK_TOP_NETSYS_2X_SEL 32
-#define CK_TOP_NETSYS_GSW_SEL 33
-#define CK_TOP_ETH_GMII_SEL 34
-#define CK_TOP_NETSYS_MCU_SEL 35
-#define CK_TOP_NETSYS_PAO_2X_SEL 36
-#define CK_TOP_EIP197_SEL 37
-#define CK_TOP_AXI_INFRA_SEL 38
-#define CK_TOP_UART_SEL 39
-#define CK_TOP_EMMC_250M_SEL 40
-#define CK_TOP_EMMC_400M_SEL 41
-#define CK_TOP_SPI_SEL 42
-#define CK_TOP_SPIM_MST_SEL 43
-#define CK_TOP_NFI1X_SEL 44
-#define CK_TOP_SPINFI_SEL 45
-#define CK_TOP_PWM_SEL 46
-#define CK_TOP_I2C_SEL 47
-#define CK_TOP_PCIE_MBIST_250M_SEL 48
-#define CK_TOP_PEXTP_TL_SEL 49
-#define CK_TOP_PEXTP_TL_P1_SEL 50
-#define CK_TOP_PEXTP_TL_P2_SEL 51
-#define CK_TOP_PEXTP_TL_P3_SEL 52
-#define CK_TOP_USB_SYS_SEL 53
-#define CK_TOP_USB_SYS_P1_SEL 54
-#define CK_TOP_USB_XHCI_SEL 55
-#define CK_TOP_USB_XHCI_P1_SEL 56
-#define CK_TOP_USB_FRMCNT_SEL 57
-#define CK_TOP_USB_FRMCNT_P1_SEL 58
-#define CK_TOP_AUD_SEL 59
-#define CK_TOP_A1SYS_SEL 60
-#define CK_TOP_AUD_L_SEL 61
-#define CK_TOP_A_TUNER_SEL 62
-#define CK_TOP_SSPXTP_SEL 63
-#define CK_TOP_USB_PHY_SEL 64
-#define CK_TOP_USXGMII_SBUS_0_SEL 65
-#define CK_TOP_USXGMII_SBUS_1_SEL 66
-#define CK_TOP_SGM_0_SEL 67
-#define CK_TOP_SGM_SBUS_0_SEL 68
-#define CK_TOP_SGM_1_SEL 69
-#define CK_TOP_SGM_SBUS_1_SEL 70
-#define CK_TOP_XFI_PHY_0_XTAL_SEL 71
-#define CK_TOP_XFI_PHY_1_XTAL_SEL 72
-#define CK_TOP_SYSAXI_SEL 73
-#define CK_TOP_SYSAPB_SEL 74
-#define CK_TOP_ETH_REFCK_50M_SEL 75
-#define CK_TOP_ETH_SYS_200M_SEL 76
-#define CK_TOP_ETH_SYS_SEL 77
-#define CK_TOP_ETH_XGMII_SEL 78
-#define CK_TOP_BUS_TOPS_SEL 79
-#define CK_TOP_NPU_TOPS_SEL 80
-#define CK_TOP_DRAMC_SEL 81
-#define CK_TOP_DRAMC_MD32_SEL 82
-#define CK_TOP_INFRA_F26M_SEL 83
-#define CK_TOP_PEXTP_P0_SEL 84
-#define CK_TOP_PEXTP_P1_SEL 85
-#define CK_TOP_PEXTP_P2_SEL 86
-#define CK_TOP_PEXTP_P3_SEL 87
-#define CK_TOP_DA_XTP_GLB_P0_SEL 88
-#define CK_TOP_DA_XTP_GLB_P1_SEL 89
-#define CK_TOP_DA_XTP_GLB_P2_SEL 90
-#define CK_TOP_DA_XTP_GLB_P3_SEL 91
-#define CK_TOP_CKM_SEL 92
-#define CK_TOP_DA_SEL 93
-#define CK_TOP_PEXTP_SEL 94
-#define CK_TOP_TOPS_P2_26M_SEL 95
-#define CK_TOP_MCUSYS_BACKUP_625M_SEL 96
-#define CK_TOP_NETSYS_SYNC_250M_SEL 97
-#define CK_TOP_MACSEC_SEL 98
-#define CK_TOP_NETSYS_TOPS_400M_SEL 99
-#define CK_TOP_NETSYS_PPEFB_250M_SEL 100
-#define CK_TOP_NETSYS_WARP_SEL 101
-#define CK_TOP_ETH_MII_SEL 102
-#define CK_TOP_NPU_SEL 103
+#define CLK_TOP_NETSYS_SEL 30
+#define CLK_TOP_NETSYS_500M_SEL 31
+#define CLK_TOP_NETSYS_2X_SEL 32
+#define CLK_TOP_NETSYS_GSW_SEL 33
+#define CLK_TOP_ETH_GMII_SEL 34
+#define CLK_TOP_NETSYS_MCU_SEL 35
+#define CLK_TOP_NETSYS_PAO_2X_SEL 36
+#define CLK_TOP_EIP197_SEL 37
+#define CLK_TOP_AXI_INFRA_SEL 38
+#define CLK_TOP_UART_SEL 39
+#define CLK_TOP_EMMC_250M_SEL 40
+#define CLK_TOP_EMMC_400M_SEL 41
+#define CLK_TOP_SPI_SEL 42
+#define CLK_TOP_SPIM_MST_SEL 43
+#define CLK_TOP_NFI1X_SEL 44
+#define CLK_TOP_SPINFI_SEL 45
+#define CLK_TOP_PWM_SEL 46
+#define CLK_TOP_I2C_SEL 47
+#define CLK_TOP_PCIE_MBIST_250M_SEL 48
+#define CLK_TOP_PEXTP_TL_SEL 49
+#define CLK_TOP_PEXTP_TL_P1_SEL 50
+#define CLK_TOP_PEXTP_TL_P2_SEL 51
+#define CLK_TOP_PEXTP_TL_P3_SEL 52
+#define CLK_TOP_USB_SYS_SEL 53
+#define CLK_TOP_USB_SYS_P1_SEL 54
+#define CLK_TOP_USB_XHCI_SEL 55
+#define CLK_TOP_USB_XHCI_P1_SEL 56
+#define CLK_TOP_USB_FRMCNT_SEL 57
+#define CLK_TOP_USB_FRMCNT_P1_SEL 58
+#define CLK_TOP_AUD_SEL 59
+#define CLK_TOP_A1SYS_SEL 60
+#define CLK_TOP_AUD_L_SEL 61
+#define CLK_TOP_A_TUNER_SEL 62
+#define CLK_TOP_SSPXTP_SEL 63
+#define CLK_TOP_USB_PHY_SEL 64
+#define CLK_TOP_USXGMII_SBUS_0_SEL 65
+#define CLK_TOP_USXGMII_SBUS_1_SEL 66
+#define CLK_TOP_SGM_0_SEL 67
+#define CLK_TOP_SGM_SBUS_0_SEL 68
+#define CLK_TOP_SGM_1_SEL 69
+#define CLK_TOP_SGM_SBUS_1_SEL 70
+#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
+#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
+#define CLK_TOP_SYSAXI_SEL 73
+#define CLK_TOP_SYSAPB_SEL 74
+#define CLK_TOP_ETH_REFCK_50M_SEL 75
+#define CLK_TOP_ETH_SYS_200M_SEL 76
+#define CLK_TOP_ETH_SYS_SEL 77
+#define CLK_TOP_ETH_XGMII_SEL 78
+#define CLK_TOP_BUS_TOPS_SEL 79
+#define CLK_TOP_NPU_TOPS_SEL 80
+#define CLK_TOP_DRAMC_SEL 81
+#define CLK_TOP_DRAMC_MD32_SEL 82
+#define CLK_TOP_INFRA_F26M_SEL 83
+#define CLK_TOP_PEXTP_P0_SEL 84
+#define CLK_TOP_PEXTP_P1_SEL 85
+#define CLK_TOP_PEXTP_P2_SEL 86
+#define CLK_TOP_PEXTP_P3_SEL 87
+#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
+#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
+#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
+#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
+#define CLK_TOP_CKM_SEL 92
+#define CLK_TOP_DA_SEL 93
+#define CLK_TOP_PEXTP_SEL 94
+#define CLK_TOP_TOPS_P2_26M_SEL 95
+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
+#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
+#define CLK_TOP_MACSEC_SEL 98
+#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
+#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
+#define CLK_TOP_NETSYS_WARP_SEL 101
+#define CLK_TOP_ETH_MII_SEL 102
+#define CLK_TOP_NPU_SEL 103
/* APMIXEDSYS */
/* mtk_pll_data */
-#define CK_APMIXED_NETSYSPLL 0
-#define CK_APMIXED_MPLL 1
-#define CK_APMIXED_MMPLL 2
-#define CK_APMIXED_APLL2 3
-#define CK_APMIXED_NET1PLL 4
-#define CK_APMIXED_NET2PLL 5
-#define CK_APMIXED_WEDMCUPLL 6
-#define CK_APMIXED_SGMPLL 7
-#define CK_APMIXED_ARM_B 8
-#define CK_APMIXED_CCIPLL2_B 9
-#define CK_APMIXED_USXGMIIPLL 10
-#define CK_APMIXED_MSDCPLL 11
+#define CLK_APMIXED_NETSYSPLL 0
+#define CLK_APMIXED_MPLL 1
+#define CLK_APMIXED_MMPLL 2
+#define CLK_APMIXED_APLL2 3
+#define CLK_APMIXED_NET1PLL 4
+#define CLK_APMIXED_NET2PLL 5
+#define CLK_APMIXED_WEDMCUPLL 6
+#define CLK_APMIXED_SGMPLL 7
+#define CLK_APMIXED_ARM_B 8
+#define CLK_APMIXED_CCIPLL2_B 9
+#define CLK_APMIXED_USXGMIIPLL 10
+#define CLK_APMIXED_MSDCPLL 11
/* ETHSYS ETH DMA */
/* mtk_gate */
-#define CK_ETHDMA_FE_EN 0
+#define CLK_ETHDMA_FE_EN 0
/* SGMIISYS_0 */
/* mtk_gate */
-#define CK_SGM0_TX_EN 0
-#define CK_SGM0_RX_EN 1
+#define CLK_SGM0_TX_EN 0
+#define CLK_SGM0_RX_EN 1
/* SGMIISYS_1 */
/* mtk_gate */
-#define CK_SGM1_TX_EN 0
-#define CK_SGM1_RX_EN 1
+#define CLK_SGM1_TX_EN 0
+#define CLK_SGM1_RX_EN 1
/* ETHWARP */
/* mtk_gate */
-#define CK_ETHWARP_WOCPU2_EN 0
-#define CK_ETHWARP_WOCPU1_EN 1
-#define CK_ETHWARP_WOCPU0_EN 2
+#define CLK_ETHWARP_WOCPU2_EN 0
+#define CLK_ETHWARP_WOCPU1_EN 1
+#define CLK_ETHWARP_WOCPU0_EN 2
#endif /* _DT_BINDINGS_CLK_MT7988_H */
--
2.45.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Aw: [PATCH 13/13] clk: mediatek: mt7988: rename CK to CLK
2024-08-03 8:33 ` [PATCH 13/13] clk: mediatek: mt7988: rename CK to CLK Christian Marangi
@ 2024-08-10 18:46 ` Frank Wunderlich
0 siblings, 0 replies; 16+ messages in thread
From: Frank Wunderlich @ 2024-08-10 18:46 UTC (permalink / raw)
To: Christian Marangi
Cc: Tom Rini, Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Christian Marangi,
Dong Huang, u-boot
Hi,
tested on Banana Pi R4
does not break downstream DTS, upstream dts is nearly empty, have tried with our internal dts(i)...so we srtil nee some driver patches to add/fix compatibles and work without syscon.
tested: mmc, usb, network, spi, pci/nvme
Tested-by: Frank Wunderlich <frank-w@public-files.de>
regards Frank
> Gesendet: Samstag, 03. August 2024 um 10:33 Uhr
> Von: "Christian Marangi" <ansuelsmth@gmail.com>
> An: "Tom Rini" <trini@konsulko.com>, "Lukasz Majewski" <lukma@denx.de>, "Sean Anderson" <seanga2@gmail.com>, "Ryder Lee" <ryder.lee@mediatek.com>, "Weijie Gao" <weijie.gao@mediatek.com>, "Chunfeng Yun" <chunfeng.yun@mediatek.com>, "GSS_MTK_Uboot_upstream" <GSS_MTK_Uboot_upstream@mediatek.com>, "Christian Marangi" <ansuelsmth@gmail.com>, "Frank Wunderlich" <frank-w@public-files.de>, "Dong Huang" <dong.huang@mediatek.com>, u-boot@lists.denx.de
> Betreff: [PATCH 13/13] clk: mediatek: mt7988: rename CK to CLK
>
> Rename each entry from CK to CLK to match the include in upstream kernel
> linux.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> arch/arm/dts/mt7988.dtsi | 84 +--
> drivers/clk/mediatek/clk-mt7988.c | 768 ++++++++++++-------------
> include/dt-bindings/clock/mt7988-clk.h | 450 +++++++--------
> 3 files changed, 651 insertions(+), 651 deletions(-)
>
> diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
> index 4695e1db1ad..e120e5084ce 100644
> --- a/arch/arm/dts/mt7988.dtsi
> +++ b/arch/arm/dts/mt7988.dtsi
> @@ -255,11 +255,11 @@
> compatible = "mediatek,hsuart";
> reg = <0 0x11000000 0 0x100>;
> interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&infracfg CK_INFRA_52M_UART0_CK>;
> - assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
> - <&infracfg CK_INFRA_MUX_UART0_SEL>;
> - assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
> - <&topckgen CK_TOP_UART_SEL>;
> + clocks = <&infracfg CLK_INFRA_52M_UART0_CK>;
> + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
> + <&infracfg CLK_INFRA_MUX_UART0_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
> + <&topckgen CLK_TOP_UART_SEL>;
> status = "disabled";
> };
>
> @@ -267,11 +267,11 @@
> compatible = "mediatek,hsuart";
> reg = <0 0x11000100 0 0x100>;
> interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&infracfg CK_INFRA_52M_UART1_CK>;
> - assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
> - <&infracfg CK_INFRA_MUX_UART1_SEL>;
> - assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
> - <&topckgen CK_TOP_UART_SEL>;
> + clocks = <&infracfg CLK_INFRA_52M_UART1_CK>;
> + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
> + <&infracfg CLK_INFRA_MUX_UART1_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
> + <&topckgen CLK_TOP_UART_SEL>;
> status = "disabled";
> };
>
> @@ -279,11 +279,11 @@
> compatible = "mediatek,hsuart";
> reg = <0 0x11000200 0 0x100>;
> interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&infracfg CK_INFRA_52M_UART2_CK>;
> - assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
> - <&infracfg CK_INFRA_MUX_UART2_SEL>;
> - assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
> - <&topckgen CK_TOP_UART_SEL>;
> + clocks = <&infracfg CLK_INFRA_52M_UART2_CK>;
> + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
> + <&infracfg CLK_INFRA_MUX_UART2_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
> + <&topckgen CLK_TOP_UART_SEL>;
> status = "disabled";
> };
>
> @@ -294,8 +294,8 @@
> <0 0x10217080 0 0x80>;
> interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
> clock-div = <1>;
> - clocks = <&infracfg CK_INFRA_I2C_BCK>,
> - <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
> + clocks = <&infracfg CLK_INFRA_I2C_BCK>,
> + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
> clock-names = "main", "dma";
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -309,8 +309,8 @@
> <0 0x10217100 0 0x80>;
> interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> clock-div = <1>;
> - clocks = <&infracfg CK_INFRA_I2C_BCK>,
> - <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
> + clocks = <&infracfg CLK_INFRA_I2C_BCK>,
> + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
> clock-names = "main", "dma";
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -324,8 +324,8 @@
> <0 0x10217180 0 0x80>;
> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> clock-div = <1>;
> - clocks = <&infracfg CK_INFRA_I2C_BCK>,
> - <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
> + clocks = <&infracfg CLK_INFRA_I2C_BCK>,
> + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
> clock-names = "main", "dma";
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -336,16 +336,16 @@
> compatible = "mediatek,mt7988-pwm";
> reg = <0 0x10048000 0 0x1000>;
> #pwm-cells = <2>;
> - clocks = <&infracfg CK_INFRA_66M_PWM_BCK>,
> - <&infracfg CK_INFRA_66M_PWM_HCK>,
> - <&infracfg CK_INFRA_66M_PWM_CK1>,
> - <&infracfg CK_INFRA_66M_PWM_CK2>,
> - <&infracfg CK_INFRA_66M_PWM_CK3>,
> - <&infracfg CK_INFRA_66M_PWM_CK4>,
> - <&infracfg CK_INFRA_66M_PWM_CK5>,
> - <&infracfg CK_INFRA_66M_PWM_CK6>,
> - <&infracfg CK_INFRA_66M_PWM_CK7>,
> - <&infracfg CK_INFRA_66M_PWM_CK8>;
> + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
> + <&infracfg CLK_INFRA_66M_PWM_HCK>,
> + <&infracfg CLK_INFRA_66M_PWM_CK1>,
> + <&infracfg CLK_INFRA_66M_PWM_CK2>,
> + <&infracfg CLK_INFRA_66M_PWM_CK3>,
> + <&infracfg CLK_INFRA_66M_PWM_CK4>,
> + <&infracfg CLK_INFRA_66M_PWM_CK5>,
> + <&infracfg CLK_INFRA_66M_PWM_CK6>,
> + <&infracfg CLK_INFRA_66M_PWM_CK7>,
> + <&infracfg CLK_INFRA_66M_PWM_CK8>;
> clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
> "pwm4","pwm5","pwm6","pwm7","pwm8";
> status = "disabled";
> @@ -358,14 +358,14 @@
> <0 0x11002000 0 0x1000>;
> reg-names = "nfi", "ecc";
> interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&infracfg CK_INFRA_SPINFI>,
> - <&infracfg CK_INFRA_NFI>,
> - <&infracfg CK_INFRA_66M_NFI_HCK>;
> + clocks = <&infracfg CLK_INFRA_SPINFI>,
> + <&infracfg CLK_INFRA_NFI>,
> + <&infracfg CLK_INFRA_66M_NFI_HCK>;
> clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
> - assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
> - <&topckgen CK_TOP_NFI1X_SEL>;
> - assigned-clock-parents = <&topckgen CK_TOP_MPLL_D8>,
> - <&topckgen CK_TOP_MPLL_D8>;
> + assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
> + <&topckgen CLK_TOP_NFI1X_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
> + <&topckgen CLK_TOP_MPLL_D8>;
> status = "disabled";
> };
>
> @@ -401,10 +401,10 @@
> "mediatek,mt7986-mmc";
> reg = <0 0x11230000 0 0x1000>;
> interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&infracfg CK_INFRA_MSDC400>,
> - <&infracfg CK_INFRA_MSDC2_HCK>,
> - <&infracfg CK_INFRA_133M_MSDC_0_HCK>,
> - <&infracfg CK_INFRA_66M_MSDC_0_HCK>;
> + clocks = <&infracfg CLK_INFRA_MSDC400>,
> + <&infracfg CLK_INFRA_MSDC2_HCK>,
> + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
> + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
> clock-names = "source", "hclk", "source_cg", "axi_cg";
> status = "disabled";
> };
> diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
> index a8d278816bb..8f4e8f4e8c9 100644
> --- a/drivers/clk/mediatek/clk-mt7988.c
> +++ b/drivers/clk/mediatek/clk-mt7988.c
> @@ -35,59 +35,59 @@
>
> /* FIXED PLLS */
> static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
> - FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
> - FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
> - FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
> - FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
> - FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
> - FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
> - FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
> - FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
> - FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
> - FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
> - FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
> - FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
> + FIXED_CLK(CLK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
> + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
> + FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),
> + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
> + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
> + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
> + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
> + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
> + FIXED_CLK(CLK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
> + FIXED_CLK(CLK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
> + FIXED_CLK(CLK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
> + FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
> };
>
> /* TOPCKGEN FIXED CLK */
> static const struct mtk_fixed_clk topckgen_mtk_fixed_clks[] = {
> - FIXED_CLK(CK_TOP_XTAL, CLK_XTAL, 40000000),
> + FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),
> };
>
> /* TOPCKGEN FIXED DIV */
> static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
> - TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL, 1, 2),
> - TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
> + TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL, 1, 2),
> + TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1,
> 1250),
> - TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
> + TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1,
> 1220),
> - PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
> - PLL_FACTOR(CK_TOP_MPLL_D3_D2, "mpll_d3_d2", CK_APMIXED_MPLL, 1, 2),
> - PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
> - PLL_FACTOR(CK_TOP_MPLL_D8, "mpll_d8", CK_APMIXED_MPLL, 1, 8),
> - PLL_FACTOR(CK_TOP_MPLL_D8_D2, "mpll_d8_d2", CK_APMIXED_MPLL, 1, 16),
> - PLL_FACTOR(CK_TOP_MMPLL_D2, "mmpll_d2", CK_APMIXED_MMPLL, 1, 2),
> - PLL_FACTOR(CK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CK_APMIXED_MMPLL, 1, 15),
> - PLL_FACTOR(CK_TOP_MMPLL_D4, "mmpll_d4", CK_APMIXED_MMPLL, 1, 4),
> - PLL_FACTOR(CK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CK_APMIXED_MMPLL, 1, 12),
> - PLL_FACTOR(CK_TOP_MMPLL_D8, "mmpll_d8", CK_APMIXED_MMPLL, 1, 8),
> - PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
> - PLL_FACTOR(CK_TOP_NET1PLL_D4, "net1pll_d4", CK_APMIXED_NET1PLL, 1, 4),
> - PLL_FACTOR(CK_TOP_NET1PLL_D5, "net1pll_d5", CK_APMIXED_NET1PLL, 1, 5),
> - PLL_FACTOR(CK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
> - PLL_FACTOR(CK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
> - PLL_FACTOR(CK_TOP_NET1PLL_D8, "net1pll_d8", CK_APMIXED_NET1PLL, 1, 8),
> - PLL_FACTOR(CK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
> - PLL_FACTOR(CK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
> - PLL_FACTOR(CK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
> - PLL_FACTOR(CK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CK_APMIXED_NET1PLL, 1,
> + PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2),
> + PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2),
> + PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4),
> + PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8),
> + PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16),
> + PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
> + PLL_FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CLK_APMIXED_MMPLL, 1, 15),
> + PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4),
> + PLL_FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CLK_APMIXED_MMPLL, 1, 12),
> + PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8),
> + PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
> + PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4),
> + PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5),
> + PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
> + PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
> + PLL_FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", CLK_APMIXED_NET1PLL, 1, 8),
> + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
> + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
> + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CLK_APMIXED_NET1PLL, 1, 64),
> + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CLK_APMIXED_NET1PLL, 1,
> 128),
> - PLL_FACTOR(CK_TOP_NET2PLL_D2, "net2pll_d2", CK_APMIXED_NET2PLL, 1, 2),
> - PLL_FACTOR(CK_TOP_NET2PLL_D4, "net2pll_d4", CK_APMIXED_NET2PLL, 1, 4),
> - PLL_FACTOR(CK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
> - PLL_FACTOR(CK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
> - PLL_FACTOR(CK_TOP_NET2PLL_D6, "net2pll_d6", CK_APMIXED_NET2PLL, 1, 6),
> - PLL_FACTOR(CK_TOP_NET2PLL_D8, "net2pll_d8", CK_APMIXED_NET2PLL, 1, 8),
> + PLL_FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", CLK_APMIXED_NET2PLL, 1, 2),
> + PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4),
> + PLL_FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CLK_APMIXED_NET2PLL, 1, 16),
> + PLL_FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CLK_APMIXED_NET2PLL, 1, 32),
> + PLL_FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", CLK_APMIXED_NET2PLL, 1, 6),
> + PLL_FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", CLK_APMIXED_NET2PLL, 1, 8),
> };
>
> /* TOPCKGEN MUX PARENTS */
> @@ -95,182 +95,182 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
> #define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
>
> static const struct mtk_parent netsys_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D2),
> - TOP_PARENT(CK_TOP_MMPLL_D2),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2),
> + TOP_PARENT(CLK_TOP_MMPLL_D2),
> };
>
> static const struct mtk_parent netsys_500m_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5),
> - TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
> + TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
> };
>
> static const struct mtk_parent netsys_2x_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
> - APMIXED_PARENT(CK_APMIXED_MMPLL),
> + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
> + APMIXED_PARENT(CLK_APMIXED_MMPLL),
> };
>
> static const struct mtk_parent netsys_gsw_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D4),
> - TOP_PARENT(CK_TOP_NET1PLL_D5),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
> + TOP_PARENT(CLK_TOP_NET1PLL_D5),
> };
>
> static const struct mtk_parent eth_gmii_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
> };
>
> static const struct mtk_parent netsys_mcu_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
> - APMIXED_PARENT(CK_APMIXED_MMPLL), TOP_PARENT(CK_TOP_NET1PLL_D4),
> - TOP_PARENT(CK_TOP_NET1PLL_D5), APMIXED_PARENT(CK_APMIXED_MPLL),
> + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
> + APMIXED_PARENT(CLK_APMIXED_MMPLL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
> + TOP_PARENT(CLK_TOP_NET1PLL_D5), APMIXED_PARENT(CLK_APMIXED_MPLL),
> };
>
> static const struct mtk_parent eip197_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NETSYSPLL),
> - APMIXED_PARENT(CK_APMIXED_NET2PLL), APMIXED_PARENT(CK_APMIXED_MMPLL),
> - TOP_PARENT(CK_TOP_NET1PLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D5),
> + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NETSYSPLL),
> + APMIXED_PARENT(CLK_APMIXED_NET2PLL), APMIXED_PARENT(CLK_APMIXED_MMPLL),
> + TOP_PARENT(CLK_TOP_NET1PLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D5),
> };
>
> static const struct mtk_parent axi_infra_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
> };
>
> static const struct mtk_parent uart_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D8),
> - TOP_PARENT(CK_TOP_MPLL_D8_D2),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8),
> + TOP_PARENT(CLK_TOP_MPLL_D8_D2),
> };
>
> static const struct mtk_parent emmc_250m_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
> - TOP_PARENT(CK_TOP_MMPLL_D4),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
> + TOP_PARENT(CLK_TOP_MMPLL_D4),
> };
>
> static const struct mtk_parent emmc_400m_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_MSDCPLL),
> - TOP_PARENT(CK_TOP_MMPLL_D2), TOP_PARENT(CK_TOP_MPLL_D2),
> - TOP_PARENT(CK_TOP_MMPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
> + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MSDCPLL),
> + TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_MPLL_D2),
> + TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
> };
>
> static const struct mtk_parent spi_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
> - TOP_PARENT(CK_TOP_MMPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
> - TOP_PARENT(CK_TOP_NET2PLL_D6), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
> - TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
> + TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
> + TOP_PARENT(CLK_TOP_NET2PLL_D6), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
> + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
> };
>
> static const struct mtk_parent nfi1x_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D4),
> - TOP_PARENT(CK_TOP_NET1PLL_D8_D2), TOP_PARENT(CK_TOP_NET2PLL_D6),
> - TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_MMPLL_D8),
> - TOP_PARENT(CK_TOP_NET1PLL_D8_D4), TOP_PARENT(CK_TOP_MPLL_D8),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4),
> + TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D6),
> + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8),
> + TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), TOP_PARENT(CLK_TOP_MPLL_D8),
> };
>
> static const struct mtk_parent spinfi_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_XTAL),
> - TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
> - TOP_PARENT(CK_TOP_MMPLL_D8), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
> - TOP_PARENT(CK_TOP_MMPLL_D6_D2), TOP_PARENT(CK_TOP_MPLL_D8),
> + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL),
> + TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
> + TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
> + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_MPLL_D8),
> };
>
> static const struct mtk_parent pwm_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
> - TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
> - TOP_PARENT(CK_TOP_MPLL_D8_D2), TOP_PARENT(CK_TOP_RTC_32K),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
> + TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
> + TOP_PARENT(CLK_TOP_MPLL_D8_D2), TOP_PARENT(CLK_TOP_RTC_32K),
> };
>
> static const struct mtk_parent i2c_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
> - TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
> + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
> };
>
> static const struct mtk_parent pcie_mbist_250m_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
> };
>
> static const struct mtk_parent pextp_tl_ck_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D6),
> - TOP_PARENT(CK_TOP_MMPLL_D8), TOP_PARENT(CK_TOP_MPLL_D8_D2),
> - TOP_PARENT(CK_TOP_RTC_32K),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D6),
> + TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
> + TOP_PARENT(CLK_TOP_RTC_32K),
> };
>
> static const struct mtk_parent usb_frmcnt_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D3_D5),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D3_D5),
> };
>
> static const struct mtk_parent aud_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_APLL2),
> + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
> };
>
> static const struct mtk_parent a1sys_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_APLL2_D4),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
> };
>
> static const struct mtk_parent aud_l_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_APLL2),
> - TOP_PARENT(CK_TOP_MPLL_D8_D2),
> + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
> + TOP_PARENT(CLK_TOP_MPLL_D8_D2),
> };
>
> static const struct mtk_parent sspxtp_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_MPLL_D8_D2),
> + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
> };
>
> static const struct mtk_parent usxgmii_sbus_0_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
> };
>
> static const struct mtk_parent sgm_0_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_SGMPLL),
> + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
> };
>
> static const struct mtk_parent sysapb_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D3_D2),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2),
> };
>
> static const struct mtk_parent eth_refck_50m_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D4_D4),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4_D4),
> };
>
> static const struct mtk_parent eth_sys_200m_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D4),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4),
> };
>
> static const struct mtk_parent eth_xgmii_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_NET1PLL_D8_D8),
> - TOP_PARENT(CK_TOP_NET1PLL_D8_D16),
> + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D8_D8),
> + TOP_PARENT(CLK_TOP_NET1PLL_D8_D16),
> };
>
> static const struct mtk_parent bus_tops_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5),
> - TOP_PARENT(CK_TOP_NET2PLL_D2),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
> + TOP_PARENT(CLK_TOP_NET2PLL_D2),
> };
>
> static const struct mtk_parent npu_tops_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
> + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
> };
>
> static const struct mtk_parent dramc_md32_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
> - APMIXED_PARENT(CK_APMIXED_WEDMCUPLL),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
> + APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL),
> };
>
> static const struct mtk_parent da_xtp_glb_p0_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D8),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D8),
> };
>
> static const struct mtk_parent mcusys_backup_625m_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D4),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
> };
>
> static const struct mtk_parent macsec_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_SGMPLL),
> - TOP_PARENT(CK_TOP_NET1PLL_D8),
> + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
> + TOP_PARENT(CLK_TOP_NET1PLL_D8),
> };
>
> static const struct mtk_parent netsys_tops_400m_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D2),
> + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2),
> };
>
> static const struct mtk_parent eth_mii_parents[] = {
> - TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_NET2PLL_D4_D8),
> + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET2PLL_D4_D8),
> };
>
> #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
> @@ -287,197 +287,197 @@ static const struct mtk_parent eth_mii_parents[] = {
>
> /* TOPCKGEN MUX_GATE */
> static const struct mtk_composite topckgen_mtk_muxes[] = {
> - TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
> + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
> 0, 2, 7, 0x1c0, 0),
> - TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
> + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
> 0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1),
> - TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
> + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
> 0x4, 0x8, 16, 2, 23, 0x1c0, 2),
> - TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
> + TOP_MUX(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
> 0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3),
> - TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
> + TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
> 0x14, 0x18, 0, 1, 7, 0x1c0, 4),
> - TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
> + TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
> 0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5),
> - TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
> + TOP_MUX(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
> netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6),
> - TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
> + TOP_MUX(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
> 0x18, 24, 3, 31, 0x1c0, 7),
> - TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
> + TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
> 0x24, 0x28, 0, 1, 7, 0x1c0, 8),
> - TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
> + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
> 2, 15, 0x1c0, 9),
> - TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
> + TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
> 0x24, 0x28, 16, 2, 23, 0x1c0, 10),
> - TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
> + TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
> 0x24, 0x28, 24, 3, 31, 0x1c0, 11),
> - TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
> + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
> 7, 0x1c0, 12),
> - TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
> + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
> 0x38, 8, 3, 15, 0x1c0, 13),
> - TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
> + TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
> 16, 3, 23, 0x1c0, 14),
> - TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
> + TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
> 0x38, 24, 3, 31, 0x1c0, 15),
> - TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
> + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
> 7, 0x1c0, 16),
> - TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
> + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
> 15, 0x1c0, 17),
> - TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
> + TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
> pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0,
> 18),
> - TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
> + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
> 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
> - TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
> + TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
> pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20),
> - TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
> + TOP_MUX(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
> pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21),
> - TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
> + TOP_MUX(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
> pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22),
> - TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
> + TOP_MUX(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
> 0x58, 24, 1, 31, 0x1c0, 23),
> - TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
> + TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
> 0x64, 0x68, 0, 1, 7, 0x1c0, 24),
> - TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
> + TOP_MUX(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
> 0x64, 0x68, 8, 1, 15, 0x1c0, 25),
> - TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
> + TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
> 0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26),
> - TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
> + TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
> 0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27),
> - TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
> + TOP_MUX(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
> usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28),
> - TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
> + TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
> 15, 0x1c0, 29),
> - TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
> + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
> 16, 1, 23, 0x1c0, 30),
> - TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
> + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
> 24, 2, 31, 0x1c4, 0),
> - TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
> + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
> 0x88, 0, 1, 7, 0x1c4, 1),
> - TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
> + TOP_MUX(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
> 0x88, 8, 1, 15, 0x1c4, 2),
> - TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
> + TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
> 0x88, 16, 1, 23, 0x1c4, 3),
> - TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
> + TOP_MUX(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
> usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4),
> - TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
> + TOP_MUX(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
> usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5),
> - TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
> + TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
> 8, 1, 15, 0x1c4, 6),
> - TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
> + TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
> 0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7),
> - TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
> + TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
> 24, 1, 31, 0x1c4, 8),
> - TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
> + TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
> 0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9),
> - TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
> + TOP_MUX(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
> 0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10),
> - TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
> + TOP_MUX(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
> 0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11),
> - TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
> + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
> 0xa8, 24, 1, 31, 0x1c4, 12),
> - TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
> + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
> 0xb8, 0, 1, 7, 0x1c4, 13),
> - TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
> + TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
> eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14),
> - TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
> + TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
> eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15),
> - TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
> + TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
> 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16),
> - TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
> + TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
> 0xc4, 0xc8, 0, 2, 7, 0x1c4, 17),
> - TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
> + TOP_MUX(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
> 0xc4, 0xc8, 8, 2, 15, 0x1c4, 18),
> - TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
> + TOP_MUX(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
> 0xc4, 0xc8, 16, 1, 23, 0x1c4, 19),
> - TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
> + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
> 24, 1, 31, 0x1c4, 20),
> - TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
> + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
> 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21),
> - TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
> + TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
> 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22),
> - TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
> + TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
> 0xd8, 16, 1, 23, 0x1c4, 23),
> - TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
> + TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
> 0xd8, 24, 1, 31, 0x1c4, 24),
> - TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
> + TOP_MUX(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
> 0xe8, 0, 1, 7, 0x1c4, 25),
> - TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
> + TOP_MUX(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
> 0xe8, 8, 1, 15, 0x1c4, 26),
> - TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
> + TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
> da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27),
> - TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
> + TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
> da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28),
> - TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
> + TOP_MUX(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
> da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29),
> - TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
> + TOP_MUX(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
> da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
> - TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
> + TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
> 1, 23, 0x1c8, 0),
> - TOP_MUX(CK_TOP_DA_SEL, "da_sel", sspxtp_parents,
> + TOP_MUX(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents,
> 0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
> - TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
> + TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
> 0x108, 0, 1, 7, 0x1c8, 2),
> - TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
> + TOP_MUX(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
> 0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3),
> - TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
> + TOP_MUX(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
> mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23,
> 0x1c8, 4),
> - TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
> + TOP_MUX(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
> pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8,
> 5),
> - TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
> + TOP_MUX(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
> 0x118, 0, 2, 7, 0x1c8, 6),
> - TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
> + TOP_MUX(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
> netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8,
> 7),
> - TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
> + TOP_MUX(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
> pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8,
> 8),
> - TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
> + TOP_MUX(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
> 0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
> - TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
> + TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
> 0x124, 0x128, 0, 1, 7, 0x1c8, 10),
> - TOP_MUX(CK_TOP_NPU_SEL, "ck_npu_sel",
> + TOP_MUX(CLK_TOP_NPU_SEL, "ck_npu_sel",
> netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
> };
>
> /* INFRASYS MUX PARENTS */
> -static const int infra_mux_uart0_parents[] = { CK_TOP_INFRA_F26M_SEL,
> - CK_TOP_UART_SEL };
> +static const int infra_mux_uart0_parents[] = { CLK_TOP_INFRA_F26M_SEL,
> + CLK_TOP_UART_SEL };
>
> -static const int infra_mux_uart1_parents[] = { CK_TOP_INFRA_F26M_SEL,
> - CK_TOP_UART_SEL };
> +static const int infra_mux_uart1_parents[] = { CLK_TOP_INFRA_F26M_SEL,
> + CLK_TOP_UART_SEL };
>
> -static const int infra_mux_uart2_parents[] = { CK_TOP_INFRA_F26M_SEL,
> - CK_TOP_UART_SEL };
> +static const int infra_mux_uart2_parents[] = { CLK_TOP_INFRA_F26M_SEL,
> + CLK_TOP_UART_SEL };
>
> -static const int infra_mux_spi0_parents[] = { CK_TOP_I2C_SEL, CK_TOP_SPI_SEL };
> +static const int infra_mux_spi0_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPI_SEL };
>
> -static const int infra_mux_spi1_parents[] = { CK_TOP_I2C_SEL, CK_TOP_SPIM_MST_SEL };
> +static const int infra_mux_spi1_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPIM_MST_SEL };
>
> -static const int infra_pwm_bck_parents[] = { CK_TOP_RTC_32P7K,
> - CK_TOP_INFRA_F26M_SEL, CK_TOP_SYSAXI_SEL,
> - CK_TOP_PWM_SEL };
> +static const int infra_pwm_bck_parents[] = { CLK_TOP_RTC_32P7K,
> + CLK_TOP_INFRA_F26M_SEL, CLK_TOP_SYSAXI_SEL,
> + CLK_TOP_PWM_SEL };
>
> static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
> - CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
> - CK_TOP_PEXTP_TL_SEL
> + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
> + CLK_TOP_PEXTP_TL_SEL
> };
>
> static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
> - CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
> - CK_TOP_PEXTP_TL_P1_SEL
> + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
> + CLK_TOP_PEXTP_TL_P1_SEL
> };
>
> static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
> - CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
> - CK_TOP_PEXTP_TL_P2_SEL
> + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
> + CLK_TOP_PEXTP_TL_P2_SEL
> };
>
> static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
> - CK_TOP_RTC_32P7K, CK_TOP_INFRA_F26M_SEL, CK_TOP_INFRA_F26M_SEL,
> - CK_TOP_PEXTP_TL_P3_SEL
> + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
> + CLK_TOP_PEXTP_TL_P3_SEL
> };
>
> #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
> @@ -491,46 +491,46 @@ static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
>
> /* INFRA MUX */
> static const struct mtk_composite infracfg_mtk_mux[] = {
> - INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
> + INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
> infra_mux_uart0_parents, 0x10, 0, 1),
> - INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
> + INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
> infra_mux_uart1_parents, 0x10, 1, 1),
> - INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
> + INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
> infra_mux_uart2_parents, 0x10, 2, 1),
> - INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
> + INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
> infra_mux_spi0_parents, 0x10, 4, 1),
> - INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
> + INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
> infra_mux_spi1_parents, 0x10, 5, 1),
> - INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
> + INFRA_MUX(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
> infra_mux_spi0_parents, 0x10, 6, 1),
> - INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
> + INFRA_MUX(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
> 0x10, 14, 2),
> - INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
> + INFRA_MUX(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
> infra_pwm_bck_parents, 0x10, 16, 2),
> - INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
> + INFRA_MUX(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
> infra_pwm_bck_parents, 0x10, 18, 2),
> - INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
> + INFRA_MUX(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
> infra_pwm_bck_parents, 0x10, 20, 2),
> - INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
> + INFRA_MUX(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
> infra_pwm_bck_parents, 0x10, 22, 2),
> - INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
> + INFRA_MUX(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
> infra_pwm_bck_parents, 0x10, 24, 2),
> - INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
> + INFRA_MUX(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
> infra_pwm_bck_parents, 0x10, 26, 2),
> - INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
> + INFRA_MUX(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
> infra_pwm_bck_parents, 0x10, 28, 2),
> - INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
> + INFRA_MUX(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
> infra_pwm_bck_parents, 0x10, 30, 2),
> - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
> + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
> "infra_pcie_gfmux_tl_o_p0_sel",
> infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2),
> - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
> + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
> "infra_pcie_gfmux_tl_o_p1_sel",
> infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2),
> - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
> + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
> "infra_pcie_gfmux_tl_o_p2_sel",
> infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2),
> - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
> + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
> "infra_pcie_gfmux_tl_o_p3_sel",
> infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2),
> };
> @@ -607,166 +607,166 @@ static const struct mtk_gate_regs infra_3_cg_regs = {
>
> /* INFRA GATE */
> static const struct mtk_gate infracfg_mtk_gates[] = {
> - GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P0,
> - "infra_pcie_peri_ck_26m_ck_p0", CK_TOP_INFRA_F26M_SEL, 7),
> - GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P1,
> - "infra_pcie_peri_ck_26m_ck_p1", CK_TOP_INFRA_F26M_SEL, 8),
> - GATE_INFRA0_INFRA(CK_INFRA_PCIE_PERI_26M_CK_P2,
> - "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_PCIE_PERI_26M_CK_P3, 9),
> - GATE_INFRA0_TOP(CK_INFRA_PCIE_PERI_26M_CK_P3,
> - "infra_pcie_peri_ck_26m_ck_p3", CK_TOP_INFRA_F26M_SEL, 10),
> - GATE_INFRA1_TOP(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
> - CK_TOP_SYSAXI_SEL, 0),
> - GATE_INFRA1_TOP(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
> - CK_TOP_SYSAXI_SEL, 1),
> - GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
> - CK_INFRA_PWM_SEL, 2),
> - GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
> - CK_INFRA_PWM_CK1_SEL, 3),
> - GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
> - CK_INFRA_PWM_CK2_SEL, 4),
> - GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
> - CK_INFRA_PWM_CK3_SEL, 5),
> - GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
> - CK_INFRA_PWM_CK4_SEL, 6),
> - GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
> - CK_INFRA_PWM_CK5_SEL, 7),
> - GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
> - CK_INFRA_PWM_CK6_SEL, 8),
> - GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
> - CK_INFRA_PWM_CK7_SEL, 9),
> - GATE_INFRA1_INFRA(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
> - CK_INFRA_PWM_CK8_SEL, 10),
> - GATE_INFRA1_TOP(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
> - CK_TOP_SYSAXI_SEL, 12),
> - GATE_INFRA1_TOP(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
> - CK_TOP_SYSAXI_SEL, 13),
> - GATE_INFRA1_TOP(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_TOP_INFRA_F26M_SEL, 14),
> - GATE_INFRA1_TOP(CK_INFRA_AUD_L, "infra_f_faud_l", CK_TOP_AUD_L_SEL, 15),
> - GATE_INFRA1_TOP(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_TOP_A1SYS_SEL,
> + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0,
> + "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7),
> + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1,
> + "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8),
> + GATE_INFRA0_INFRA(CLK_INFRA_PCIE_PERI_26M_CK_P2,
> + "infra_pcie_peri_ck_26m_ck_p2", CLK_INFRA_PCIE_PERI_26M_CK_P3, 9),
> + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P3,
> + "infra_pcie_peri_ck_26m_ck_p3", CLK_TOP_INFRA_F26M_SEL, 10),
> + GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
> + CLK_TOP_SYSAXI_SEL, 0),
> + GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
> + CLK_TOP_SYSAXI_SEL, 1),
> + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
> + CLK_INFRA_PWM_SEL, 2),
> + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
> + CLK_INFRA_PWM_CK1_SEL, 3),
> + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
> + CLK_INFRA_PWM_CK2_SEL, 4),
> + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
> + CLK_INFRA_PWM_CK3_SEL, 5),
> + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
> + CLK_INFRA_PWM_CK4_SEL, 6),
> + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
> + CLK_INFRA_PWM_CK5_SEL, 7),
> + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
> + CLK_INFRA_PWM_CK6_SEL, 8),
> + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
> + CLK_INFRA_PWM_CK7_SEL, 9),
> + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
> + CLK_INFRA_PWM_CK8_SEL, 10),
> + GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
> + CLK_TOP_SYSAXI_SEL, 12),
> + GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
> + CLK_TOP_SYSAXI_SEL, 13),
> + GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m", CLK_TOP_INFRA_F26M_SEL, 14),
> + GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15),
> + GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL,
> 16),
> - GATE_INFRA1_TOP(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_TOP_A_TUNER_SEL,
> + GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", CLK_TOP_A_TUNER_SEL,
> 18),
> - GATE_INFRA1_TOP(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_TOP_INFRA_F26M_SEL,
> + GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CLK_TOP_INFRA_F26M_SEL,
> 19),
> - GATE_INFRA1_TOP(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
> - CK_TOP_SYSAXI_SEL, 20),
> - GATE_INFRA1_TOP(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
> - CK_TOP_SYSAXI_SEL, 21),
> - GATE_INFRA1_TOP(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
> - CK_TOP_SYSAXI_SEL, 29),
> - GATE_INFRA1_TOP(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
> - CK_TOP_INFRA_F26M_SEL, 30),
> - /* GATE_INFRA1_TOP(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_TOP_SYSAXI_SEL,
> + GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
> + CLK_TOP_SYSAXI_SEL, 20),
> + GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
> + CLK_TOP_SYSAXI_SEL, 21),
> + GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
> + CLK_TOP_SYSAXI_SEL, 29),
> + GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
> + CLK_TOP_INFRA_F26M_SEL, 30),
> + /* GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", CLK_TOP_SYSAXI_SEL,
> 31), */
> - GATE_INFRA2_TOP(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
> - CK_TOP_INFRA_F26M_SEL, 0),
> - GATE_INFRA2_TOP(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_TOP_I2C_SEL, 1),
> - /* GATE_INFRA2_TOP(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
> - CK_TOP_SYSAXI_SEL, 3), */
> - /* GATE_INFRA2_TOP(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
> - CK_TOP_SYSAXI_SEL, 4), */
> - /* GATE_INFRA2_TOP(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
> - CK_TOP_SYSAXI_SEL, 5), */
> - GATE_INFRA2_INFRA(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
> - CK_INFRA_MUX_UART0_SEL, 3),
> - GATE_INFRA2_INFRA(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
> - CK_INFRA_MUX_UART1_SEL, 4),
> - GATE_INFRA2_INFRA(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
> - CK_INFRA_MUX_UART2_SEL, 5),
> - GATE_INFRA2_TOP(CK_INFRA_NFI, "infra_f_fnfi", CK_TOP_NFI1X_SEL, 9),
> - GATE_INFRA2_TOP(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_TOP_SPINFI_SEL, 10),
> - GATE_INFRA2_TOP(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
> - CK_TOP_SYSAXI_SEL, 11),
> - GATE_INFRA2_INFRA(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
> - CK_INFRA_MUX_SPI0_SEL, 12),
> - GATE_INFRA2_INFRA(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
> - CK_INFRA_MUX_SPI1_SEL, 13),
> - GATE_INFRA2_INFRA(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
> - CK_INFRA_MUX_SPI2_SEL, 14),
> - GATE_INFRA2_TOP(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
> - CK_TOP_SYSAXI_SEL, 15),
> - GATE_INFRA2_TOP(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
> - CK_TOP_SYSAXI_SEL, 16),
> - GATE_INFRA2_TOP(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
> - CK_TOP_SYSAXI_SEL, 17),
> - GATE_INFRA2_TOP(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
> - CK_TOP_SYSAXI_SEL, 18),
> - GATE_INFRA2_TOP(CK_INFRA_RTC, "infra_f_frtc", CK_TOP_RTC_32K, 19),
> - GATE_INFRA2_TOP(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
> - CK_TOP_INFRA_F26M_SEL, 20),
> - GATE_INFRA2_INFRA(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
> + GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
> + CLK_TOP_INFRA_F26M_SEL, 0),
> + GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1),
> + /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
> + CLK_TOP_SYSAXI_SEL, 3), */
> + /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
> + CLK_TOP_SYSAXI_SEL, 4), */
> + /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
> + CLK_TOP_SYSAXI_SEL, 5), */
> + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
> + CLK_INFRA_MUX_UART0_SEL, 3),
> + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
> + CLK_INFRA_MUX_UART1_SEL, 4),
> + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
> + CLK_INFRA_MUX_UART2_SEL, 5),
> + GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI1X_SEL, 9),
> + GATE_INFRA2_TOP(CLK_INFRA_SPINFI, "infra_f_fspinfi", CLK_TOP_SPINFI_SEL, 10),
> + GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
> + CLK_TOP_SYSAXI_SEL, 11),
> + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
> + CLK_INFRA_MUX_SPI0_SEL, 12),
> + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
> + CLK_INFRA_MUX_SPI1_SEL, 13),
> + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
> + CLK_INFRA_MUX_SPI2_SEL, 14),
> + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
> + CLK_TOP_SYSAXI_SEL, 15),
> + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
> + CLK_TOP_SYSAXI_SEL, 16),
> + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
> + CLK_TOP_SYSAXI_SEL, 17),
> + GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
> + CLK_TOP_SYSAXI_SEL, 18),
> + GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_RTC_32K, 19),
> + GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
> + CLK_TOP_INFRA_F26M_SEL, 20),
> + GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc", CLK_INFRA_26M_ADC_BCK,
> 21),
> - GATE_INFRA2_TOP(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_TOP_EMMC_400M_SEL,
> + GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400", CLK_TOP_EMMC_400M_SEL,
> 22),
> - GATE_INFRA2_TOP(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
> - CK_TOP_EMMC_250M_SEL, 23),
> - GATE_INFRA2_TOP(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
> - CK_TOP_SYSAXI_SEL, 24),
> - GATE_INFRA2_TOP(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
> - CK_TOP_SYSAXI_SEL, 25),
> - GATE_INFRA2_TOP(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
> - CK_TOP_SYSAXI_SEL, 26),
> - GATE_INFRA2_TOP(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_TOP_NFI1X_SEL,
> + GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
> + CLK_TOP_EMMC_250M_SEL, 23),
> + GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
> + CLK_TOP_SYSAXI_SEL, 24),
> + GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
> + CLK_TOP_SYSAXI_SEL, 25),
> + GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
> + CLK_TOP_SYSAXI_SEL, 26),
> + GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CLK_TOP_NFI1X_SEL,
> 27),
> - GATE_INFRA2_TOP(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
> - CK_TOP_SYSAXI_SEL, 29),
> - GATE_INFRA2_TOP(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
> - CK_TOP_SYSAXI_SEL, 31),
> - GATE_INFRA3_TOP(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
> - CK_TOP_SYSAXI_SEL, 0),
> - GATE_INFRA3_TOP(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
> - CK_TOP_SYSAXI_SEL, 1),
> - GATE_INFRA3_TOP(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
> - CK_TOP_SYSAXI_SEL, 2),
> - GATE_INFRA3_TOP(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
> - CK_TOP_SYSAXI_SEL, 3),
> - GATE_INFRA3_TOP(CK_INFRA_USB_SYS, "infra_usb_sys", CK_TOP_USB_SYS_SEL, 4),
> - GATE_INFRA3_TOP(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
> - CK_TOP_USB_SYS_P1_SEL, 5),
> - GATE_INFRA3_XTAL(CK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6),
> - GATE_INFRA3_XTAL(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL,
> + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
> + CLK_TOP_SYSAXI_SEL, 29),
> + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
> + CLK_TOP_SYSAXI_SEL, 31),
> + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
> + CLK_TOP_SYSAXI_SEL, 0),
> + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
> + CLK_TOP_SYSAXI_SEL, 1),
> + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
> + CLK_TOP_SYSAXI_SEL, 2),
> + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
> + CLK_TOP_SYSAXI_SEL, 3),
> + GATE_INFRA3_TOP(CLK_INFRA_USB_SYS, "infra_usb_sys", CLK_TOP_USB_SYS_SEL, 4),
> + GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
> + CLK_TOP_USB_SYS_P1_SEL, 5),
> + GATE_INFRA3_XTAL(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6),
> + GATE_INFRA3_XTAL(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL,
> 7),
> - GATE_INFRA3_TOP(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
> - CK_TOP_USB_FRMCNT_SEL, 8),
> - GATE_INFRA3_TOP(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
> - CK_TOP_USB_FRMCNT_P1_SEL, 9),
> - GATE_INFRA3_XTAL(CK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL,
> + GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
> + CLK_TOP_USB_FRMCNT_SEL, 8),
> + GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
> + CLK_TOP_USB_FRMCNT_P1_SEL, 9),
> + GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL,
> 10),
> - GATE_INFRA3_XTAL(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
> + GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
> CLK_XTAL, 11),
> - GATE_INFRA3_XTAL(CK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL,
> + GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL,
> 12),
> - GATE_INFRA3_XTAL(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
> + GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
> CLK_XTAL, 13),
> - GATE_INFRA3_TOP(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_TOP_USB_XHCI_SEL,
> + GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI, "infra_usb_xhci", CLK_TOP_USB_XHCI_SEL,
> 14),
> - GATE_INFRA3_TOP(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
> - CK_TOP_USB_XHCI_P1_SEL, 15),
> - GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
> - CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
> - GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
> - CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
> - GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
> - CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
> - GATE_INFRA3_INFRA(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
> - CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
> - GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
> + GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
> + CLK_TOP_USB_XHCI_P1_SEL, 15),
> + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
> + CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
> + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
> + CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
> + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
> + CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
> + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
> + CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
> + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
> CLK_XTAL, 24),
> - GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
> + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
> CLK_XTAL, 25),
> - GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
> + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
> CLK_XTAL, 26),
> - GATE_INFRA3_XTAL(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
> + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
> CLK_XTAL, 27),
> - GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
> - CK_TOP_SYSAXI_SEL, 28),
> - GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
> - CK_TOP_SYSAXI_SEL, 29),
> - GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
> - CK_TOP_SYSAXI_SEL, 30),
> - GATE_INFRA3_TOP(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
> - CK_TOP_SYSAXI_SEL, 31),
> + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
> + CLK_TOP_SYSAXI_SEL, 28),
> + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
> + CLK_TOP_SYSAXI_SEL, 29),
> + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
> + CLK_TOP_SYSAXI_SEL, 30),
> + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
> + CLK_TOP_SYSAXI_SEL, 31),
> };
>
> static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
> @@ -777,8 +777,8 @@ static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
> };
>
> static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
> - .fdivs_offs = CK_TOP_XTAL_D2,
> - .muxes_offs = CK_TOP_NETSYS_SEL,
> + .fdivs_offs = CLK_TOP_XTAL_D2,
> + .muxes_offs = CLK_TOP_NETSYS_SEL,
> .fclks = topckgen_mtk_fixed_clks,
> .fdivs = topckgen_mtk_fixed_factors,
> .muxes = topckgen_mtk_muxes,
> @@ -787,8 +787,8 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
> };
>
> static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
> - .muxes_offs = CK_INFRA_MUX_UART0_SEL,
> - .gates_offs = CK_INFRA_PCIE_PERI_26M_CK_P0,
> + .muxes_offs = CLK_INFRA_MUX_UART0_SEL,
> + .gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0,
> .muxes = infracfg_mtk_mux,
> .gates = infracfg_mtk_gates,
> .flags = CLK_BYPASS_XTAL,
> @@ -879,7 +879,7 @@ static const struct mtk_gate_regs ethdma_cg_regs = {
> }
>
> static const struct mtk_gate ethdma_mtk_gate[] = {
> - GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X_SEL, 6),
> + GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6),
> };
>
> static int mt7988_ethdma_probe(struct udevice *dev)
> @@ -934,10 +934,10 @@ static const struct mtk_gate_regs sgmii0_cg_regs = {
> }
>
> static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
> - /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
> - GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_XTAL, 2),
> - /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
> - GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_XTAL, 3),
> + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
> + GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_XTAL, 2),
> + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
> + GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_XTAL, 3),
> };
>
> static int mt7988_sgmiisys_0_probe(struct udevice *dev)
> @@ -978,10 +978,10 @@ static const struct mtk_gate_regs sgmii1_cg_regs = {
> }
>
> static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
> - /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
> - GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_XTAL, 2),
> - /* connect to fake clock, so use CK_TOP_XTAL as the clock parent */
> - GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_XTAL, 3),
> + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
> + GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_XTAL, 2),
> + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
> + GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_XTAL, 3),
> };
>
> static int mt7988_sgmiisys_1_probe(struct udevice *dev)
> @@ -1022,12 +1022,12 @@ static const struct mtk_gate_regs ethwarp_cg_regs = {
> }
>
> static const struct mtk_gate ethwarp_mtk_gate[] = {
> - GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
> - CK_TOP_NETSYS_MCU_SEL, 13),
> - GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
> - CK_TOP_NETSYS_MCU_SEL, 14),
> - GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
> - CK_TOP_NETSYS_MCU_SEL, 15),
> + GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
> + CLK_TOP_NETSYS_MCU_SEL, 13),
> + GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
> + CLK_TOP_NETSYS_MCU_SEL, 14),
> + GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
> + CLK_TOP_NETSYS_MCU_SEL, 15),
> };
>
> static int mt7988_ethwarp_probe(struct udevice *dev)
> diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
> index 7c64f5f3d03..e6e6978809d 100644
> --- a/include/dt-bindings/clock/mt7988-clk.h
> +++ b/include/dt-bindings/clock/mt7988-clk.h
> @@ -10,255 +10,255 @@
>
> /* INFRACFG_AO */
> /* mtk_mux */
> -#define CK_INFRA_MUX_UART0_SEL 0
> -#define CK_INFRA_MUX_UART1_SEL 1
> -#define CK_INFRA_MUX_UART2_SEL 2
> -#define CK_INFRA_MUX_SPI0_SEL 3
> -#define CK_INFRA_MUX_SPI1_SEL 4
> -#define CK_INFRA_MUX_SPI2_SEL 5
> -#define CK_INFRA_PWM_SEL 6
> -#define CK_INFRA_PWM_CK1_SEL 7
> -#define CK_INFRA_PWM_CK2_SEL 8
> -#define CK_INFRA_PWM_CK3_SEL 9
> -#define CK_INFRA_PWM_CK4_SEL 10
> -#define CK_INFRA_PWM_CK5_SEL 11
> -#define CK_INFRA_PWM_CK6_SEL 12
> -#define CK_INFRA_PWM_CK7_SEL 13
> -#define CK_INFRA_PWM_CK8_SEL 14
> -#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
> -#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
> -#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
> -#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
> +#define CLK_INFRA_MUX_UART0_SEL 0
> +#define CLK_INFRA_MUX_UART1_SEL 1
> +#define CLK_INFRA_MUX_UART2_SEL 2
> +#define CLK_INFRA_MUX_SPI0_SEL 3
> +#define CLK_INFRA_MUX_SPI1_SEL 4
> +#define CLK_INFRA_MUX_SPI2_SEL 5
> +#define CLK_INFRA_PWM_SEL 6
> +#define CLK_INFRA_PWM_CK1_SEL 7
> +#define CLK_INFRA_PWM_CK2_SEL 8
> +#define CLK_INFRA_PWM_CK3_SEL 9
> +#define CLK_INFRA_PWM_CK4_SEL 10
> +#define CLK_INFRA_PWM_CK5_SEL 11
> +#define CLK_INFRA_PWM_CK6_SEL 12
> +#define CLK_INFRA_PWM_CK7_SEL 13
> +#define CLK_INFRA_PWM_CK8_SEL 14
> +#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
> +#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
> +#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
> +#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
>
> /* INFRACFG */
> /* mtk_gate */
> -#define CK_INFRA_PCIE_PERI_26M_CK_P0 19
> -#define CK_INFRA_PCIE_PERI_26M_CK_P1 20
> -#define CK_INFRA_PCIE_PERI_26M_CK_P2 21
> -#define CK_INFRA_PCIE_PERI_26M_CK_P3 22
> -#define CK_INFRA_66M_GPT_BCK 23
> -#define CK_INFRA_66M_PWM_HCK 24
> -#define CK_INFRA_66M_PWM_BCK 25
> -#define CK_INFRA_66M_PWM_CK1 26
> -#define CK_INFRA_66M_PWM_CK2 27
> -#define CK_INFRA_66M_PWM_CK3 28
> -#define CK_INFRA_66M_PWM_CK4 29
> -#define CK_INFRA_66M_PWM_CK5 30
> -#define CK_INFRA_66M_PWM_CK6 31
> -#define CK_INFRA_66M_PWM_CK7 32
> -#define CK_INFRA_66M_PWM_CK8 33
> -#define CK_INFRA_133M_CQDMA_BCK 34
> -#define CK_INFRA_66M_AUD_SLV_BCK 35
> -#define CK_INFRA_AUD_26M 36
> -#define CK_INFRA_AUD_L 37
> -#define CK_INFRA_AUD_AUD 38
> -#define CK_INFRA_AUD_EG2 39
> -#define CK_INFRA_DRAMC_F26M 40
> -#define CK_INFRA_133M_DBG_ACKM 41
> -#define CK_INFRA_66M_AP_DMA_BCK 42
> -#define CK_INFRA_66M_SEJ_BCK 43
> -#define CK_INFRA_PRE_CK_SEJ_F13M 44
> -/* #define CK_INFRA_66M_TRNG 44 */
> +#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
> +#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
> +#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
> +#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
> +#define CLK_INFRA_66M_GPT_BCK 23
> +#define CLK_INFRA_66M_PWM_HCK 24
> +#define CLK_INFRA_66M_PWM_BCK 25
> +#define CLK_INFRA_66M_PWM_CK1 26
> +#define CLK_INFRA_66M_PWM_CK2 27
> +#define CLK_INFRA_66M_PWM_CK3 28
> +#define CLK_INFRA_66M_PWM_CK4 29
> +#define CLK_INFRA_66M_PWM_CK5 30
> +#define CLK_INFRA_66M_PWM_CK6 31
> +#define CLK_INFRA_66M_PWM_CK7 32
> +#define CLK_INFRA_66M_PWM_CK8 33
> +#define CLK_INFRA_133M_CQDMA_BCK 34
> +#define CLK_INFRA_66M_AUD_SLV_BCK 35
> +#define CLK_INFRA_AUD_26M 36
> +#define CLK_INFRA_AUD_L 37
> +#define CLK_INFRA_AUD_AUD 38
> +#define CLK_INFRA_AUD_EG2 39
> +#define CLK_INFRA_DRAMC_F26M 40
> +#define CLK_INFRA_133M_DBG_ACKM 41
> +#define CLK_INFRA_66M_AP_DMA_BCK 42
> +#define CLK_INFRA_66M_SEJ_BCK 43
> +#define CLK_INFRA_PRE_CK_SEJ_F13M 44
> +/* #define CLK_INFRA_66M_TRNG 44 */
> #define CLK_INFRA_26M_THERM_SYSTEM 45
> #define CLK_INFRA_I2C_BCK 46
> -/* #define CK_INFRA_66M_UART0_PCK 46 */
> -/* #define CK_INFRA_66M_UART1_PCK 47 */
> -/* #define CK_INFRA_66M_UART2_PCK 48 */
> -#define CK_INFRA_52M_UART0_CK 47
> -#define CK_INFRA_52M_UART1_CK 48
> -#define CK_INFRA_52M_UART2_CK 49
> -#define CK_INFRA_NFI 50
> -#define CK_INFRA_SPINFI 51
> -#define CK_INFRA_66M_NFI_HCK 52
> -#define CK_INFRA_104M_SPI0 53
> -#define CK_INFRA_104M_SPI1 54
> -#define CK_INFRA_104M_SPI2_BCK 55
> -#define CK_INFRA_66M_SPI0_HCK 56
> -#define CK_INFRA_66M_SPI1_HCK 57
> -#define CK_INFRA_66M_SPI2_HCK 58
> -#define CK_INFRA_66M_FLASHIF_AXI 59
> -#define CK_INFRA_RTC 60
> -#define CK_INFRA_26M_ADC_BCK 61
> -#define CK_INFRA_RC_ADC 62
> -#define CK_INFRA_MSDC400 63
> -#define CK_INFRA_MSDC2_HCK 64
> -#define CK_INFRA_133M_MSDC_0_HCK 65
> -#define CK_INFRA_66M_MSDC_0_HCK 66
> -#define CK_INFRA_133M_CPUM_BCK 67
> -#define CK_INFRA_BIST2FPC 68
> -#define CK_INFRA_I2C_X16W_MCK_CK_P1 69
> -#define CK_INFRA_I2C_X16W_PCK_CK_P1 70
> -#define CK_INFRA_133M_USB_HCK 71
> -#define CK_INFRA_133M_USB_HCK_CK_P1 72
> -#define CK_INFRA_66M_USB_HCK 73
> -#define CK_INFRA_66M_USB_HCK_CK_P1 74
> -#define CK_INFRA_USB_SYS 75
> -#define CK_INFRA_USB_SYS_CK_P1 76
> -#define CK_INFRA_USB_REF 77
> -#define CK_INFRA_USB_CK_P1 78
> -#define CK_INFRA_USB_FRMCNT 79
> -#define CK_INFRA_USB_FRMCNT_CK_P1 80
> -#define CK_INFRA_USB_PIPE 81
> -#define CK_INFRA_USB_PIPE_CK_P1 82
> -#define CK_INFRA_USB_UTMI 83
> -#define CK_INFRA_USB_UTMI_CK_P1 84
> -#define CK_INFRA_USB_XHCI 85
> -#define CK_INFRA_USB_XHCI_CK_P1 86
> -#define CK_INFRA_PCIE_GFMUX_TL_P0 87
> -#define CK_INFRA_PCIE_GFMUX_TL_P1 88
> -#define CK_INFRA_PCIE_GFMUX_TL_P2 89
> -#define CK_INFRA_PCIE_GFMUX_TL_P3 90
> -#define CK_INFRA_PCIE_PIPE_P0 91
> -#define CK_INFRA_PCIE_PIPE_P1 92
> -#define CK_INFRA_PCIE_PIPE_P2 93
> -#define CK_INFRA_PCIE_PIPE_P3 94
> -#define CK_INFRA_133M_PCIE_CK_P0 95
> -#define CK_INFRA_133M_PCIE_CK_P1 96
> -#define CK_INFRA_133M_PCIE_CK_P2 97
> -#define CK_INFRA_133M_PCIE_CK_P3 98
> +/* #define CLK_INFRA_66M_UART0_PCK 46 */
> +/* #define CLK_INFRA_66M_UART1_PCK 47 */
> +/* #define CLK_INFRA_66M_UART2_PCK 48 */
> +#define CLK_INFRA_52M_UART0_CK 47
> +#define CLK_INFRA_52M_UART1_CK 48
> +#define CLK_INFRA_52M_UART2_CK 49
> +#define CLK_INFRA_NFI 50
> +#define CLK_INFRA_SPINFI 51
> +#define CLK_INFRA_66M_NFI_HCK 52
> +#define CLK_INFRA_104M_SPI0 53
> +#define CLK_INFRA_104M_SPI1 54
> +#define CLK_INFRA_104M_SPI2_BCK 55
> +#define CLK_INFRA_66M_SPI0_HCK 56
> +#define CLK_INFRA_66M_SPI1_HCK 57
> +#define CLK_INFRA_66M_SPI2_HCK 58
> +#define CLK_INFRA_66M_FLASHIF_AXI 59
> +#define CLK_INFRA_RTC 60
> +#define CLK_INFRA_26M_ADC_BCK 61
> +#define CLK_INFRA_RC_ADC 62
> +#define CLK_INFRA_MSDC400 63
> +#define CLK_INFRA_MSDC2_HCK 64
> +#define CLK_INFRA_133M_MSDC_0_HCK 65
> +#define CLK_INFRA_66M_MSDC_0_HCK 66
> +#define CLK_INFRA_133M_CPUM_BCK 67
> +#define CLK_INFRA_BIST2FPC 68
> +#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
> +#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
> +#define CLK_INFRA_133M_USB_HCK 71
> +#define CLK_INFRA_133M_USB_HCK_CK_P1 72
> +#define CLK_INFRA_66M_USB_HCK 73
> +#define CLK_INFRA_66M_USB_HCK_CK_P1 74
> +#define CLK_INFRA_USB_SYS 75
> +#define CLK_INFRA_USB_SYS_CK_P1 76
> +#define CLK_INFRA_USB_REF 77
> +#define CLK_INFRA_USB_CK_P1 78
> +#define CLK_INFRA_USB_FRMCNT 79
> +#define CLK_INFRA_USB_FRMCNT_CK_P1 80
> +#define CLK_INFRA_USB_PIPE 81
> +#define CLK_INFRA_USB_PIPE_CK_P1 82
> +#define CLK_INFRA_USB_UTMI 83
> +#define CLK_INFRA_USB_UTMI_CK_P1 84
> +#define CLK_INFRA_USB_XHCI 85
> +#define CLK_INFRA_USB_XHCI_CK_P1 86
> +#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
> +#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
> +#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
> +#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
> +#define CLK_INFRA_PCIE_PIPE_P0 91
> +#define CLK_INFRA_PCIE_PIPE_P1 92
> +#define CLK_INFRA_PCIE_PIPE_P2 93
> +#define CLK_INFRA_PCIE_PIPE_P3 94
> +#define CLK_INFRA_133M_PCIE_CK_P0 95
> +#define CLK_INFRA_133M_PCIE_CK_P1 96
> +#define CLK_INFRA_133M_PCIE_CK_P2 97
> +#define CLK_INFRA_133M_PCIE_CK_P3 98
>
> /* TOPCKGEN */
> /* mtk_fixed_clk */
> -#define CK_TOP_XTAL 0
> +#define CLK_TOP_XTAL 0
> /* mtk_fixed_factor */
> -#define CK_TOP_XTAL_D2 1
> -#define CK_TOP_RTC_32K 2
> -#define CK_TOP_RTC_32P7K 3
> -#define CK_TOP_MPLL_D2 4
> -#define CK_TOP_MPLL_D3_D2 5
> -#define CK_TOP_MPLL_D4 6
> -#define CK_TOP_MPLL_D8 7
> -#define CK_TOP_MPLL_D8_D2 8
> -#define CK_TOP_MMPLL_D2 9
> -#define CK_TOP_MMPLL_D3_D5 10
> -#define CK_TOP_MMPLL_D4 11
> -#define CK_TOP_MMPLL_D6_D2 12
> -#define CK_TOP_MMPLL_D8 13
> -#define CK_TOP_APLL2_D4 14
> -#define CK_TOP_NET1PLL_D4 15
> -#define CK_TOP_NET1PLL_D5 16
> -#define CK_TOP_NET1PLL_D5_D2 17
> -#define CK_TOP_NET1PLL_D5_D4 18
> -#define CK_TOP_NET1PLL_D8 19
> -#define CK_TOP_NET1PLL_D8_D2 20
> -#define CK_TOP_NET1PLL_D8_D4 21
> -#define CK_TOP_NET1PLL_D8_D8 22
> -#define CK_TOP_NET1PLL_D8_D16 23
> -#define CK_TOP_NET2PLL_D2 24
> -#define CK_TOP_NET2PLL_D4 25
> -#define CK_TOP_NET2PLL_D4_D4 26
> -#define CK_TOP_NET2PLL_D4_D8 27
> -#define CK_TOP_NET2PLL_D6 28
> -#define CK_TOP_NET2PLL_D8 29
> +#define CLK_TOP_XTAL_D2 1
> +#define CLK_TOP_RTC_32K 2
> +#define CLK_TOP_RTC_32P7K 3
> +#define CLK_TOP_MPLL_D2 4
> +#define CLK_TOP_MPLL_D3_D2 5
> +#define CLK_TOP_MPLL_D4 6
> +#define CLK_TOP_MPLL_D8 7
> +#define CLK_TOP_MPLL_D8_D2 8
> +#define CLK_TOP_MMPLL_D2 9
> +#define CLK_TOP_MMPLL_D3_D5 10
> +#define CLK_TOP_MMPLL_D4 11
> +#define CLK_TOP_MMPLL_D6_D2 12
> +#define CLK_TOP_MMPLL_D8 13
> +#define CLK_TOP_APLL2_D4 14
> +#define CLK_TOP_NET1PLL_D4 15
> +#define CLK_TOP_NET1PLL_D5 16
> +#define CLK_TOP_NET1PLL_D5_D2 17
> +#define CLK_TOP_NET1PLL_D5_D4 18
> +#define CLK_TOP_NET1PLL_D8 19
> +#define CLK_TOP_NET1PLL_D8_D2 20
> +#define CLK_TOP_NET1PLL_D8_D4 21
> +#define CLK_TOP_NET1PLL_D8_D8 22
> +#define CLK_TOP_NET1PLL_D8_D16 23
> +#define CLK_TOP_NET2PLL_D2 24
> +#define CLK_TOP_NET2PLL_D4 25
> +#define CLK_TOP_NET2PLL_D4_D4 26
> +#define CLK_TOP_NET2PLL_D4_D8 27
> +#define CLK_TOP_NET2PLL_D6 28
> +#define CLK_TOP_NET2PLL_D8 29
> /* mtk_mux */
> -#define CK_TOP_NETSYS_SEL 30
> -#define CK_TOP_NETSYS_500M_SEL 31
> -#define CK_TOP_NETSYS_2X_SEL 32
> -#define CK_TOP_NETSYS_GSW_SEL 33
> -#define CK_TOP_ETH_GMII_SEL 34
> -#define CK_TOP_NETSYS_MCU_SEL 35
> -#define CK_TOP_NETSYS_PAO_2X_SEL 36
> -#define CK_TOP_EIP197_SEL 37
> -#define CK_TOP_AXI_INFRA_SEL 38
> -#define CK_TOP_UART_SEL 39
> -#define CK_TOP_EMMC_250M_SEL 40
> -#define CK_TOP_EMMC_400M_SEL 41
> -#define CK_TOP_SPI_SEL 42
> -#define CK_TOP_SPIM_MST_SEL 43
> -#define CK_TOP_NFI1X_SEL 44
> -#define CK_TOP_SPINFI_SEL 45
> -#define CK_TOP_PWM_SEL 46
> -#define CK_TOP_I2C_SEL 47
> -#define CK_TOP_PCIE_MBIST_250M_SEL 48
> -#define CK_TOP_PEXTP_TL_SEL 49
> -#define CK_TOP_PEXTP_TL_P1_SEL 50
> -#define CK_TOP_PEXTP_TL_P2_SEL 51
> -#define CK_TOP_PEXTP_TL_P3_SEL 52
> -#define CK_TOP_USB_SYS_SEL 53
> -#define CK_TOP_USB_SYS_P1_SEL 54
> -#define CK_TOP_USB_XHCI_SEL 55
> -#define CK_TOP_USB_XHCI_P1_SEL 56
> -#define CK_TOP_USB_FRMCNT_SEL 57
> -#define CK_TOP_USB_FRMCNT_P1_SEL 58
> -#define CK_TOP_AUD_SEL 59
> -#define CK_TOP_A1SYS_SEL 60
> -#define CK_TOP_AUD_L_SEL 61
> -#define CK_TOP_A_TUNER_SEL 62
> -#define CK_TOP_SSPXTP_SEL 63
> -#define CK_TOP_USB_PHY_SEL 64
> -#define CK_TOP_USXGMII_SBUS_0_SEL 65
> -#define CK_TOP_USXGMII_SBUS_1_SEL 66
> -#define CK_TOP_SGM_0_SEL 67
> -#define CK_TOP_SGM_SBUS_0_SEL 68
> -#define CK_TOP_SGM_1_SEL 69
> -#define CK_TOP_SGM_SBUS_1_SEL 70
> -#define CK_TOP_XFI_PHY_0_XTAL_SEL 71
> -#define CK_TOP_XFI_PHY_1_XTAL_SEL 72
> -#define CK_TOP_SYSAXI_SEL 73
> -#define CK_TOP_SYSAPB_SEL 74
> -#define CK_TOP_ETH_REFCK_50M_SEL 75
> -#define CK_TOP_ETH_SYS_200M_SEL 76
> -#define CK_TOP_ETH_SYS_SEL 77
> -#define CK_TOP_ETH_XGMII_SEL 78
> -#define CK_TOP_BUS_TOPS_SEL 79
> -#define CK_TOP_NPU_TOPS_SEL 80
> -#define CK_TOP_DRAMC_SEL 81
> -#define CK_TOP_DRAMC_MD32_SEL 82
> -#define CK_TOP_INFRA_F26M_SEL 83
> -#define CK_TOP_PEXTP_P0_SEL 84
> -#define CK_TOP_PEXTP_P1_SEL 85
> -#define CK_TOP_PEXTP_P2_SEL 86
> -#define CK_TOP_PEXTP_P3_SEL 87
> -#define CK_TOP_DA_XTP_GLB_P0_SEL 88
> -#define CK_TOP_DA_XTP_GLB_P1_SEL 89
> -#define CK_TOP_DA_XTP_GLB_P2_SEL 90
> -#define CK_TOP_DA_XTP_GLB_P3_SEL 91
> -#define CK_TOP_CKM_SEL 92
> -#define CK_TOP_DA_SEL 93
> -#define CK_TOP_PEXTP_SEL 94
> -#define CK_TOP_TOPS_P2_26M_SEL 95
> -#define CK_TOP_MCUSYS_BACKUP_625M_SEL 96
> -#define CK_TOP_NETSYS_SYNC_250M_SEL 97
> -#define CK_TOP_MACSEC_SEL 98
> -#define CK_TOP_NETSYS_TOPS_400M_SEL 99
> -#define CK_TOP_NETSYS_PPEFB_250M_SEL 100
> -#define CK_TOP_NETSYS_WARP_SEL 101
> -#define CK_TOP_ETH_MII_SEL 102
> -#define CK_TOP_NPU_SEL 103
> +#define CLK_TOP_NETSYS_SEL 30
> +#define CLK_TOP_NETSYS_500M_SEL 31
> +#define CLK_TOP_NETSYS_2X_SEL 32
> +#define CLK_TOP_NETSYS_GSW_SEL 33
> +#define CLK_TOP_ETH_GMII_SEL 34
> +#define CLK_TOP_NETSYS_MCU_SEL 35
> +#define CLK_TOP_NETSYS_PAO_2X_SEL 36
> +#define CLK_TOP_EIP197_SEL 37
> +#define CLK_TOP_AXI_INFRA_SEL 38
> +#define CLK_TOP_UART_SEL 39
> +#define CLK_TOP_EMMC_250M_SEL 40
> +#define CLK_TOP_EMMC_400M_SEL 41
> +#define CLK_TOP_SPI_SEL 42
> +#define CLK_TOP_SPIM_MST_SEL 43
> +#define CLK_TOP_NFI1X_SEL 44
> +#define CLK_TOP_SPINFI_SEL 45
> +#define CLK_TOP_PWM_SEL 46
> +#define CLK_TOP_I2C_SEL 47
> +#define CLK_TOP_PCIE_MBIST_250M_SEL 48
> +#define CLK_TOP_PEXTP_TL_SEL 49
> +#define CLK_TOP_PEXTP_TL_P1_SEL 50
> +#define CLK_TOP_PEXTP_TL_P2_SEL 51
> +#define CLK_TOP_PEXTP_TL_P3_SEL 52
> +#define CLK_TOP_USB_SYS_SEL 53
> +#define CLK_TOP_USB_SYS_P1_SEL 54
> +#define CLK_TOP_USB_XHCI_SEL 55
> +#define CLK_TOP_USB_XHCI_P1_SEL 56
> +#define CLK_TOP_USB_FRMCNT_SEL 57
> +#define CLK_TOP_USB_FRMCNT_P1_SEL 58
> +#define CLK_TOP_AUD_SEL 59
> +#define CLK_TOP_A1SYS_SEL 60
> +#define CLK_TOP_AUD_L_SEL 61
> +#define CLK_TOP_A_TUNER_SEL 62
> +#define CLK_TOP_SSPXTP_SEL 63
> +#define CLK_TOP_USB_PHY_SEL 64
> +#define CLK_TOP_USXGMII_SBUS_0_SEL 65
> +#define CLK_TOP_USXGMII_SBUS_1_SEL 66
> +#define CLK_TOP_SGM_0_SEL 67
> +#define CLK_TOP_SGM_SBUS_0_SEL 68
> +#define CLK_TOP_SGM_1_SEL 69
> +#define CLK_TOP_SGM_SBUS_1_SEL 70
> +#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
> +#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
> +#define CLK_TOP_SYSAXI_SEL 73
> +#define CLK_TOP_SYSAPB_SEL 74
> +#define CLK_TOP_ETH_REFCK_50M_SEL 75
> +#define CLK_TOP_ETH_SYS_200M_SEL 76
> +#define CLK_TOP_ETH_SYS_SEL 77
> +#define CLK_TOP_ETH_XGMII_SEL 78
> +#define CLK_TOP_BUS_TOPS_SEL 79
> +#define CLK_TOP_NPU_TOPS_SEL 80
> +#define CLK_TOP_DRAMC_SEL 81
> +#define CLK_TOP_DRAMC_MD32_SEL 82
> +#define CLK_TOP_INFRA_F26M_SEL 83
> +#define CLK_TOP_PEXTP_P0_SEL 84
> +#define CLK_TOP_PEXTP_P1_SEL 85
> +#define CLK_TOP_PEXTP_P2_SEL 86
> +#define CLK_TOP_PEXTP_P3_SEL 87
> +#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
> +#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
> +#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
> +#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
> +#define CLK_TOP_CKM_SEL 92
> +#define CLK_TOP_DA_SEL 93
> +#define CLK_TOP_PEXTP_SEL 94
> +#define CLK_TOP_TOPS_P2_26M_SEL 95
> +#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
> +#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
> +#define CLK_TOP_MACSEC_SEL 98
> +#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
> +#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
> +#define CLK_TOP_NETSYS_WARP_SEL 101
> +#define CLK_TOP_ETH_MII_SEL 102
> +#define CLK_TOP_NPU_SEL 103
>
> /* APMIXEDSYS */
> /* mtk_pll_data */
> -#define CK_APMIXED_NETSYSPLL 0
> -#define CK_APMIXED_MPLL 1
> -#define CK_APMIXED_MMPLL 2
> -#define CK_APMIXED_APLL2 3
> -#define CK_APMIXED_NET1PLL 4
> -#define CK_APMIXED_NET2PLL 5
> -#define CK_APMIXED_WEDMCUPLL 6
> -#define CK_APMIXED_SGMPLL 7
> -#define CK_APMIXED_ARM_B 8
> -#define CK_APMIXED_CCIPLL2_B 9
> -#define CK_APMIXED_USXGMIIPLL 10
> -#define CK_APMIXED_MSDCPLL 11
> +#define CLK_APMIXED_NETSYSPLL 0
> +#define CLK_APMIXED_MPLL 1
> +#define CLK_APMIXED_MMPLL 2
> +#define CLK_APMIXED_APLL2 3
> +#define CLK_APMIXED_NET1PLL 4
> +#define CLK_APMIXED_NET2PLL 5
> +#define CLK_APMIXED_WEDMCUPLL 6
> +#define CLK_APMIXED_SGMPLL 7
> +#define CLK_APMIXED_ARM_B 8
> +#define CLK_APMIXED_CCIPLL2_B 9
> +#define CLK_APMIXED_USXGMIIPLL 10
> +#define CLK_APMIXED_MSDCPLL 11
>
> /* ETHSYS ETH DMA */
> /* mtk_gate */
> -#define CK_ETHDMA_FE_EN 0
> +#define CLK_ETHDMA_FE_EN 0
>
> /* SGMIISYS_0 */
> /* mtk_gate */
> -#define CK_SGM0_TX_EN 0
> -#define CK_SGM0_RX_EN 1
> +#define CLK_SGM0_TX_EN 0
> +#define CLK_SGM0_RX_EN 1
>
> /* SGMIISYS_1 */
> /* mtk_gate */
> -#define CK_SGM1_TX_EN 0
> -#define CK_SGM1_RX_EN 1
> +#define CLK_SGM1_TX_EN 0
> +#define CLK_SGM1_RX_EN 1
>
> /* ETHWARP */
> /* mtk_gate */
> -#define CK_ETHWARP_WOCPU2_EN 0
> -#define CK_ETHWARP_WOCPU1_EN 1
> -#define CK_ETHWARP_WOCPU0_EN 2
> +#define CLK_ETHWARP_WOCPU2_EN 0
> +#define CLK_ETHWARP_WOCPU1_EN 1
> +#define CLK_ETHWARP_WOCPU0_EN 2
>
> #endif /* _DT_BINDINGS_CLK_MT7988_H */
> --
> 2.45.2
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
` (12 preceding siblings ...)
2024-08-03 8:33 ` [PATCH 13/13] clk: mediatek: mt7988: rename CK to CLK Christian Marangi
@ 2024-08-20 0:29 ` Tom Rini
13 siblings, 0 replies; 16+ messages in thread
From: Tom Rini @ 2024-08-20 0:29 UTC (permalink / raw)
To: Lukasz Majewski, Sean Anderson, Ryder Lee, Weijie Gao,
Chunfeng Yun, GSS_MTK_Uboot_upstream, Frank Wunderlich,
Dong Huang, u-boot, Christian Marangi
On Sat, 03 Aug 2024 10:32:49 +0200, Christian Marangi wrote:
> These are all the required patches to migrate clk and correctly support
> OF_UPSTREAM. This will align the clk index to upstream to support the same
> clk implementation with downstream and upstream DTS.
>
> Christian Marangi (13):
> clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL
> clk: mediatek: mt7988: rename TOP_DA_SELM_XTAL_SEL to TOP_DA_SEL
> clk: mediatek: mt7988: rename TOP_CK_NPU_SEL_CM_TOPS_SEL to
> TOP_NPU_SEL
> clk: mediatek: mt7988: move INFRA_PCIE_PERI_26M_CK_Px clock at top
> clk: mediatek: mt7988: fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2
> clk: mediatek: mt7988: drop 1/1 infracfg spurious factor
> clk: mediatek: mt7988: rename TOPCKGEN factor clock to upstream naming
> clk: mediatek: mt7988: reorder TOPCKGEN factor ID
> clk: mediatek: mt7988: drop 1/1 spurious factor for topckgen
> clk: mediatek: mt7988: comment out infracfg clk not defined
> clk: mediatek: mt7988: replace clock ID with upstream linux
> clk: mediatek: mt7988: convert to unified infracfg gates + muxes
> clk: mediatek: mt7988: rename CK to CLK
>
> [...]
Applied to u-boot/next, thanks!
--
Tom
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2024-08-20 0:30 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-08-03 8:32 [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Christian Marangi
2024-08-03 8:32 ` [PATCH 01/13] clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL Christian Marangi
2024-08-03 8:32 ` [PATCH 02/13] clk: mediatek: mt7988: rename TOP_DA_SELM_XTAL_SEL to TOP_DA_SEL Christian Marangi
2024-08-03 8:32 ` [PATCH 03/13] clk: mediatek: mt7988: rename TOP_CK_NPU_SEL_CM_TOPS_SEL to TOP_NPU_SEL Christian Marangi
2024-08-03 8:32 ` [PATCH 04/13] clk: mediatek: mt7988: move INFRA_PCIE_PERI_26M_CK_Px clock at top Christian Marangi
2024-08-03 8:32 ` [PATCH 05/13] clk: mediatek: mt7988: fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2 Christian Marangi
2024-08-03 8:32 ` [PATCH 06/13] clk: mediatek: mt7988: drop 1/1 infracfg spurious factor Christian Marangi
2024-08-03 8:32 ` [PATCH 07/13] clk: mediatek: mt7988: rename TOPCKGEN factor clock to upstream naming Christian Marangi
2024-08-03 8:32 ` [PATCH 08/13] clk: mediatek: mt7988: reorder TOPCKGEN factor ID Christian Marangi
2024-08-03 8:32 ` [PATCH 09/13] clk: mediatek: mt7988: drop 1/1 spurious factor for topckgen Christian Marangi
2024-08-03 8:32 ` [PATCH 10/13] clk: mediatek: mt7988: comment out infracfg clk not defined Christian Marangi
2024-08-03 8:33 ` [PATCH 11/13] clk: mediatek: mt7988: replace clock ID with upstream linux Christian Marangi
2024-08-03 8:33 ` [PATCH 12/13] clk: mediatek: mt7988: convert to unified infracfg gates + muxes Christian Marangi
2024-08-03 8:33 ` [PATCH 13/13] clk: mediatek: mt7988: rename CK to CLK Christian Marangi
2024-08-10 18:46 ` Aw: " Frank Wunderlich
2024-08-20 0:29 ` [PATCH 00/13] clk: mediatek: mt7988: clk migration for OF_UPSTREAM Tom Rini
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