From: Christian Marangi <ansuelsmth@gmail.com>
To: Tom Rini <trini@konsulko.com>, Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>,
Ryder Lee <ryder.lee@mediatek.com>,
Weijie Gao <weijie.gao@mediatek.com>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
Christian Marangi <ansuelsmth@gmail.com>,
u-boot@lists.denx.de
Subject: [PATCH 09/15] clk: mediatek: mt7986: reorder TOPCKGEN factor ID
Date: Sat, 3 Aug 2024 10:40:42 +0200 [thread overview]
Message-ID: <20240803084050.449-10-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20240803084050.449-1-ansuelsmth@gmail.com>
Reorder TOPCKGEN factor ID to put TOP_FACTOR first and then PLL. This is
to match how it's done in upstream kernel linux and in preparation for
OF_UPSTREAM support.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/mediatek/clk-mt7986.c | 70 ++++++++--------
include/dt-bindings/clock/mt7986-clk.h | 108 ++++++++++++-------------
2 files changed, 89 insertions(+), 89 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index c1f63ecc3b2..34b8eba5398 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -46,6 +46,41 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor top_fixed_divs[] = {
+ /* TOP Factors */
+ TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL,
+ 1, 2),
+ TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
+ 1250),
+ TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
+ 1220),
+ TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_XTAL, 1,
+ 1),
+ TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_XTAL, 1, 1),
+ TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_XTAL, 1, 1),
+ TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_XTAL, 1, 1),
+ TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1,
+ 1),
+ TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
+ CK_TOP_NETSYS_MCU_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
+ TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
+ 1),
/* MPLL */
PLL_FACTOR(CK_TOP_CB_MPLL_416M, "cb_mpll_416m", CK_APMIXED_MPLL, 1, 1),
PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
@@ -84,41 +119,6 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
10),
/* SGMPLL */
PLL_FACTOR(CK_TOP_CB_SGMPLL_325M, "cb_sgmpll_325m", CK_APMIXED_SGMPLL, 1, 1),
- /* TOPCKGEN and XTAL */
- TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL,
- 1, 2),
- TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
- 1250),
- TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
- 1220),
- TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_XTAL, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_XTAL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_XTAL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_XTAL, 1, 1),
- TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
- CK_TOP_NETSYS_MCU_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
- TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
- 1),
};
/* TOPCKGEN MUX PARENTS */
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index f19948cca16..0048d183389 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -16,60 +16,60 @@
/* TOPCKGEN */
#define CK_TOP_XTAL 0
-#define CK_TOP_CB_MPLL_416M 1
-#define CK_TOP_MPLL_D2 2
-#define CK_TOP_MPLL_D4 3
-#define CK_TOP_MPLL_D8 4
-#define CK_TOP_MPLL_D8_D2 5
-#define CK_TOP_MPLL_D3_D2 6
-#define CK_TOP_MMPLL_D2 7
-#define CK_TOP_MMPLL_D4 8
-#define CK_TOP_MMPLL_D8 9
-#define CK_TOP_MMPLL_D8_D2 10
-#define CK_TOP_MMPLL_D3_D8 11
-#define CK_TOP_MMPLL_U2PHYD 12
-#define CK_TOP_CB_APLL2_196M 13
-#define CK_TOP_APLL2_D4 14
-#define CK_TOP_NET1PLL_D4 15
-#define CK_TOP_NET1PLL_D5 16
-#define CK_TOP_NET1PLL_D5_D2 17
-#define CK_TOP_NET1PLL_D5_D4 18
-#define CK_TOP_NET1PLL_D8_D2 19
-#define CK_TOP_NET1PLL_D8_D4 20
-#define CK_TOP_CB_NET2PLL_800M 21
-#define CK_TOP_NET2PLL_D4 22
-#define CK_TOP_NET2PLL_D4_D2 23
-#define CK_TOP_NET2PLL_D3_D2 24
-#define CK_TOP_CB_WEDMCUPLL_760M 25
-#define CK_TOP_WEDMCUPLL_D5_D2 26
-#define CK_TOP_CB_SGMPLL_325M 27
-#define CK_TOP_XTAL_D2 28
-#define CK_TOP_RTC_32K 29
-#define CK_TOP_RTC_32P7K 30
-#define CK_TOP_NFI1X 31
-#define CK_TOP_USB_EQ_RX250M 32
-#define CK_TOP_USB_TX250M 33
-#define CK_TOP_USB_LN0_CK 34
-#define CK_TOP_USB_CDR_CK 35
-#define CK_TOP_SPINFI_BCK 36
-#define CK_TOP_I2C_BCK 37
-#define CK_TOP_PEXTP_TL 38
-#define CK_TOP_EMMC_250M 39
-#define CK_TOP_EMMC_416M 40
-#define CK_TOP_F_26M_ADC_CK 41
-#define CK_TOP_SYSAXI 42
-#define CK_TOP_NETSYS_WED_MCU 43
-#define CK_TOP_NETSYS_2X 44
-#define CK_TOP_SGM_325M 45
-#define CK_TOP_A1SYS 46
-#define CK_TOP_EIP_B 47
-#define CK_TOP_F26M 48
-#define CK_TOP_AUD_L 49
-#define CK_TOP_A_TUNER 50
-#define CK_TOP_U2U3_REF 51
-#define CK_TOP_U2U3_SYS 52
-#define CK_TOP_U2U3_XHCI 53
-#define CK_TOP_AP2CNN_HOST 54
+#define CK_TOP_XTAL_D2 1
+#define CK_TOP_RTC_32K 2
+#define CK_TOP_RTC_32P7K 3
+#define CK_TOP_NFI1X 4
+#define CK_TOP_USB_EQ_RX250M 5
+#define CK_TOP_USB_TX250M 6
+#define CK_TOP_USB_LN0_CK 7
+#define CK_TOP_USB_CDR_CK 8
+#define CK_TOP_SPINFI_BCK 9
+#define CK_TOP_I2C_BCK 10
+#define CK_TOP_PEXTP_TL 11
+#define CK_TOP_EMMC_250M 12
+#define CK_TOP_EMMC_416M 13
+#define CK_TOP_F_26M_ADC_CK 14
+#define CK_TOP_SYSAXI 15
+#define CK_TOP_NETSYS_WED_MCU 16
+#define CK_TOP_NETSYS_2X 17
+#define CK_TOP_SGM_325M 18
+#define CK_TOP_A1SYS 19
+#define CK_TOP_EIP_B 20
+#define CK_TOP_F26M 21
+#define CK_TOP_AUD_L 22
+#define CK_TOP_A_TUNER 23
+#define CK_TOP_U2U3_REF 24
+#define CK_TOP_U2U3_SYS 25
+#define CK_TOP_U2U3_XHCI 26
+#define CK_TOP_AP2CNN_HOST 27
+#define CK_TOP_CB_MPLL_416M 28
+#define CK_TOP_MPLL_D2 29
+#define CK_TOP_MPLL_D4 30
+#define CK_TOP_MPLL_D8 31
+#define CK_TOP_MPLL_D8_D2 32
+#define CK_TOP_MPLL_D3_D2 33
+#define CK_TOP_MMPLL_D2 34
+#define CK_TOP_MMPLL_D4 35
+#define CK_TOP_MMPLL_D8 36
+#define CK_TOP_MMPLL_D8_D2 37
+#define CK_TOP_MMPLL_D3_D8 38
+#define CK_TOP_MMPLL_U2PHYD 39
+#define CK_TOP_CB_APLL2_196M 40
+#define CK_TOP_APLL2_D4 41
+#define CK_TOP_NET1PLL_D4 42
+#define CK_TOP_NET1PLL_D5 43
+#define CK_TOP_NET1PLL_D5_D2 44
+#define CK_TOP_NET1PLL_D5_D4 45
+#define CK_TOP_NET1PLL_D8_D2 46
+#define CK_TOP_NET1PLL_D8_D4 47
+#define CK_TOP_CB_NET2PLL_800M 48
+#define CK_TOP_NET2PLL_D4 49
+#define CK_TOP_NET2PLL_D4_D2 50
+#define CK_TOP_NET2PLL_D3_D2 51
+#define CK_TOP_CB_WEDMCUPLL_760M 52
+#define CK_TOP_WEDMCUPLL_D5_D2 53
+#define CK_TOP_CB_SGMPLL_325M 54
#define CK_TOP_NFI1X_SEL 55
#define CK_TOP_SPINFI_SEL 56
#define CK_TOP_SPI_SEL 57
--
2.45.2
next prev parent reply other threads:[~2024-08-03 11:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-03 8:40 [PATCH 00/15] clk: mediatek: mt7986: clk migration for OF_UPSTREAM Christian Marangi
2024-08-03 8:40 ` [PATCH 01/15] clk: mediatek: mt7986: fix wrong shift for PCIe clocks Christian Marangi
2024-08-03 8:40 ` [PATCH 02/15] clk: mediatek: mt7986: rename CB_CKSQ_40M to TOP_XTAL Christian Marangi
2024-08-03 8:40 ` [PATCH 03/15] clk: mediatek: mt7986: rename 66M_MCK to SYSAXI_D2 Christian Marangi
2024-08-03 8:40 ` [PATCH 04/15] clk: mediatek: mt7986: fix wrong parent for INFRA_ADC_26M_CK Christian Marangi
2024-08-03 8:40 ` [PATCH 05/15] clk: mediatek: mt7986: drop 1/1 infracfg spurious factor Christian Marangi
2024-08-03 8:40 ` [PATCH 06/15] clk: mediatek: mt7986: add missing entry for IPCIE_PIPE_CK infra gate Christian Marangi
2024-08-03 8:40 ` [PATCH 07/15] clk: mediatek: mt7986: fix typo for infra_i2c0_ck Christian Marangi
2024-08-03 8:40 ` [PATCH 08/15] clk: mediatek: mt7986: rename TOPCKGEN factor clock to upstream naming Christian Marangi
2024-08-03 8:40 ` Christian Marangi [this message]
2024-08-03 8:40 ` [PATCH 10/15] clk: mediatek: mt7986: drop 1/1 spurious factor for topckgen Christian Marangi
2024-08-03 8:40 ` [PATCH 11/15] clk: mediatek: mt7986: comment out CK_TOP_A_TUNER as not used Christian Marangi
2024-08-03 8:40 ` [PATCH 12/15] clk: mediatek: mt7986: move INFRA_TRNG_CK to the bottom of the list Christian Marangi
2024-08-03 8:40 ` [PATCH 13/15] clk: mediatek: mt7986: replace infracfg ID with upstream linux Christian Marangi
2024-08-03 8:40 ` [PATCH 14/15] clk: mediatek: mt7986: convert to unified infracfg gates + muxes Christian Marangi
2024-08-03 8:40 ` [PATCH 15/15] clk: mediatek: mt7986: rename CK to CLK Christian Marangi
2024-08-10 13:31 ` Aw: " Frank Wunderlich
2024-08-20 0:29 ` [PATCH 00/15] clk: mediatek: mt7986: clk migration for OF_UPSTREAM Tom Rini
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