[PATCH 00/15] clk: mediatek: mt7986: clk migration for OF_UPSTREAM

[PATCH 00/15] clk: mediatek: mt7986: clk migration for OF_UPSTREAM

[Christian Marangi]

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.

Christian Marangi (15):
  clk: mediatek: mt7986: fix wrong shift for PCIe clocks
  clk: mediatek: mt7986: rename CB_CKSQ_40M to TOP_XTAL
  clk: mediatek: mt7986: rename 66M_MCK to SYSAXI_D2
  clk: mediatek: mt7986: fix wrong parent for INFRA_ADC_26M_CK
  clk: mediatek: mt7986: drop 1/1 infracfg spurious factor
  clk: mediatek: mt7986: add missing entry for IPCIE_PIPE_CK infra gate
  clk: mediatek: mt7986: fix typo for infra_i2c0_ck
  clk: mediatek: mt7986: rename TOPCKGEN factor clock to upstream naming
  clk: mediatek: mt7986: reorder TOPCKGEN factor ID
  clk: mediatek: mt7986: drop 1/1 spurious factor for topckgen
  clk: mediatek: mt7986: comment out CK_TOP_A_TUNER as not used
  clk: mediatek: mt7986: move INFRA_TRNG_CK to the bottom of the list
  clk: mediatek: mt7986: replace infracfg ID with upstream linux
  clk: mediatek: mt7986: convert to unified infracfg gates + muxes
  clk: mediatek: mt7986: rename CK to CLK

 arch/arm/dts/mt7986.dtsi               |  95 ++--
 drivers/clk/mediatek/clk-mt7986.c      | 658 ++++++++++++-------------
 include/dt-bindings/clock/mt7986-clk.h | 359 ++++++--------
 3 files changed, 511 insertions(+), 601 deletions(-)

-- 
2.45.2

[PATCH 01/15] clk: mediatek: mt7986: fix wrong shift for PCIe clocks

[Christian Marangi]

Fix wrong shift for PCIe clocks. This cause the PCIe port to malfunction
as the gate clocks weren't correctly enabled.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7986.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index efc3d4120b7..1e8c3278346 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -504,8 +504,8 @@ static const struct mtk_gate infracfg_ao_gates[] = {
 	GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
 		    2),
 	GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
-	GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13),
-	GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15),
+	GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 12),
+	GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14),
 	GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
 };
 
-- 
2.45.2

[PATCH 02/15] clk: mediatek: mt7986: rename CB_CKSQ_40M to TOP_XTAL

[Christian Marangi]

Upstream kernel linux clock include use TOP_XTAL instead of CB_CKSQ_40M.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm/dts/mt7986.dtsi               |  2 +-
 drivers/clk/mediatek/clk-mt7986.c      | 72 +++++++++++++-------------
 include/dt-bindings/clock/mt7986-clk.h |  4 +-
 3 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index 30b5a899701..276f82f2065 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -178,7 +178,7 @@
 		clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
 		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
 				  <&infracfg_ao CK_INFRA_UART0_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+		assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
 					 <&infracfg CK_INFRA_UART>;
 		mediatek,force-highspeed;
 		status = "disabled";
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 1e8c3278346..67ed1768046 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -41,7 +41,7 @@ static const struct mtk_fixed_clk fixed_pll_clks[] = {
 
 /* TOPCKGEN FIXED CLK */
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
+	FIXED_CLK(CK_TOP_XTAL, CLK_XTAL, 40000000),
 };
 
 /* TOPCKGEN FIXED DIV */
@@ -77,18 +77,18 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
 	PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
 		   10),
 	PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
-	TOP_FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", CK_TOP_CB_CKSQ_40M,
+	TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL,
 		   1, 2),
-	TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+	TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_XTAL, 1,
 		   1250),
-	TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+	TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_XTAL, 1,
 		   1220),
 	TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
+	TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_XTAL, 1,
 		   1),
-	TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
-	TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
-	TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
+	TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_XTAL, 1, 1),
+	TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_XTAL, 1, 1),
+	TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_XTAL, 1, 1),
 	TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
 	TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
 	TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
@@ -114,91 +114,91 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
 };
 
 /* TOPCKGEN MUX PARENTS */
-static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M,  CK_TOP_CB_MM_D8,
+static const int nfi1x_parents[] = { CK_TOP_XTAL,  CK_TOP_CB_MM_D8,
 				     CK_TOP_NET1_D8_D2,   CK_TOP_NET2_D3_D2,
 				     CK_TOP_CB_M_D4,      CK_TOP_MM_D8_D2,
 				     CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 };
 
 static const int spinfi_parents[] = {
-	CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
+	CK_TOP_XTAL_D2, CK_TOP_XTAL, CK_TOP_NET1_D5_D4,
 	CK_TOP_CB_M_D4,	CK_TOP_MM_D8_D2,    CK_TOP_WEDMCU_D5_D2,
 	CK_TOP_MM_D3_D8,       CK_TOP_CB_M_D8
 };
 
-static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
+static const int spi_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D2,
 				   CK_TOP_CB_MM_D8,    CK_TOP_NET1_D8_D2,
 				   CK_TOP_NET2_D3_D2,  CK_TOP_NET1_D5_D4,
 				   CK_TOP_CB_M_D4,     CK_TOP_WEDMCU_D5_D2 };
 
-static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
+static const int uart_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D8,
 				    CK_TOP_M_D8_D2 };
 
-static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
+static const int pwm_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D2,
 				   CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 };
 
-static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
+static const int i2c_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D4,
 				   CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
 
-static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int pextp_tl_ck_parents[] = { CK_TOP_XTAL,
 					   CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2,
 					   CK_TOP_CB_RTC_32K };
 
-static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int emmc_250m_parents[] = { CK_TOP_XTAL,
 					 CK_TOP_NET1_D5_D2 };
 
-static const int emmc_416m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_416M };
+static const int emmc_416m_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_416M };
 
-static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
+static const int f_26m_adc_parents[] = { CK_TOP_XTAL, CK_TOP_M_D8_D2 };
 
-static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2 };
+static const int dramc_md32_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D2 };
 
-static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
+static const int sysaxi_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D2,
 				      CK_TOP_CB_NET2_D4 };
 
-static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2,
+static const int sysapb_parents[] = { CK_TOP_XTAL, CK_TOP_M_D3_D2,
 				      CK_TOP_NET2_D4_D2 };
 
-static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int arm_db_main_parents[] = { CK_TOP_XTAL,
 					   CK_TOP_NET2_D3_D2 };
 
-static const int arm_db_jtsel_parents[] = { -1, CK_TOP_CB_CKSQ_40M };
+static const int arm_db_jtsel_parents[] = { -1, CK_TOP_XTAL };
 
-static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4 };
+static const int netsys_parents[] = { CK_TOP_XTAL, CK_TOP_CB_MM_D4 };
 
-static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int netsys_500m_parents[] = { CK_TOP_XTAL,
 					   CK_TOP_CB_NET1_D5 };
 
-static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int netsys_mcu_parents[] = { CK_TOP_XTAL,
 					  CK_TOP_CB_WEDMCU_760M,
 					  CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4,
 					  CK_TOP_CB_NET1_D5 };
 
-static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int netsys_2x_parents[] = { CK_TOP_XTAL,
 					 CK_TOP_CB_NET2_800M,
 					 CK_TOP_CB_WEDMCU_760M,
 					 CK_TOP_CB_MM_D2 };
 
-static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int sgm_325m_parents[] = { CK_TOP_XTAL,
 					CK_TOP_CB_SGM_325M };
 
-static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 };
+static const int sgm_reg_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D4 };
 
-static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
+static const int a1sys_parents[] = { CK_TOP_XTAL, CK_TOP_APLL2_D4 };
 
-static const int conn_mcusys_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int conn_mcusys_parents[] = { CK_TOP_XTAL,
 					   CK_TOP_CB_MM_D2 };
 
-static const int eip_b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M };
+static const int eip_b_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET2_800M };
 
-static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
+static const int aud_l_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_196M,
 				     CK_TOP_M_D8_D2 };
 
-static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
+static const int a_tuner_parents[] = { CK_TOP_XTAL, CK_TOP_APLL2_D4,
 				       CK_TOP_M_D8_D2 };
 
-static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+static const int u2u3_sys_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D4 };
 
-static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int da_u2_refsel_parents[] = { CK_TOP_XTAL,
 					    CK_TOP_CB_U2_PHYD_CK };
 
 #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,    \
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 820f8631831..30720f9fb42 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -51,7 +51,7 @@
 
 /* TOPCKGEN */
 
-#define CK_TOP_CB_CKSQ_40M		0
+#define CK_TOP_XTAL			0
 #define CK_TOP_CB_M_416M		1
 #define CK_TOP_CB_M_D2			2
 #define CK_TOP_CB_M_D4			3
@@ -79,7 +79,7 @@
 #define CK_TOP_CB_WEDMCU_760M		25
 #define CK_TOP_WEDMCU_D5_D2		26
 #define CK_TOP_CB_SGM_325M		27
-#define CK_TOP_CB_CKSQ_40M_D2		28
+#define CK_TOP_XTAL_D2			28
 #define CK_TOP_CB_RTC_32K		29
 #define CK_TOP_CB_RTC_32P7K		30
 #define CK_TOP_NFI1X			31
-- 
2.45.2

[PATCH 03/15] clk: mediatek: mt7986: rename 66M_MCK to SYSAXI_D2

[Christian Marangi]

Upstream kernel linux clock include use SYSAXI_D2 instead of 66M_MCK.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7986.c      | 20 ++++++++++----------
 include/dt-bindings/clock/mt7986-clk.h |  2 +-
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 67ed1768046..72300d80884 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -309,7 +309,7 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
 	TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
 	TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPINFI_SEL, 1, 1),
 	TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
-	TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
+	TOP_FACTOR(CK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", CK_TOP_SYSAXI_SEL, 1, 2),
 	TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
 		   1),
 	TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
@@ -365,7 +365,7 @@ static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
 
 static const int infra_pwm_bsel_parents[] = { CK_INFRA_CK_F32K,
 					      CK_INFRA_CK_F26M,
-					      CK_INFRA_66M_MCK, CK_INFRA_PWM };
+					      CK_INFRA_SYSAXI_D2, CK_INFRA_PWM };
 
 static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
 					  -1, CK_INFRA_PCIE_CK };
@@ -447,8 +447,8 @@ static const struct mtk_gate_regs infra_2_cg_regs = {
 
 static const struct mtk_gate infracfg_ao_gates[] = {
 	/* INFRA0 */
-	GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
-	GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
+	GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_SYSAXI_D2, 0),
+	GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_SYSAXI_D2, 1),
 	GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
 	GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
 	GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
@@ -463,9 +463,9 @@ static const struct mtk_gate infracfg_ao_gates[] = {
 		    13),
 	GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
 		    14),
-	GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
-	GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
-	GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
+	GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_SYSAXI_D2, 15),
+	GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_SYSAXI_D2, 16),
+	GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_SYSAXI_D2, 24),
 	GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
 	GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", CK_INFRA_HD_133M, 26),
 	/* INFRA1 */
@@ -477,12 +477,12 @@ static const struct mtk_gate infracfg_ao_gates[] = {
 	GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
 	GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
 		    9),
-	GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
+	GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_SYSAXI_D2, 10),
 	GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
 	GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
-	GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
+	GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_SYSAXI_D2,
 		    13),
-	GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
+	GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_SYSAXI_D2,
 		    14),
 	GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
 	GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 30720f9fb42..f45ef7afcc6 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -16,7 +16,7 @@
 #define CK_INFRA_I2C			3
 #define CK_INFRA_ISPI1			4
 #define CK_INFRA_PWM			5
-#define CK_INFRA_66M_MCK		6
+#define CK_INFRA_SYSAXI_D2		6
 #define CK_INFRA_CK_F32K		7
 #define CK_INFRA_PCIE_CK		8
 #define CK_INFRA_PWM_BCK		9
-- 
2.45.2

[PATCH 04/15] clk: mediatek: mt7986: fix wrong parent for INFRA_ADC_26M_CK

[Christian Marangi]

Fix wrong parent for INFRA_ADC_26M_CK as should be INFRA_ADC_FRC_CK
instead of INFRA_CK_F26M. This is to match implementation on upstream
kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7986.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 72300d80884..cb4d20a204d 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -492,7 +492,7 @@ static const struct mtk_gate infracfg_ao_gates[] = {
 		    CK_INFRA_PERI_133M, 18),
 	GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
 		    19),
-	GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_CK_F26M, 20),
+	GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_ADC_FRC_CK, 20),
 	GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_INFRA_CK_F26M, 21),
 	GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
 		    23),
-- 
2.45.2

[PATCH 05/15] clk: mediatek: mt7986: drop 1/1 infracfg spurious factor

[Christian Marangi]

Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7986.

Drop the factor entry from mt7986-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for infracfg and topckgen.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm/dts/mt7986.dtsi               |  18 +-
 drivers/clk/mediatek/clk-mt7986.c      | 235 ++++++++++++-------------
 include/dt-bindings/clock/mt7986-clk.h |  40 +----
 3 files changed, 120 insertions(+), 173 deletions(-)

diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index 276f82f2065..e26b85b8266 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -78,7 +78,7 @@
 		compatible = "mediatek,mt7986-timer";
 		reg = <0x10008000 0x1000>;
 		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CK_INFRA_CK_F26M>;
+		clocks = <&topckgen CK_TOP_F26M_SEL>;
 		clock-names = "gpt-clk";
 		bootph-all;
 	};
@@ -154,7 +154,7 @@
 		#clock-cells = <1>;
 		#pwm-cells = <2>;
 		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CK_INFRA_PWM>,
+		clocks = <&topckgen CK_TOP_PWM_SEL>,
 			 <&infracfg_ao CK_INFRA_PWM_BSEL>,
 			 <&infracfg_ao CK_INFRA_PWM1_CK>,
 			 <&infracfg_ao CK_INFRA_PWM2_CK>;
@@ -163,9 +163,9 @@
 				  <&infracfg CK_INFRA_PWM1_SEL>,
 				  <&infracfg CK_INFRA_PWM2_SEL>;
 		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
-					 <&infracfg CK_INFRA_PWM>,
-					 <&infracfg CK_INFRA_PWM>,
-					 <&infracfg CK_INFRA_PWM>;
+					 <&topckgen CK_TOP_PWM_SEL>,
+					 <&topckgen CK_TOP_PWM_SEL>,
+					 <&topckgen CK_TOP_PWM_SEL>;
 		clock-names = "top", "main", "pwm1", "pwm2";
 		status = "disabled";
 		bootph-all;
@@ -179,7 +179,7 @@
 		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
 				  <&infracfg_ao CK_INFRA_UART0_SEL>;
 		assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
-					 <&infracfg CK_INFRA_UART>;
+					 <&topckgen CK_TOP_UART_SEL>;
 		mediatek,force-highspeed;
 		status = "disabled";
 		bootph-all;
@@ -191,7 +191,7 @@
 		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
 		assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
-		assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
+		assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
 		mediatek,force-highspeed;
 		status = "disabled";
 	};
@@ -202,7 +202,7 @@
 		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
 		assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
-		assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
+		assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
 		mediatek,force-highspeed;
 		status = "disabled";
 	};
@@ -263,7 +263,7 @@
 		assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
 				  <&infracfg CK_INFRA_SPI0_SEL>;
 		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
-					 <&topckgen CK_INFRA_ISPI0>;
+					 <&topckgen CK_TOP_SPI_SEL>;
 		clock-names = "sel-clk", "spi-clk";
 		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index cb4d20a204d..f1870ce3d60 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -303,80 +303,50 @@ static const struct mtk_composite top_muxes[] = {
 
 /* INFRA FIXED DIV */
 static const struct mtk_fixed_factor infra_fixed_divs[] = {
-	TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
-	TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
-	TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
-	TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
-	TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPINFI_SEL, 1, 1),
-	TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
 	TOP_FACTOR(CK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", CK_TOP_SYSAXI_SEL, 1, 2),
-	TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
-		   1),
-	TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
-	INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
-		     1),
-	INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
-		     1),
-	INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
-		     1),
-	TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
-	TOP_FACTOR(CK_INFRA_EIP_CK, "infra_eip", CK_TOP_EIP_B, 1, 1),
-	INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
-		     1),
-	TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
-	TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
-	TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
-		   1),
-	TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
-	INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
-		     1, 1),
-	INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
-		     1, 1),
-	INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
-		     1, 1),
-	TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
-	TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
-	INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
-		     1),
-	INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
-		     1),
-	TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
-	TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_416M, 1, 1),
-	TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_250M,
-		   1, 1),
-	TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
-	TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
-	TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
-	TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
-	TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
-		   1),
-	TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
-		   CK_TOP_PEXTP_TL, 1, 1),
-	TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
-	TOP_FACTOR(CK_INFRA_HD_133M, "infra_hd_133m", CK_TOP_SYSAXI, 1, 1),
 };
 
 /* INFRASYS MUX PARENTS */
-static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
+#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS)
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
+#define VOID_PARENT PARENT(-1, 0)
 
-static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
+static const struct mtk_parent infra_uart0_parents[] = {
+	TOP_PARENT(CK_TOP_F26M_SEL),
+	TOP_PARENT(CK_TOP_UART_SEL)
+};
 
-static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
+static const struct mtk_parent infra_spi0_parents[] = {
+	TOP_PARENT(CK_TOP_I2C_SEL),
+	TOP_PARENT(CK_TOP_SPI_SEL)
+};
 
-static const int infra_pwm_bsel_parents[] = { CK_INFRA_CK_F32K,
-					      CK_INFRA_CK_F26M,
-					      CK_INFRA_SYSAXI_D2, CK_INFRA_PWM };
+static const struct mtk_parent infra_spi1_parents[] = {
+	TOP_PARENT(CK_TOP_I2C_SEL),
+	TOP_PARENT(CK_TOP_SPINFI_SEL)
+};
+
+static const struct mtk_parent infra_pwm_bsel_parents[] = {
+	TOP_PARENT(CK_TOP_CB_RTC_32P7K),
+	TOP_PARENT(CK_TOP_F26M_SEL),
+	INFRA_PARENT(CK_INFRA_SYSAXI_D2),
+	TOP_PARENT(CK_TOP_PWM_SEL)
+};
 
-static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
-					  -1, CK_INFRA_PCIE_CK };
+static const struct mtk_parent infra_pcie_parents[] = {
+	TOP_PARENT(CK_TOP_CB_RTC_32P7K),
+	TOP_PARENT(CK_TOP_F26M_SEL),
+	VOID_PARENT,
+	TOP_PARENT(CK_TOP_PEXTP_TL_SEL)
+};
 
 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width)                  \
 	{                                                                      \
 		.id = _id, .mux_reg = (_reg) + 0x8,                            \
 		.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4,      \
 		.mux_shift = _shift, .mux_mask = BIT(_width) - 1,              \
-		.parent = _parents, .num_parents = ARRAY_SIZE(_parents),       \
-		.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS,             \
+		.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
+		.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED,                \
 	}
 
 /* INFRA MUX */
@@ -422,91 +392,103 @@ static const struct mtk_gate_regs infra_2_cg_regs = {
 	.sta_ofs = 0x68,
 };
 
-#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
+#define GATE_INFRA0(_id, _name, _parent, _shift, _flags)                       \
 	{                                                                      \
 		.id = _id, .parent = _parent, .regs = &infra_0_cg_regs,        \
 		.shift = _shift,                                               \
-		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
+		.flags = _flags,                                               \
 	}
+#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \
+	GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \
+	GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
 
-#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
+#define GATE_INFRA1(_id, _name, _parent, _shift, _flags)                       \
 	{                                                                      \
 		.id = _id, .parent = _parent, .regs = &infra_1_cg_regs,        \
 		.shift = _shift,                                               \
-		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
+		.flags = _flags,                                               \
 	}
+#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \
+	GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \
+	GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
 
-#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
+#define GATE_INFRA2(_id, _name, _parent, _shift, _flags)                       \
 	{                                                                      \
 		.id = _id, .parent = _parent, .regs = &infra_2_cg_regs,        \
 		.shift = _shift,                                               \
-		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
+		.flags = _flags,                                               \
 	}
+#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \
+	GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \
+	GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
 
 /* INFRA GATE */
 
 static const struct mtk_gate infracfg_ao_gates[] = {
 	/* INFRA0 */
-	GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_SYSAXI_D2, 0),
-	GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_SYSAXI_D2, 1),
-	GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
-	GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
-	GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
-	GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
-	GATE_INFRA0(CK_INFRA_EIP97_CK, "infra_eip97", CK_INFRA_EIP_CK, 7),
-	GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
-	GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
-	GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
-	GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
-		    11),
-	GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
-		    13),
-	GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
-		    14),
-	GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_SYSAXI_D2, 15),
-	GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_SYSAXI_D2, 16),
-	GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_SYSAXI_D2, 24),
-	GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
-	GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", CK_INFRA_HD_133M, 26),
+	GATE_INFRA0_INFRA(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_SYSAXI_D2, 0),
+	GATE_INFRA0_INFRA(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_SYSAXI_D2, 1),
+	GATE_INFRA0_INFRA(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BSEL, 2),
+	GATE_INFRA0_INFRA(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM1_SEL, 3),
+	GATE_INFRA0_INFRA(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM2_SEL, 4),
+	GATE_INFRA0_TOP(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_TOP_SYSAXI_SEL, 6),
+	GATE_INFRA0_TOP(CK_INFRA_EIP97_CK, "infra_eip97", CK_TOP_EIP_B_SEL, 7),
+	GATE_INFRA0_TOP(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_TOP_SYSAXI_SEL, 8),
+	GATE_INFRA0_TOP(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_TOP_F26M_SEL, 9),
+	GATE_INFRA0_TOP(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_TOP_AUD_L_SEL, 10),
+	GATE_INFRA0_TOP(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_TOP_A1SYS_SEL,
+			11),
+	GATE_INFRA0_TOP(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_TOP_A_TUNER_SEL,
+			13),
+	GATE_INFRA0_TOP(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_TOP_F26M_SEL,
+			14),
+	GATE_INFRA0_INFRA(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_SYSAXI_D2, 15),
+	GATE_INFRA0_INFRA(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_SYSAXI_D2, 16),
+	GATE_INFRA0_INFRA(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_SYSAXI_D2, 24),
+	GATE_INFRA0_TOP(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_TOP_F26M_SEL, 25),
+	GATE_INFRA0_TOP(CK_INFRA_TRNG_CK, "infra_trng", CK_TOP_SYSAXI_SEL, 26),
 	/* INFRA1 */
-	GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
-	GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
-	GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
-	GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
-	GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
-	GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
-	GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
-		    9),
-	GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_SYSAXI_D2, 10),
-	GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
-	GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
-	GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_SYSAXI_D2,
-		    13),
-	GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_SYSAXI_D2,
-		    14),
-	GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
-	GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
-	GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
-		    CK_INFRA_FMSDC_HCK_CK, 17),
-	GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
-		    CK_INFRA_PERI_133M, 18),
-	GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
-		    19),
-	GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_ADC_FRC_CK, 20),
-	GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_INFRA_CK_F26M, 21),
-	GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
-		    23),
+	GATE_INFRA1_TOP(CK_INFRA_THERM_CK, "infra_therm", CK_TOP_F26M_SEL, 0),
+	GATE_INFRA1_TOP(CK_INFRA_I2CO_CK, "infra_i2co", CK_TOP_I2C_SEL, 1),
+	GATE_INFRA1_INFRA(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_UART0_SEL, 2),
+	GATE_INFRA1_INFRA(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_UART1_SEL, 3),
+	GATE_INFRA1_INFRA(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_UART2_SEL, 4),
+	GATE_INFRA1_TOP(CK_INFRA_NFI1_CK, "infra_nfi1", CK_TOP_NFI1X_SEL, 8),
+	GATE_INFRA1_TOP(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_TOP_SPINFI_SEL,
+			9),
+	GATE_INFRA1_INFRA(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_SYSAXI_D2, 10),
+	GATE_INFRA1_INFRA(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_SPI0_SEL, 11),
+	GATE_INFRA1_INFRA(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_SPI1_SEL, 12),
+	GATE_INFRA1_INFRA(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_SYSAXI_D2,
+			  13),
+	GATE_INFRA1_INFRA(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_SYSAXI_D2,
+			  14),
+	GATE_INFRA1_TOP(CK_INFRA_FRTC_CK, "infra_frtc", CK_TOP_CB_RTC_32K, 15),
+	GATE_INFRA1_TOP(CK_INFRA_MSDC_CK, "infra_msdc", CK_TOP_EMMC_416M_SEL, 16),
+	GATE_INFRA1_TOP(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
+			CK_TOP_EMMC_250M_SEL, 17),
+	GATE_INFRA1_TOP(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
+			CK_TOP_SYSAXI_SEL, 18),
+	GATE_INFRA1_INFRA(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_SYSAXI_D2,
+			  19),
+	GATE_INFRA1_INFRA(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_ADC_FRC_CK, 20),
+	GATE_INFRA1_TOP(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M_SEL, 21),
+	GATE_INFRA1_TOP(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_TOP_NFI1X_SEL,
+			23),
 	/* INFRA2 */
-	GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
-		    0),
-	GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
-		    1),
-	GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
-		    2),
-	GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
-	GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 12),
-	GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14),
-	GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
+	GATE_INFRA2_TOP(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_TOP_SYSAXI_SEL,
+			0),
+	GATE_INFRA2_INFRA(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_SYSAXI_D2,
+			  1),
+	GATE_INFRA2_TOP(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_TOP_U2U3_SYS_SEL,
+			2),
+	GATE_INFRA2_TOP(CK_INFRA_IUSB_CK, "infra_iusb", CK_TOP_U2U3_SEL, 3),
+	GATE_INFRA2_TOP(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_TOP_PEXTP_TL_SEL, 12),
+	GATE_INFRA2_TOP(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_TOP_F26M_SEL, 14),
+	GATE_INFRA2_TOP(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_TOP_SYSAXI_SEL, 15),
 };
 
 static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
@@ -521,14 +503,15 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
 	.muxes = top_muxes,
-	.flags = CLK_BYPASS_XTAL,
+	.flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
 };
 
 static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
-	.fdivs_offs = CK_INFRA_CK_F26M,
+	.fdivs_offs = CK_INFRA_SYSAXI_D2,
 	.muxes_offs = CK_INFRA_UART0_SEL,
 	.fdivs = infra_fixed_divs,
 	.muxes = infra_muxes,
+	.flags = CLK_INFRASYS,
 };
 
 static const struct udevice_id mt7986_fixed_pll_compat[] = {
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index f45ef7afcc6..dbae389858a 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -10,44 +10,8 @@
 
 /* INFRACFG */
 
-#define CK_INFRA_CK_F26M		0
-#define CK_INFRA_UART			1
-#define CK_INFRA_ISPI0			2
-#define CK_INFRA_I2C			3
-#define CK_INFRA_ISPI1			4
-#define CK_INFRA_PWM			5
-#define CK_INFRA_SYSAXI_D2		6
-#define CK_INFRA_CK_F32K		7
-#define CK_INFRA_PCIE_CK		8
-#define CK_INFRA_PWM_BCK		9
-#define CK_INFRA_PWM_CK1		10
-#define CK_INFRA_PWM_CK2		11
-#define CK_INFRA_133M_HCK		12
-#define CK_INFRA_EIP_CK			13
-#define CK_INFRA_66M_PHCK		14
-#define CK_INFRA_FAUD_L_CK		15
-#define CK_INFRA_FAUD_AUD_CK		17
-#define CK_INFRA_FAUD_EG2_CK		17
-#define CK_INFRA_I2CS_CK		18
-#define CK_INFRA_MUX_UART0		19
-#define CK_INFRA_MUX_UART1		20
-#define CK_INFRA_MUX_UART2		21
-#define CK_INFRA_NFI_CK			22
-#define CK_INFRA_SPINFI_CK		23
-#define CK_INFRA_MUX_SPI0		24
-#define CK_INFRA_MUX_SPI1		25
-#define CK_INFRA_RTC_32K		26
-#define CK_INFRA_FMSDC_CK		27
-#define CK_INFRA_FMSDC_HCK_CK		28
-#define CK_INFRA_PERI_133M		29
-#define CK_INFRA_133M_PHCK		30
-#define CK_INFRA_USB_SYS_CK		31
-#define CK_INFRA_USB_CK			32
-#define CK_INFRA_USB_XHCI_CK		33
-#define CK_INFRA_PCIE_GFMUX_TL_O_PRE	34
-#define CK_INFRA_F26M_CK0		35
-#define CK_INFRA_HD_133M		36
-#define CLK_INFRA_NR_CLK		37
+#define CK_INFRA_SYSAXI_D2		0
+#define CLK_INFRA_NR_CLK		1
 
 /* TOPCKGEN */
 
-- 
2.45.2

[PATCH 06/15] clk: mediatek: mt7986: add missing entry for IPCIE_PIPE_CK infra gate

[Christian Marangi]

Add missing entry for IPCIE_PIPE_CK infra gate clock. Renumber the clock
order to match the expected offset in the gate array.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7986.c      | 3 ++-
 include/dt-bindings/clock/mt7986-clk.h | 7 ++++---
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index f1870ce3d60..5f07de23756 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -336,7 +336,7 @@ static const struct mtk_parent infra_pwm_bsel_parents[] = {
 static const struct mtk_parent infra_pcie_parents[] = {
 	TOP_PARENT(CK_TOP_CB_RTC_32P7K),
 	TOP_PARENT(CK_TOP_F26M_SEL),
-	VOID_PARENT,
+	TOP_PARENT(CK_TOP_XTAL),
 	TOP_PARENT(CK_TOP_PEXTP_TL_SEL)
 };
 
@@ -487,6 +487,7 @@ static const struct mtk_gate infracfg_ao_gates[] = {
 			2),
 	GATE_INFRA2_TOP(CK_INFRA_IUSB_CK, "infra_iusb", CK_TOP_U2U3_SEL, 3),
 	GATE_INFRA2_TOP(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_TOP_PEXTP_TL_SEL, 12),
+	GATE_INFRA2_TOP(CK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CK_TOP_XTAL, 13),
 	GATE_INFRA2_TOP(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_TOP_F26M_SEL, 14),
 	GATE_INFRA2_TOP(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_TOP_SYSAXI_SEL, 15),
 };
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index dbae389858a..16faca5fef8 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -167,9 +167,10 @@
 #define CK_INFRA_IUSB_SYS_CK		40
 #define CK_INFRA_IUSB_CK		41
 #define CK_INFRA_IPCIE_CK		42
-#define CK_INFRA_IPCIER_CK		43
-#define CK_INFRA_IPCIEB_CK		44
-#define CLK_INFRA_AO_NR_CLK		45
+#define CK_INFRA_IPCIE_PIPE_CK		43
+#define CK_INFRA_IPCIER_CK		44
+#define CK_INFRA_IPCIEB_CK		45
+#define CLK_INFRA_AO_NR_CLK		46
 
 /* APMIXEDSYS */
 
-- 
2.45.2

[PATCH 07/15] clk: mediatek: mt7986: fix typo for infra_i2c0_ck

[Christian Marangi]

Fix a typo for infra_i2c0_ck where 0 was misspelled as O.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7986.c      | 2 +-
 include/dt-bindings/clock/mt7986-clk.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 5f07de23756..303d959d750 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -452,7 +452,7 @@ static const struct mtk_gate infracfg_ao_gates[] = {
 	GATE_INFRA0_TOP(CK_INFRA_TRNG_CK, "infra_trng", CK_TOP_SYSAXI_SEL, 26),
 	/* INFRA1 */
 	GATE_INFRA1_TOP(CK_INFRA_THERM_CK, "infra_therm", CK_TOP_F26M_SEL, 0),
-	GATE_INFRA1_TOP(CK_INFRA_I2CO_CK, "infra_i2co", CK_TOP_I2C_SEL, 1),
+	GATE_INFRA1_TOP(CK_INFRA_I2C0_CK, "infra_i2co", CK_TOP_I2C_SEL, 1),
 	GATE_INFRA1_INFRA(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_UART0_SEL, 2),
 	GATE_INFRA1_INFRA(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_UART1_SEL, 3),
 	GATE_INFRA1_INFRA(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_UART2_SEL, 4),
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 16faca5fef8..a48d57512d1 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -142,7 +142,7 @@
 #define CK_INFRA_SEJ_CK			15
 #define CK_INFRA_SEJ_13M_CK		16
 #define CK_INFRA_THERM_CK		17
-#define CK_INFRA_I2CO_CK		18
+#define CK_INFRA_I2C0_CK		18
 #define CK_INFRA_TRNG_CK		19
 #define CK_INFRA_UART0_CK		20
 #define CK_INFRA_UART1_CK		21
-- 
2.45.2

[PATCH 08/15] clk: mediatek: mt7986: rename TOPCKGEN factor clock to upstream naming

[Christian Marangi]

Rename TOPCKGEN factor clock to upstream neaming.
Upstream kernel linux reference the factor clock for apmixedpll with the
"pll" suffix. Align the naming to the upstream naming format in
preparation for OF_UPSTREAM support.

Also rename rtc clock to drop the CB_ as upstream doesn't have that.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm/dts/mt7986.dtsi               |   2 +-
 drivers/clk/mediatek/clk-mt7986.c      | 152 +++++++++++++------------
 include/dt-bindings/clock/mt7986-clk.h |  54 ++++-----
 3 files changed, 108 insertions(+), 100 deletions(-)

diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index e26b85b8266..31119640d23 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -287,7 +287,7 @@
 		assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
 				  <&topckgen CK_TOP_EMMC_250M_SEL>;
 		assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>,
-					 <&topckgen CK_TOP_NET1_D5_D2>;
+					 <&topckgen CK_TOP_NET1PLL_D5_D2>;
 		clock-names = "source", "hclk", "source_cg";
 		status = "disabled";
 	};
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 303d959d750..c1f63ecc3b2 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -46,42 +46,50 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
 
 /* TOPCKGEN FIXED DIV */
 static const struct mtk_fixed_factor top_fixed_divs[] = {
-	PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
-	PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
-	PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
-	PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
-	PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
-	PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
-	PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
-	PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
-	PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
-	PLL_FACTOR(CK_TOP_MM_D8_D2, "mm_d8_d2", CK_APMIXED_MMPLL, 1, 16),
-	PLL_FACTOR(CK_TOP_MM_D3_D8, "mm_d3_d8", CK_APMIXED_MMPLL, 1, 8),
-	PLL_FACTOR(CK_TOP_CB_U2_PHYD_CK, "cb_u2_phyd", CK_APMIXED_MMPLL, 1, 30),
+	/* MPLL */
+	PLL_FACTOR(CK_TOP_CB_MPLL_416M, "cb_mpll_416m", CK_APMIXED_MPLL, 1, 1),
+	PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
+	PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
+	PLL_FACTOR(CK_TOP_MPLL_D8, "mpll_d8", CK_APMIXED_MPLL, 1, 8),
+	PLL_FACTOR(CK_TOP_MPLL_D8_D2, "mpll_d8_d2", CK_APMIXED_MPLL, 1, 16),
+	PLL_FACTOR(CK_TOP_MPLL_D3_D2, "mpll_d3_d2", CK_APMIXED_MPLL, 1, 2),
+	/* MMPLL */
+	PLL_FACTOR(CK_TOP_MMPLL_D2, "mmpll_d2", CK_APMIXED_MMPLL, 1, 2),
+	PLL_FACTOR(CK_TOP_MMPLL_D4, "mmpll_d4", CK_APMIXED_MMPLL, 1, 4),
+	PLL_FACTOR(CK_TOP_MMPLL_D8, "mmpll_d8", CK_APMIXED_MMPLL, 1, 8),
+	PLL_FACTOR(CK_TOP_MMPLL_D8_D2, "mmpll_d8_d2", CK_APMIXED_MMPLL, 1, 16),
+	PLL_FACTOR(CK_TOP_MMPLL_D3_D8, "mmpll_d3_d8", CK_APMIXED_MMPLL, 1, 8),
+	PLL_FACTOR(CK_TOP_MMPLL_U2PHYD, "mmpll_u2phy", CK_APMIXED_MMPLL, 1, 30),
+	/* APLL2 */
 	PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
 		   1),
 	PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
-	PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
-	PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
-	PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
-	PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
-	PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
-	PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
-	PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
+	/* NET1PLL */
+	PLL_FACTOR(CK_TOP_NET1PLL_D4, "net1pll_d4", CK_APMIXED_NET1PLL, 1, 4),
+	PLL_FACTOR(CK_TOP_NET1PLL_D5, "net1pll_d5", CK_APMIXED_NET1PLL, 1, 5),
+	PLL_FACTOR(CK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
+	PLL_FACTOR(CK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
+	PLL_FACTOR(CK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
+	PLL_FACTOR(CK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
+	/* NET2PLL */
+	PLL_FACTOR(CK_TOP_CB_NET2PLL_800M, "cb_net2pll_800m", CK_APMIXED_NET2PLL, 1,
 		   1),
-	PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
-	PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
-	PLL_FACTOR(CK_TOP_NET2_D3_D2, "net2_d3_d2", CK_APMIXED_NET2PLL, 1, 2),
-	PLL_FACTOR(CK_TOP_CB_WEDMCU_760M, "cb_wedmcu_760m",
+	PLL_FACTOR(CK_TOP_NET2PLL_D4, "net2pll_d4", CK_APMIXED_NET2PLL, 1, 4),
+	PLL_FACTOR(CK_TOP_NET2PLL_D4_D2, "net2pll_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
+	PLL_FACTOR(CK_TOP_NET2PLL_D3_D2, "net2pll_d3_d2", CK_APMIXED_NET2PLL, 1, 2),
+	/* WEDMCUPLL */
+	PLL_FACTOR(CK_TOP_CB_WEDMCUPLL_760M, "cb_wedmcupll_760m",
 		   CK_APMIXED_WEDMCUPLL, 1, 1),
-	PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
+	PLL_FACTOR(CK_TOP_WEDMCUPLL_D5_D2, "wedmcupll_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
 		   10),
-	PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
+	/* SGMPLL */
+	PLL_FACTOR(CK_TOP_CB_SGMPLL_325M, "cb_sgmpll_325m", CK_APMIXED_SGMPLL, 1, 1),
+	/* TOPCKGEN and XTAL */
 	TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL,
 		   1, 2),
-	TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_XTAL, 1,
+	TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
 		   1250),
-	TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_XTAL, 1,
+	TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
 		   1220),
 	TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
 	TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_XTAL, 1,
@@ -114,92 +122,92 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
 };
 
 /* TOPCKGEN MUX PARENTS */
-static const int nfi1x_parents[] = { CK_TOP_XTAL,  CK_TOP_CB_MM_D8,
-				     CK_TOP_NET1_D8_D2,   CK_TOP_NET2_D3_D2,
-				     CK_TOP_CB_M_D4,      CK_TOP_MM_D8_D2,
-				     CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 };
+static const int nfi1x_parents[] = { CK_TOP_XTAL,  CK_TOP_MMPLL_D8,
+				     CK_TOP_NET1PLL_D8_D2,   CK_TOP_NET2PLL_D3_D2,
+				     CK_TOP_MPLL_D4,      CK_TOP_MMPLL_D8_D2,
+				     CK_TOP_WEDMCUPLL_D5_D2, CK_TOP_MPLL_D8 };
 
 static const int spinfi_parents[] = {
-	CK_TOP_XTAL_D2, CK_TOP_XTAL, CK_TOP_NET1_D5_D4,
-	CK_TOP_CB_M_D4,	CK_TOP_MM_D8_D2,    CK_TOP_WEDMCU_D5_D2,
-	CK_TOP_MM_D3_D8,       CK_TOP_CB_M_D8
+	CK_TOP_XTAL_D2, CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D4,
+	CK_TOP_MPLL_D4,	CK_TOP_MMPLL_D8_D2,    CK_TOP_WEDMCUPLL_D5_D2,
+	CK_TOP_MMPLL_D3_D8,       CK_TOP_MPLL_D8
 };
 
-static const int spi_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D2,
-				   CK_TOP_CB_MM_D8,    CK_TOP_NET1_D8_D2,
-				   CK_TOP_NET2_D3_D2,  CK_TOP_NET1_D5_D4,
-				   CK_TOP_CB_M_D4,     CK_TOP_WEDMCU_D5_D2 };
+static const int spi_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D2,
+				   CK_TOP_MMPLL_D8,    CK_TOP_NET1PLL_D8_D2,
+				   CK_TOP_NET2PLL_D3_D2,  CK_TOP_NET1PLL_D5_D4,
+				   CK_TOP_MPLL_D4,     CK_TOP_WEDMCUPLL_D5_D2 };
 
-static const int uart_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D8,
-				    CK_TOP_M_D8_D2 };
+static const int uart_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D8,
+				    CK_TOP_MPLL_D8_D2 };
 
-static const int pwm_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D2,
-				   CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 };
+static const int pwm_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D8_D2,
+				   CK_TOP_NET1PLL_D5_D4, CK_TOP_MPLL_D4 };
 
-static const int i2c_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D4,
-				   CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const int i2c_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D4,
+				   CK_TOP_MPLL_D4, CK_TOP_NET1PLL_D8_D4 };
 
 static const int pextp_tl_ck_parents[] = { CK_TOP_XTAL,
-					   CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2,
-					   CK_TOP_CB_RTC_32K };
+					   CK_TOP_NET1PLL_D5_D4, CK_TOP_NET2PLL_D4_D2,
+					   CK_TOP_RTC_32K };
 
 static const int emmc_250m_parents[] = { CK_TOP_XTAL,
-					 CK_TOP_NET1_D5_D2 };
+					 CK_TOP_NET1PLL_D5_D2 };
 
-static const int emmc_416m_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_416M };
+static const int emmc_416m_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_416M };
 
-static const int f_26m_adc_parents[] = { CK_TOP_XTAL, CK_TOP_M_D8_D2 };
+static const int f_26m_adc_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D8_D2 };
 
-static const int dramc_md32_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D2 };
+static const int dramc_md32_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D2 };
 
-static const int sysaxi_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D2,
-				      CK_TOP_CB_NET2_D4 };
+static const int sysaxi_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D8_D2,
+				      CK_TOP_NET2PLL_D4 };
 
-static const int sysapb_parents[] = { CK_TOP_XTAL, CK_TOP_M_D3_D2,
-				      CK_TOP_NET2_D4_D2 };
+static const int sysapb_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D3_D2,
+				      CK_TOP_NET2PLL_D4_D2 };
 
 static const int arm_db_main_parents[] = { CK_TOP_XTAL,
-					   CK_TOP_NET2_D3_D2 };
+					   CK_TOP_NET2PLL_D3_D2 };
 
 static const int arm_db_jtsel_parents[] = { -1, CK_TOP_XTAL };
 
-static const int netsys_parents[] = { CK_TOP_XTAL, CK_TOP_CB_MM_D4 };
+static const int netsys_parents[] = { CK_TOP_XTAL, CK_TOP_MMPLL_D4 };
 
 static const int netsys_500m_parents[] = { CK_TOP_XTAL,
-					   CK_TOP_CB_NET1_D5 };
+					   CK_TOP_NET1PLL_D5 };
 
 static const int netsys_mcu_parents[] = { CK_TOP_XTAL,
 					  CK_TOP_CB_WEDMCU_760M,
-					  CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4,
-					  CK_TOP_CB_NET1_D5 };
+					  CK_TOP_MMPLL_D2, CK_TOP_NET1PLL_D4,
+					  CK_TOP_NET1PLL_D5 };
 
 static const int netsys_2x_parents[] = { CK_TOP_XTAL,
-					 CK_TOP_CB_NET2_800M,
+					 CK_TOP_CB_NET2PLL_800M,
 					 CK_TOP_CB_WEDMCU_760M,
-					 CK_TOP_CB_MM_D2 };
+					 CK_TOP_MMPLL_D2 };
 
 static const int sgm_325m_parents[] = { CK_TOP_XTAL,
 					CK_TOP_CB_SGM_325M };
 
-static const int sgm_reg_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D4 };
+static const int sgm_reg_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D8_D4 };
 
 static const int a1sys_parents[] = { CK_TOP_XTAL, CK_TOP_APLL2_D4 };
 
 static const int conn_mcusys_parents[] = { CK_TOP_XTAL,
-					   CK_TOP_CB_MM_D2 };
+					   CK_TOP_MMPLL_D2 };
 
-static const int eip_b_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET2_800M };
+static const int eip_b_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET2PLL_800M };
 
 static const int aud_l_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_196M,
-				     CK_TOP_M_D8_D2 };
+				     CK_TOP_MPLL_D8_D2 };
 
 static const int a_tuner_parents[] = { CK_TOP_XTAL, CK_TOP_APLL2_D4,
-				       CK_TOP_M_D8_D2 };
+				       CK_TOP_MPLL_D8_D2 };
 
-static const int u2u3_sys_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D4 };
+static const int u2u3_sys_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D4 };
 
 static const int da_u2_refsel_parents[] = { CK_TOP_XTAL,
-					    CK_TOP_CB_U2_PHYD_CK };
+					    CK_TOP_MMPLL_U2PHYD };
 
 #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,    \
 		_shift, _width, _gate, _upd_ofs, _upd)                         \
@@ -327,14 +335,14 @@ static const struct mtk_parent infra_spi1_parents[] = {
 };
 
 static const struct mtk_parent infra_pwm_bsel_parents[] = {
-	TOP_PARENT(CK_TOP_CB_RTC_32P7K),
+	TOP_PARENT(CK_TOP_RTC_32P7K),
 	TOP_PARENT(CK_TOP_F26M_SEL),
 	INFRA_PARENT(CK_INFRA_SYSAXI_D2),
 	TOP_PARENT(CK_TOP_PWM_SEL)
 };
 
 static const struct mtk_parent infra_pcie_parents[] = {
-	TOP_PARENT(CK_TOP_CB_RTC_32P7K),
+	TOP_PARENT(CK_TOP_RTC_32P7K),
 	TOP_PARENT(CK_TOP_F26M_SEL),
 	TOP_PARENT(CK_TOP_XTAL),
 	TOP_PARENT(CK_TOP_PEXTP_TL_SEL)
@@ -466,7 +474,7 @@ static const struct mtk_gate infracfg_ao_gates[] = {
 			  13),
 	GATE_INFRA1_INFRA(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_SYSAXI_D2,
 			  14),
-	GATE_INFRA1_TOP(CK_INFRA_FRTC_CK, "infra_frtc", CK_TOP_CB_RTC_32K, 15),
+	GATE_INFRA1_TOP(CK_INFRA_FRTC_CK, "infra_frtc", CK_TOP_RTC_32K, 15),
 	GATE_INFRA1_TOP(CK_INFRA_MSDC_CK, "infra_msdc", CK_TOP_EMMC_416M_SEL, 16),
 	GATE_INFRA1_TOP(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
 			CK_TOP_EMMC_250M_SEL, 17),
@@ -499,7 +507,7 @@ static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
 };
 
 static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
-	.fdivs_offs = CK_TOP_CB_M_416M,
+	.fdivs_offs = CK_TOP_MPLL_416M,
 	.muxes_offs = CK_TOP_NFI1X_SEL,
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index a48d57512d1..f19948cca16 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -16,36 +16,36 @@
 /* TOPCKGEN */
 
 #define CK_TOP_XTAL			0
-#define CK_TOP_CB_M_416M		1
-#define CK_TOP_CB_M_D2			2
-#define CK_TOP_CB_M_D4			3
-#define CK_TOP_CB_M_D8			4
-#define CK_TOP_M_D8_D2			5
-#define CK_TOP_M_D3_D2			6
-#define CK_TOP_CB_MM_D2			7
-#define CK_TOP_CB_MM_D4			8
-#define CK_TOP_CB_MM_D8			9
-#define CK_TOP_MM_D8_D2			10
-#define CK_TOP_MM_D3_D8			11
-#define CK_TOP_CB_U2_PHYD_CK		12
+#define CK_TOP_CB_MPLL_416M		1
+#define CK_TOP_MPLL_D2			2
+#define CK_TOP_MPLL_D4			3
+#define CK_TOP_MPLL_D8			4
+#define CK_TOP_MPLL_D8_D2		5
+#define CK_TOP_MPLL_D3_D2		6
+#define CK_TOP_MMPLL_D2			7
+#define CK_TOP_MMPLL_D4			8
+#define CK_TOP_MMPLL_D8			9
+#define CK_TOP_MMPLL_D8_D2		10
+#define CK_TOP_MMPLL_D3_D8		11
+#define CK_TOP_MMPLL_U2PHYD		12
 #define CK_TOP_CB_APLL2_196M		13
 #define CK_TOP_APLL2_D4			14
-#define CK_TOP_CB_NET1_D4		15
-#define CK_TOP_CB_NET1_D5		16
-#define CK_TOP_NET1_D5_D2		17
-#define CK_TOP_NET1_D5_D4		18
-#define CK_TOP_NET1_D8_D2		19
-#define CK_TOP_NET1_D8_D4		20
-#define CK_TOP_CB_NET2_800M		21
-#define CK_TOP_CB_NET2_D4		22
-#define CK_TOP_NET2_D4_D2		23
-#define CK_TOP_NET2_D3_D2		24
-#define CK_TOP_CB_WEDMCU_760M		25
-#define CK_TOP_WEDMCU_D5_D2		26
-#define CK_TOP_CB_SGM_325M		27
+#define CK_TOP_NET1PLL_D4		15
+#define CK_TOP_NET1PLL_D5		16
+#define CK_TOP_NET1PLL_D5_D2		17
+#define CK_TOP_NET1PLL_D5_D4		18
+#define CK_TOP_NET1PLL_D8_D2		19
+#define CK_TOP_NET1PLL_D8_D4		20
+#define CK_TOP_CB_NET2PLL_800M		21
+#define CK_TOP_NET2PLL_D4		22
+#define CK_TOP_NET2PLL_D4_D2		23
+#define CK_TOP_NET2PLL_D3_D2		24
+#define CK_TOP_CB_WEDMCUPLL_760M	25
+#define CK_TOP_WEDMCUPLL_D5_D2		26
+#define CK_TOP_CB_SGMPLL_325M		27
 #define CK_TOP_XTAL_D2			28
-#define CK_TOP_CB_RTC_32K		29
-#define CK_TOP_CB_RTC_32P7K		30
+#define CK_TOP_RTC_32K			29
+#define CK_TOP_RTC_32P7K		30
 #define CK_TOP_NFI1X			31
 #define CK_TOP_USB_EQ_RX250M		32
 #define CK_TOP_USB_TX250M		33
-- 
2.45.2

[PATCH 09/15] clk: mediatek: mt7986: reorder TOPCKGEN factor ID

[Christian Marangi]

Reorder TOPCKGEN factor ID to put TOP_FACTOR first and then PLL. This is
to match how it's done in upstream kernel linux and in preparation for
OF_UPSTREAM support.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7986.c      |  70 ++++++++--------
 include/dt-bindings/clock/mt7986-clk.h | 108 ++++++++++++-------------
 2 files changed, 89 insertions(+), 89 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index c1f63ecc3b2..34b8eba5398 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -46,6 +46,41 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
 
 /* TOPCKGEN FIXED DIV */
 static const struct mtk_fixed_factor top_fixed_divs[] = {
+	/* TOP Factors */
+	TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL,
+		   1, 2),
+	TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
+		   1250),
+	TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
+		   1220),
+	TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_XTAL, 1,
+		   1),
+	TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_XTAL, 1, 1),
+	TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_XTAL, 1, 1),
+	TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_XTAL, 1, 1),
+	TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1,
+		   1),
+	TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
+		   CK_TOP_NETSYS_MCU_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
+	TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
+	TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
+		   1),
 	/* MPLL */
 	PLL_FACTOR(CK_TOP_CB_MPLL_416M, "cb_mpll_416m", CK_APMIXED_MPLL, 1, 1),
 	PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
@@ -84,41 +119,6 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
 		   10),
 	/* SGMPLL */
 	PLL_FACTOR(CK_TOP_CB_SGMPLL_325M, "cb_sgmpll_325m", CK_APMIXED_SGMPLL, 1, 1),
-	/* TOPCKGEN and XTAL */
-	TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL,
-		   1, 2),
-	TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
-		   1250),
-	TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
-		   1220),
-	TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_XTAL, 1,
-		   1),
-	TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_XTAL, 1, 1),
-	TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_XTAL, 1, 1),
-	TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_XTAL, 1, 1),
-	TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1,
-		   1),
-	TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
-		   CK_TOP_NETSYS_MCU_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
-	TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
-		   1),
 };
 
 /* TOPCKGEN MUX PARENTS */
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index f19948cca16..0048d183389 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -16,60 +16,60 @@
 /* TOPCKGEN */
 
 #define CK_TOP_XTAL			0
-#define CK_TOP_CB_MPLL_416M		1
-#define CK_TOP_MPLL_D2			2
-#define CK_TOP_MPLL_D4			3
-#define CK_TOP_MPLL_D8			4
-#define CK_TOP_MPLL_D8_D2		5
-#define CK_TOP_MPLL_D3_D2		6
-#define CK_TOP_MMPLL_D2			7
-#define CK_TOP_MMPLL_D4			8
-#define CK_TOP_MMPLL_D8			9
-#define CK_TOP_MMPLL_D8_D2		10
-#define CK_TOP_MMPLL_D3_D8		11
-#define CK_TOP_MMPLL_U2PHYD		12
-#define CK_TOP_CB_APLL2_196M		13
-#define CK_TOP_APLL2_D4			14
-#define CK_TOP_NET1PLL_D4		15
-#define CK_TOP_NET1PLL_D5		16
-#define CK_TOP_NET1PLL_D5_D2		17
-#define CK_TOP_NET1PLL_D5_D4		18
-#define CK_TOP_NET1PLL_D8_D2		19
-#define CK_TOP_NET1PLL_D8_D4		20
-#define CK_TOP_CB_NET2PLL_800M		21
-#define CK_TOP_NET2PLL_D4		22
-#define CK_TOP_NET2PLL_D4_D2		23
-#define CK_TOP_NET2PLL_D3_D2		24
-#define CK_TOP_CB_WEDMCUPLL_760M	25
-#define CK_TOP_WEDMCUPLL_D5_D2		26
-#define CK_TOP_CB_SGMPLL_325M		27
-#define CK_TOP_XTAL_D2			28
-#define CK_TOP_RTC_32K			29
-#define CK_TOP_RTC_32P7K		30
-#define CK_TOP_NFI1X			31
-#define CK_TOP_USB_EQ_RX250M		32
-#define CK_TOP_USB_TX250M		33
-#define CK_TOP_USB_LN0_CK		34
-#define CK_TOP_USB_CDR_CK		35
-#define CK_TOP_SPINFI_BCK		36
-#define CK_TOP_I2C_BCK			37
-#define CK_TOP_PEXTP_TL			38
-#define CK_TOP_EMMC_250M		39
-#define CK_TOP_EMMC_416M		40
-#define CK_TOP_F_26M_ADC_CK		41
-#define CK_TOP_SYSAXI			42
-#define CK_TOP_NETSYS_WED_MCU		43
-#define CK_TOP_NETSYS_2X		44
-#define CK_TOP_SGM_325M			45
-#define CK_TOP_A1SYS			46
-#define CK_TOP_EIP_B			47
-#define CK_TOP_F26M			48
-#define CK_TOP_AUD_L			49
-#define CK_TOP_A_TUNER			50
-#define CK_TOP_U2U3_REF			51
-#define CK_TOP_U2U3_SYS			52
-#define CK_TOP_U2U3_XHCI		53
-#define CK_TOP_AP2CNN_HOST		54
+#define CK_TOP_XTAL_D2			1
+#define CK_TOP_RTC_32K			2
+#define CK_TOP_RTC_32P7K		3
+#define CK_TOP_NFI1X			4
+#define CK_TOP_USB_EQ_RX250M		5
+#define CK_TOP_USB_TX250M		6
+#define CK_TOP_USB_LN0_CK		7
+#define CK_TOP_USB_CDR_CK		8
+#define CK_TOP_SPINFI_BCK		9
+#define CK_TOP_I2C_BCK			10
+#define CK_TOP_PEXTP_TL			11
+#define CK_TOP_EMMC_250M		12
+#define CK_TOP_EMMC_416M		13
+#define CK_TOP_F_26M_ADC_CK		14
+#define CK_TOP_SYSAXI			15
+#define CK_TOP_NETSYS_WED_MCU		16
+#define CK_TOP_NETSYS_2X		17
+#define CK_TOP_SGM_325M			18
+#define CK_TOP_A1SYS			19
+#define CK_TOP_EIP_B			20
+#define CK_TOP_F26M			21
+#define CK_TOP_AUD_L			22
+#define CK_TOP_A_TUNER			23
+#define CK_TOP_U2U3_REF			24
+#define CK_TOP_U2U3_SYS			25
+#define CK_TOP_U2U3_XHCI		26
+#define CK_TOP_AP2CNN_HOST		27
+#define CK_TOP_CB_MPLL_416M		28
+#define CK_TOP_MPLL_D2			29
+#define CK_TOP_MPLL_D4			30
+#define CK_TOP_MPLL_D8			31
+#define CK_TOP_MPLL_D8_D2		32
+#define CK_TOP_MPLL_D3_D2		33
+#define CK_TOP_MMPLL_D2			34
+#define CK_TOP_MMPLL_D4			35
+#define CK_TOP_MMPLL_D8			36
+#define CK_TOP_MMPLL_D8_D2		37
+#define CK_TOP_MMPLL_D3_D8		38
+#define CK_TOP_MMPLL_U2PHYD		39
+#define CK_TOP_CB_APLL2_196M		40
+#define CK_TOP_APLL2_D4			41
+#define CK_TOP_NET1PLL_D4		42
+#define CK_TOP_NET1PLL_D5		43
+#define CK_TOP_NET1PLL_D5_D2		44
+#define CK_TOP_NET1PLL_D5_D4		45
+#define CK_TOP_NET1PLL_D8_D2		46
+#define CK_TOP_NET1PLL_D8_D4		47
+#define CK_TOP_CB_NET2PLL_800M		48
+#define CK_TOP_NET2PLL_D4		49
+#define CK_TOP_NET2PLL_D4_D2		50
+#define CK_TOP_NET2PLL_D3_D2		51
+#define CK_TOP_CB_WEDMCUPLL_760M	52
+#define CK_TOP_WEDMCUPLL_D5_D2		53
+#define CK_TOP_CB_SGMPLL_325M		54
 #define CK_TOP_NFI1X_SEL		55
 #define CK_TOP_SPINFI_SEL		56
 #define CK_TOP_SPI_SEL			57
-- 
2.45.2

[PATCH 10/15] clk: mediatek: mt7986: drop 1/1 spurious factor for topckgen

[Christian Marangi]

Now that we can have advanced parent handling for mux, we can drop
spurious topckgen 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7986.

Drop the factor entry from mt7986-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the apmixed clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for apmixed.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm/dts/mt7986.dtsi               |  14 +-
 drivers/clk/mediatek/clk-mt7986.c      | 223 +++++++++++++------------
 include/dt-bindings/clock/mt7986-clk.h | 150 +++++++----------
 3 files changed, 186 insertions(+), 201 deletions(-)

diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index 31119640d23..187e1298fae 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -162,7 +162,7 @@
 				  <&infracfg CK_INFRA_PWM_BSEL>,
 				  <&infracfg CK_INFRA_PWM1_SEL>,
 				  <&infracfg CK_INFRA_PWM2_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
+		assigned-clock-parents = <&topckgen CK_TOP_MPLL_D4>,
 					 <&topckgen CK_TOP_PWM_SEL>,
 					 <&topckgen CK_TOP_PWM_SEL>,
 					 <&topckgen CK_TOP_PWM_SEL>;
@@ -218,8 +218,8 @@
 		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
 		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
 				  <&topckgen CK_TOP_NFI1X_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
-					 <&topckgen CK_TOP_CB_M_D8>;
+		assigned-clock-parents = <&topckgen CK_TOP_MPLL_D8>,
+					 <&topckgen CK_TOP_MPLL_D8>;
 		status = "disabled";
 	};
 
@@ -262,7 +262,7 @@
 			 <&topckgen CK_TOP_SPI_SEL>;
 		assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
 				  <&infracfg CK_INFRA_SPI0_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
+		assigned-clock-parents = <&topckgen CK_TOP_MPLL_D2>,
 					 <&topckgen CK_TOP_SPI_SEL>;
 		clock-names = "sel-clk", "spi-clk";
 		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
@@ -281,12 +281,12 @@
 		reg = <0x11230000 0x1000>,
 		      <0x11C20000 0x1000>;
 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CK_TOP_EMMC_416M>,
-			<&topckgen CK_TOP_EMMC_250M>,
+		clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
+			<&topckgen CK_TOP_EMMC_250M_SEL>,
 			<&infracfg_ao CK_INFRA_MSDC_CK>;
 		assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
 				  <&topckgen CK_TOP_EMMC_250M_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>,
+		assigned-clock-parents = <&fixed_plls CK_APMIXED_MPLL>,
 					 <&topckgen CK_TOP_NET1PLL_D5_D2>;
 		clock-names = "source", "hclk", "source_cg";
 		status = "disabled";
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 34b8eba5398..d8e0a5790e3 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -18,6 +18,11 @@
 #define MT7986_CLK_PDN 0x250
 #define MT7986_CLK_PDN_EN_WRITE BIT(31)
 
+#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
+#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS)
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
+#define VOID_PARENT PARENT(-1, 0)
+
 #define PLL_FACTOR(_id, _name, _parent, _mult, _div)                           \
 	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
 
@@ -53,36 +58,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
 		   1250),
 	TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
 		   1220),
-	TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_XTAL, 1,
-		   1),
-	TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_XTAL, 1, 1),
-	TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_XTAL, 1, 1),
-	TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_XTAL, 1, 1),
-	TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1,
-		   1),
-	TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
-		   CK_TOP_NETSYS_MCU_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
 	TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
-	TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
-	TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
-		   1),
 	/* MPLL */
-	PLL_FACTOR(CK_TOP_CB_MPLL_416M, "cb_mpll_416m", CK_APMIXED_MPLL, 1, 1),
 	PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
 	PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
 	PLL_FACTOR(CK_TOP_MPLL_D8, "mpll_d8", CK_APMIXED_MPLL, 1, 8),
@@ -96,8 +73,6 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
 	PLL_FACTOR(CK_TOP_MMPLL_D3_D8, "mmpll_d3_d8", CK_APMIXED_MMPLL, 1, 8),
 	PLL_FACTOR(CK_TOP_MMPLL_U2PHYD, "mmpll_u2phy", CK_APMIXED_MMPLL, 1, 30),
 	/* APLL2 */
-	PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
-		   1),
 	PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
 	/* NET1PLL */
 	PLL_FACTOR(CK_TOP_NET1PLL_D4, "net1pll_d4", CK_APMIXED_NET1PLL, 1, 4),
@@ -107,107 +82,146 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
 	PLL_FACTOR(CK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
 	PLL_FACTOR(CK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
 	/* NET2PLL */
-	PLL_FACTOR(CK_TOP_CB_NET2PLL_800M, "cb_net2pll_800m", CK_APMIXED_NET2PLL, 1,
-		   1),
 	PLL_FACTOR(CK_TOP_NET2PLL_D4, "net2pll_d4", CK_APMIXED_NET2PLL, 1, 4),
 	PLL_FACTOR(CK_TOP_NET2PLL_D4_D2, "net2pll_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
 	PLL_FACTOR(CK_TOP_NET2PLL_D3_D2, "net2pll_d3_d2", CK_APMIXED_NET2PLL, 1, 2),
 	/* WEDMCUPLL */
-	PLL_FACTOR(CK_TOP_CB_WEDMCUPLL_760M, "cb_wedmcupll_760m",
-		   CK_APMIXED_WEDMCUPLL, 1, 1),
 	PLL_FACTOR(CK_TOP_WEDMCUPLL_D5_D2, "wedmcupll_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
 		   10),
-	/* SGMPLL */
-	PLL_FACTOR(CK_TOP_CB_SGMPLL_325M, "cb_sgmpll_325m", CK_APMIXED_SGMPLL, 1, 1),
 };
 
 /* TOPCKGEN MUX PARENTS */
-static const int nfi1x_parents[] = { CK_TOP_XTAL,  CK_TOP_MMPLL_D8,
-				     CK_TOP_NET1PLL_D8_D2,   CK_TOP_NET2PLL_D3_D2,
-				     CK_TOP_MPLL_D4,      CK_TOP_MMPLL_D8_D2,
-				     CK_TOP_WEDMCUPLL_D5_D2, CK_TOP_MPLL_D8 };
+static const struct mtk_parent nfi1x_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D8),
+	TOP_PARENT(CK_TOP_NET1PLL_D8_D2), TOP_PARENT(CK_TOP_NET2PLL_D3_D2),
+	TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_MMPLL_D8_D2),
+	TOP_PARENT(CK_TOP_WEDMCUPLL_D5_D2), TOP_PARENT(CK_TOP_MPLL_D8),
+};
 
-static const int spinfi_parents[] = {
-	CK_TOP_XTAL_D2, CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D4,
-	CK_TOP_MPLL_D4,	CK_TOP_MMPLL_D8_D2,    CK_TOP_WEDMCUPLL_D5_D2,
-	CK_TOP_MMPLL_D3_D8,       CK_TOP_MPLL_D8
+static const struct mtk_parent spinfi_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_XTAL),
+	TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
+	TOP_PARENT(CK_TOP_MMPLL_D8_D2), TOP_PARENT(CK_TOP_WEDMCUPLL_D5_D2),
+	TOP_PARENT(CK_TOP_MMPLL_D3_D8), TOP_PARENT(CK_TOP_MPLL_D8),
 };
 
-static const int spi_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D2,
-				   CK_TOP_MMPLL_D8,    CK_TOP_NET1PLL_D8_D2,
-				   CK_TOP_NET2PLL_D3_D2,  CK_TOP_NET1PLL_D5_D4,
-				   CK_TOP_MPLL_D4,     CK_TOP_WEDMCUPLL_D5_D2 };
+static const struct mtk_parent spi_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
+	TOP_PARENT(CK_TOP_MMPLL_D8), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
+	TOP_PARENT(CK_TOP_NET2PLL_D3_D2), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
+	TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_WEDMCUPLL_D5_D2),
+};
 
-static const int uart_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D8,
-				    CK_TOP_MPLL_D8_D2 };
+static const struct mtk_parent uart_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D8),
+	TOP_PARENT(CK_TOP_MPLL_D8_D2),
+};
 
-static const int pwm_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D8_D2,
-				   CK_TOP_NET1PLL_D5_D4, CK_TOP_MPLL_D4 };
+static const struct mtk_parent pwm_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
+	TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
+};
 
-static const int i2c_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D4,
-				   CK_TOP_MPLL_D4, CK_TOP_NET1PLL_D8_D4 };
+static const struct mtk_parent i2c_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
+	TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+};
 
-static const int pextp_tl_ck_parents[] = { CK_TOP_XTAL,
-					   CK_TOP_NET1PLL_D5_D4, CK_TOP_NET2PLL_D4_D2,
-					   CK_TOP_RTC_32K };
+static const struct mtk_parent pextp_tl_ck_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
+	TOP_PARENT(CK_TOP_NET2PLL_D4_D2), TOP_PARENT(CK_TOP_RTC_32K),
+};
 
-static const int emmc_250m_parents[] = { CK_TOP_XTAL,
-					 CK_TOP_NET1PLL_D5_D2 };
+static const struct mtk_parent emmc_250m_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
+};
 
-static const int emmc_416m_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_416M };
+static const struct mtk_parent emmc_416m_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_MPLL),
+};
 
-static const int f_26m_adc_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D8_D2 };
+static const struct mtk_parent f_26m_adc_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D8_D2),
+};
 
-static const int dramc_md32_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D2 };
+static const struct mtk_parent dramc_md32_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
+};
 
-static const int sysaxi_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D8_D2,
-				      CK_TOP_NET2PLL_D4 };
+static const struct mtk_parent sysaxi_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
+	TOP_PARENT(CK_TOP_NET2PLL_D4),
+};
 
-static const int sysapb_parents[] = { CK_TOP_XTAL, CK_TOP_MPLL_D3_D2,
-				      CK_TOP_NET2PLL_D4_D2 };
+static const struct mtk_parent sysapb_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D3_D2),
+	TOP_PARENT(CK_TOP_NET2PLL_D4_D2),
+};
 
-static const int arm_db_main_parents[] = { CK_TOP_XTAL,
-					   CK_TOP_NET2PLL_D3_D2 };
+static const struct mtk_parent arm_db_main_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D3_D2),
+};
 
-static const int arm_db_jtsel_parents[] = { -1, CK_TOP_XTAL };
+static const struct mtk_parent arm_db_jtsel_parents[] = {
+	VOID_PARENT, TOP_PARENT(CK_TOP_XTAL),
+};
 
-static const int netsys_parents[] = { CK_TOP_XTAL, CK_TOP_MMPLL_D4 };
+static const struct mtk_parent netsys_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D4),
+};
 
-static const int netsys_500m_parents[] = { CK_TOP_XTAL,
-					   CK_TOP_NET1PLL_D5 };
+static const struct mtk_parent netsys_500m_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5),
+};
 
-static const int netsys_mcu_parents[] = { CK_TOP_XTAL,
-					  CK_TOP_CB_WEDMCU_760M,
-					  CK_TOP_MMPLL_D2, CK_TOP_NET1PLL_D4,
-					  CK_TOP_NET1PLL_D5 };
+static const struct mtk_parent netsys_mcu_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_WEDMCUPLL),
+	TOP_PARENT(CK_TOP_MMPLL_D2), TOP_PARENT(CK_TOP_NET1PLL_D4),
+	TOP_PARENT(CK_TOP_NET1PLL_D5),
+};
 
-static const int netsys_2x_parents[] = { CK_TOP_XTAL,
-					 CK_TOP_CB_NET2PLL_800M,
-					 CK_TOP_CB_WEDMCU_760M,
-					 CK_TOP_MMPLL_D2 };
+static const struct mtk_parent netsys_2x_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_APMIXED_NET2PLL),
+	APMIXED_PARENT(CK_APMIXED_WEDMCUPLL), TOP_PARENT(CK_TOP_MMPLL_D2),
+};
 
-static const int sgm_325m_parents[] = { CK_TOP_XTAL,
-					CK_TOP_CB_SGM_325M };
+static const struct mtk_parent sgm_325m_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_SGMPLL),
+};
 
-static const int sgm_reg_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D8_D4 };
+static const struct mtk_parent sgm_reg_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+};
 
-static const int a1sys_parents[] = { CK_TOP_XTAL, CK_TOP_APLL2_D4 };
+static const struct mtk_parent a1sys_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_APLL2_D4),
+};
 
-static const int conn_mcusys_parents[] = { CK_TOP_XTAL,
-					   CK_TOP_MMPLL_D2 };
+static const struct mtk_parent conn_mcusys_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D2),
+};
 
-static const int eip_b_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET2PLL_800M };
+static const struct mtk_parent eip_b_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
+};
 
-static const int aud_l_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_196M,
-				     CK_TOP_MPLL_D8_D2 };
+static const struct mtk_parent aud_l_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_APLL2),
+	TOP_PARENT(CK_TOP_MPLL_D8_D2),
+};
 
-static const int a_tuner_parents[] = { CK_TOP_XTAL, CK_TOP_APLL2_D4,
-				       CK_TOP_MPLL_D8_D2 };
+static const struct mtk_parent a_tuner_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_APLL2_D4),
+	TOP_PARENT(CK_TOP_MPLL_D8_D2),
+};
 
-static const int u2u3_sys_parents[] = { CK_TOP_XTAL, CK_TOP_NET1PLL_D5_D4 };
+static const struct mtk_parent u2u3_sys_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
+};
 
-static const int da_u2_refsel_parents[] = { CK_TOP_XTAL,
-					    CK_TOP_MMPLL_U2PHYD };
+static const struct mtk_parent da_u2_refsel_parents[] = {
+	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_U2PHYD),
+};
 
 #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,    \
 		_shift, _width, _gate, _upd_ofs, _upd)                         \
@@ -216,9 +230,9 @@ static const int da_u2_refsel_parents[] = { CK_TOP_XTAL,
 		.mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs,              \
 		.upd_shift = _upd, .mux_shift = _shift,                        \
 		.mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs,             \
-		.gate_shift = _gate, .parent = _parents,                       \
+		.gate_shift = _gate, .parent_flags = _parents,                 \
 		.num_parents = ARRAY_SIZE(_parents),                           \
-		.flags = CLK_MUX_SETCLR_UPD,                                   \
+		.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED,                \
 	}
 
 /* TOPCKGEN MUX_GATE */
@@ -315,9 +329,7 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
 };
 
 /* INFRASYS MUX PARENTS */
-#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS)
-#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
-#define VOID_PARENT PARENT(-1, 0)
+
 
 static const struct mtk_parent infra_uart0_parents[] = {
 	TOP_PARENT(CK_TOP_F26M_SEL),
@@ -504,10 +516,11 @@ static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
 	.fdivs_offs = CLK_APMIXED_NR_CLK,
 	.xtal_rate = 40 * MHZ,
 	.fclks = fixed_pll_clks,
+	.flags = CLK_APMIXED,
 };
 
 static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
-	.fdivs_offs = CK_TOP_MPLL_416M,
+	.fdivs_offs = CK_TOP_XTAL_D2,
 	.muxes_offs = CK_TOP_NFI1X_SEL,
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
@@ -623,11 +636,11 @@ static const struct mtk_gate_regs eth_cg_regs = {
 	}
 
 static const struct mtk_gate eth_cgs[] = {
-	GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 7),
-	GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 8),
-	GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
-	GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_WED_MCU, 14),
-	GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
+	GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X_SEL, 7),
+	GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M_SEL, 8),
+	GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M_SEL, 8),
+	GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_MCU_SEL, 14),
+	GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_MCU_SEL, 15),
 };
 
 static int mt7986_ethsys_probe(struct udevice *dev)
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 0048d183389..478538d7cce 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -19,95 +19,67 @@
 #define CK_TOP_XTAL_D2			1
 #define CK_TOP_RTC_32K			2
 #define CK_TOP_RTC_32P7K		3
-#define CK_TOP_NFI1X			4
-#define CK_TOP_USB_EQ_RX250M		5
-#define CK_TOP_USB_TX250M		6
-#define CK_TOP_USB_LN0_CK		7
-#define CK_TOP_USB_CDR_CK		8
-#define CK_TOP_SPINFI_BCK		9
-#define CK_TOP_I2C_BCK			10
-#define CK_TOP_PEXTP_TL			11
-#define CK_TOP_EMMC_250M		12
-#define CK_TOP_EMMC_416M		13
-#define CK_TOP_F_26M_ADC_CK		14
-#define CK_TOP_SYSAXI			15
-#define CK_TOP_NETSYS_WED_MCU		16
-#define CK_TOP_NETSYS_2X		17
-#define CK_TOP_SGM_325M			18
-#define CK_TOP_A1SYS			19
-#define CK_TOP_EIP_B			20
-#define CK_TOP_F26M			21
-#define CK_TOP_AUD_L			22
-#define CK_TOP_A_TUNER			23
-#define CK_TOP_U2U3_REF			24
-#define CK_TOP_U2U3_SYS			25
-#define CK_TOP_U2U3_XHCI		26
-#define CK_TOP_AP2CNN_HOST		27
-#define CK_TOP_CB_MPLL_416M		28
-#define CK_TOP_MPLL_D2			29
-#define CK_TOP_MPLL_D4			30
-#define CK_TOP_MPLL_D8			31
-#define CK_TOP_MPLL_D8_D2		32
-#define CK_TOP_MPLL_D3_D2		33
-#define CK_TOP_MMPLL_D2			34
-#define CK_TOP_MMPLL_D4			35
-#define CK_TOP_MMPLL_D8			36
-#define CK_TOP_MMPLL_D8_D2		37
-#define CK_TOP_MMPLL_D3_D8		38
-#define CK_TOP_MMPLL_U2PHYD		39
-#define CK_TOP_CB_APLL2_196M		40
-#define CK_TOP_APLL2_D4			41
-#define CK_TOP_NET1PLL_D4		42
-#define CK_TOP_NET1PLL_D5		43
-#define CK_TOP_NET1PLL_D5_D2		44
-#define CK_TOP_NET1PLL_D5_D4		45
-#define CK_TOP_NET1PLL_D8_D2		46
-#define CK_TOP_NET1PLL_D8_D4		47
-#define CK_TOP_CB_NET2PLL_800M		48
-#define CK_TOP_NET2PLL_D4		49
-#define CK_TOP_NET2PLL_D4_D2		50
-#define CK_TOP_NET2PLL_D3_D2		51
-#define CK_TOP_CB_WEDMCUPLL_760M	52
-#define CK_TOP_WEDMCUPLL_D5_D2		53
-#define CK_TOP_CB_SGMPLL_325M		54
-#define CK_TOP_NFI1X_SEL		55
-#define CK_TOP_SPINFI_SEL		56
-#define CK_TOP_SPI_SEL			57
-#define CK_TOP_SPIM_MST_SEL		58
-#define CK_TOP_UART_SEL			59
-#define CK_TOP_PWM_SEL			60
-#define CK_TOP_I2C_SEL			61
-#define CK_TOP_PEXTP_TL_SEL		62
-#define CK_TOP_EMMC_250M_SEL		63
-#define CK_TOP_EMMC_416M_SEL		64
-#define CK_TOP_F_26M_ADC_SEL		65
-#define CK_TOP_DRAMC_SEL		66
-#define CK_TOP_DRAMC_MD32_SEL		67
-#define CK_TOP_SYSAXI_SEL		68
-#define CK_TOP_SYSAPB_SEL		69
-#define CK_TOP_ARM_DB_MAIN_SEL		70
-#define CK_TOP_ARM_DB_JTSEL		71
-#define CK_TOP_NETSYS_SEL		72
-#define CK_TOP_NETSYS_500M_SEL		73
-#define CK_TOP_NETSYS_MCU_SEL		74
-#define CK_TOP_NETSYS_2X_SEL		75
-#define CK_TOP_SGM_325M_SEL		76
-#define CK_TOP_SGM_REG_SEL		77
-#define CK_TOP_A1SYS_SEL		78
-#define CK_TOP_CONN_MCUSYS_SEL		79
-#define CK_TOP_EIP_B_SEL		80
-#define CK_TOP_PCIE_PHY_SEL		81
-#define CK_TOP_USB3_PHY_SEL		82
-#define CK_TOP_F26M_SEL			83
-#define CK_TOP_AUD_L_SEL		84
-#define CK_TOP_A_TUNER_SEL		85
-#define CK_TOP_U2U3_SEL			86
-#define CK_TOP_U2U3_SYS_SEL		87
-#define CK_TOP_U2U3_XHCI_SEL		88
-#define CK_TOP_DA_U2_REFSEL		89
-#define CK_TOP_DA_U2_CK_1P_SEL		90
-#define CK_TOP_AP2CNN_HOST_SEL		91
-#define CLK_TOP_NR_CLK			92
+#define CK_TOP_A_TUNER			4
+#define CK_TOP_MPLL_D2			5
+#define CK_TOP_MPLL_D4			6
+#define CK_TOP_MPLL_D8			7
+#define CK_TOP_MPLL_D8_D2		8
+#define CK_TOP_MPLL_D3_D2		9
+#define CK_TOP_MMPLL_D2			10
+#define CK_TOP_MMPLL_D4			11
+#define CK_TOP_MMPLL_D8			12
+#define CK_TOP_MMPLL_D8_D2		13
+#define CK_TOP_MMPLL_D3_D8		14
+#define CK_TOP_MMPLL_U2PHYD		15
+#define CK_TOP_APLL2_D4			16
+#define CK_TOP_NET1PLL_D4		17
+#define CK_TOP_NET1PLL_D5		18
+#define CK_TOP_NET1PLL_D5_D2		19
+#define CK_TOP_NET1PLL_D5_D4		20
+#define CK_TOP_NET1PLL_D8_D2		21
+#define CK_TOP_NET1PLL_D8_D4		22
+#define CK_TOP_NET2PLL_D4		23
+#define CK_TOP_NET2PLL_D4_D2		24
+#define CK_TOP_NET2PLL_D3_D2		25
+#define CK_TOP_WEDMCUPLL_D5_D2		26
+#define CK_TOP_NFI1X_SEL		27
+#define CK_TOP_SPINFI_SEL		28
+#define CK_TOP_SPI_SEL			29
+#define CK_TOP_SPIM_MST_SEL		30
+#define CK_TOP_UART_SEL			31
+#define CK_TOP_PWM_SEL			32
+#define CK_TOP_I2C_SEL			33
+#define CK_TOP_PEXTP_TL_SEL		34
+#define CK_TOP_EMMC_250M_SEL		35
+#define CK_TOP_EMMC_416M_SEL		36
+#define CK_TOP_F_26M_ADC_SEL		37
+#define CK_TOP_DRAMC_SEL		38
+#define CK_TOP_DRAMC_MD32_SEL		39
+#define CK_TOP_SYSAXI_SEL		40
+#define CK_TOP_SYSAPB_SEL		41
+#define CK_TOP_ARM_DB_MAIN_SEL		42
+#define CK_TOP_ARM_DB_JTSEL		43
+#define CK_TOP_NETSYS_SEL		44
+#define CK_TOP_NETSYS_500M_SEL		45
+#define CK_TOP_NETSYS_MCU_SEL		46
+#define CK_TOP_NETSYS_2X_SEL		47
+#define CK_TOP_SGM_325M_SEL		48
+#define CK_TOP_SGM_REG_SEL		49
+#define CK_TOP_A1SYS_SEL		50
+#define CK_TOP_CONN_MCUSYS_SEL		51
+#define CK_TOP_EIP_B_SEL		52
+#define CK_TOP_PCIE_PHY_SEL		53
+#define CK_TOP_USB3_PHY_SEL		54
+#define CK_TOP_F26M_SEL			55
+#define CK_TOP_AUD_L_SEL		56
+#define CK_TOP_A_TUNER_SEL		57
+#define CK_TOP_U2U3_SEL			58
+#define CK_TOP_U2U3_SYS_SEL		59
+#define CK_TOP_U2U3_XHCI_SEL		60
+#define CK_TOP_DA_U2_REFSEL		61
+#define CK_TOP_DA_U2_CK_1P_SEL		62
+#define CK_TOP_AP2CNN_HOST_SEL		63
+#define CLK_TOP_NR_CLK			64
 
 /*
  * INFRACFG_AO
-- 
2.45.2

[PATCH 11/15] clk: mediatek: mt7986: comment out CK_TOP_A_TUNER as not used

[Christian Marangi]

Comment out CK_TOP_A_TUNER as not used and not defined in upstream
kernel linux. This is to permit support of OF_UPSTREAM and have a 1:1
match with upstream linux clock ID.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7986.c      |   3 +-
 include/dt-bindings/clock/mt7986-clk.h | 122 ++++++++++++-------------
 2 files changed, 63 insertions(+), 62 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index d8e0a5790e3..08b7ab8a81e 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -58,7 +58,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
 		   1250),
 	TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
 		   1220),
-	TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
+	/* Not defined upstream and not used */
+	/* TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1), */
 	/* MPLL */
 	PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
 	PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 478538d7cce..7df13665900 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -19,67 +19,67 @@
 #define CK_TOP_XTAL_D2			1
 #define CK_TOP_RTC_32K			2
 #define CK_TOP_RTC_32P7K		3
-#define CK_TOP_A_TUNER			4
-#define CK_TOP_MPLL_D2			5
-#define CK_TOP_MPLL_D4			6
-#define CK_TOP_MPLL_D8			7
-#define CK_TOP_MPLL_D8_D2		8
-#define CK_TOP_MPLL_D3_D2		9
-#define CK_TOP_MMPLL_D2			10
-#define CK_TOP_MMPLL_D4			11
-#define CK_TOP_MMPLL_D8			12
-#define CK_TOP_MMPLL_D8_D2		13
-#define CK_TOP_MMPLL_D3_D8		14
-#define CK_TOP_MMPLL_U2PHYD		15
-#define CK_TOP_APLL2_D4			16
-#define CK_TOP_NET1PLL_D4		17
-#define CK_TOP_NET1PLL_D5		18
-#define CK_TOP_NET1PLL_D5_D2		19
-#define CK_TOP_NET1PLL_D5_D4		20
-#define CK_TOP_NET1PLL_D8_D2		21
-#define CK_TOP_NET1PLL_D8_D4		22
-#define CK_TOP_NET2PLL_D4		23
-#define CK_TOP_NET2PLL_D4_D2		24
-#define CK_TOP_NET2PLL_D3_D2		25
-#define CK_TOP_WEDMCUPLL_D5_D2		26
-#define CK_TOP_NFI1X_SEL		27
-#define CK_TOP_SPINFI_SEL		28
-#define CK_TOP_SPI_SEL			29
-#define CK_TOP_SPIM_MST_SEL		30
-#define CK_TOP_UART_SEL			31
-#define CK_TOP_PWM_SEL			32
-#define CK_TOP_I2C_SEL			33
-#define CK_TOP_PEXTP_TL_SEL		34
-#define CK_TOP_EMMC_250M_SEL		35
-#define CK_TOP_EMMC_416M_SEL		36
-#define CK_TOP_F_26M_ADC_SEL		37
-#define CK_TOP_DRAMC_SEL		38
-#define CK_TOP_DRAMC_MD32_SEL		39
-#define CK_TOP_SYSAXI_SEL		40
-#define CK_TOP_SYSAPB_SEL		41
-#define CK_TOP_ARM_DB_MAIN_SEL		42
-#define CK_TOP_ARM_DB_JTSEL		43
-#define CK_TOP_NETSYS_SEL		44
-#define CK_TOP_NETSYS_500M_SEL		45
-#define CK_TOP_NETSYS_MCU_SEL		46
-#define CK_TOP_NETSYS_2X_SEL		47
-#define CK_TOP_SGM_325M_SEL		48
-#define CK_TOP_SGM_REG_SEL		49
-#define CK_TOP_A1SYS_SEL		50
-#define CK_TOP_CONN_MCUSYS_SEL		51
-#define CK_TOP_EIP_B_SEL		52
-#define CK_TOP_PCIE_PHY_SEL		53
-#define CK_TOP_USB3_PHY_SEL		54
-#define CK_TOP_F26M_SEL			55
-#define CK_TOP_AUD_L_SEL		56
-#define CK_TOP_A_TUNER_SEL		57
-#define CK_TOP_U2U3_SEL			58
-#define CK_TOP_U2U3_SYS_SEL		59
-#define CK_TOP_U2U3_XHCI_SEL		60
-#define CK_TOP_DA_U2_REFSEL		61
-#define CK_TOP_DA_U2_CK_1P_SEL		62
-#define CK_TOP_AP2CNN_HOST_SEL		63
-#define CLK_TOP_NR_CLK			64
+/* #define CK_TOP_A_TUNER		4 */
+#define CK_TOP_MPLL_D2			4
+#define CK_TOP_MPLL_D4			5
+#define CK_TOP_MPLL_D8			6
+#define CK_TOP_MPLL_D8_D2		7
+#define CK_TOP_MPLL_D3_D2		8
+#define CK_TOP_MMPLL_D2			9
+#define CK_TOP_MMPLL_D4			10
+#define CK_TOP_MMPLL_D8			11
+#define CK_TOP_MMPLL_D8_D2		12
+#define CK_TOP_MMPLL_D3_D8		13
+#define CK_TOP_MMPLL_U2PHYD		14
+#define CK_TOP_APLL2_D4			15
+#define CK_TOP_NET1PLL_D4		16
+#define CK_TOP_NET1PLL_D5		17
+#define CK_TOP_NET1PLL_D5_D2		18
+#define CK_TOP_NET1PLL_D5_D4		19
+#define CK_TOP_NET1PLL_D8_D2		20
+#define CK_TOP_NET1PLL_D8_D4		21
+#define CK_TOP_NET2PLL_D4		22
+#define CK_TOP_NET2PLL_D4_D2		23
+#define CK_TOP_NET2PLL_D3_D2		24
+#define CK_TOP_WEDMCUPLL_D5_D2		25
+#define CK_TOP_NFI1X_SEL		26
+#define CK_TOP_SPINFI_SEL		27
+#define CK_TOP_SPI_SEL			28
+#define CK_TOP_SPIM_MST_SEL		29
+#define CK_TOP_UART_SEL			30
+#define CK_TOP_PWM_SEL			31
+#define CK_TOP_I2C_SEL			32
+#define CK_TOP_PEXTP_TL_SEL		33
+#define CK_TOP_EMMC_250M_SEL		34
+#define CK_TOP_EMMC_416M_SEL		35
+#define CK_TOP_F_26M_ADC_SEL		36
+#define CK_TOP_DRAMC_SEL		37
+#define CK_TOP_DRAMC_MD32_SEL		38
+#define CK_TOP_SYSAXI_SEL		39
+#define CK_TOP_SYSAPB_SEL		40
+#define CK_TOP_ARM_DB_MAIN_SEL		41
+#define CK_TOP_ARM_DB_JTSEL		42
+#define CK_TOP_NETSYS_SEL		43
+#define CK_TOP_NETSYS_500M_SEL		44
+#define CK_TOP_NETSYS_MCU_SEL		45
+#define CK_TOP_NETSYS_2X_SEL		46
+#define CK_TOP_SGM_325M_SEL		47
+#define CK_TOP_SGM_REG_SEL		48
+#define CK_TOP_A1SYS_SEL		49
+#define CK_TOP_CONN_MCUSYS_SEL		50
+#define CK_TOP_EIP_B_SEL		51
+#define CK_TOP_PCIE_PHY_SEL		52
+#define CK_TOP_USB3_PHY_SEL		53
+#define CK_TOP_F26M_SEL			54
+#define CK_TOP_AUD_L_SEL		55
+#define CK_TOP_A_TUNER_SEL		56
+#define CK_TOP_U2U3_SEL			57
+#define CK_TOP_U2U3_SYS_SEL		58
+#define CK_TOP_U2U3_XHCI_SEL		59
+#define CK_TOP_DA_U2_REFSEL		60
+#define CK_TOP_DA_U2_CK_1P_SEL		61
+#define CK_TOP_AP2CNN_HOST_SEL		62
+#define CLK_TOP_NR_CLK			63
 
 /*
  * INFRACFG_AO
-- 
2.45.2

[PATCH 12/15] clk: mediatek: mt7986: move INFRA_TRNG_CK to the bottom of the list

[Christian Marangi]

Move INFRA_TRNG_CK to the bottom of the list to have a 1:1 match with
upstream linux clock ID.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7986.c      |  3 +-
 include/dt-bindings/clock/mt7986-clk.h | 54 +++++++++++++-------------
 2 files changed, 29 insertions(+), 28 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 08b7ab8a81e..7476024f584 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -470,7 +470,6 @@ static const struct mtk_gate infracfg_ao_gates[] = {
 	GATE_INFRA0_INFRA(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_SYSAXI_D2, 16),
 	GATE_INFRA0_INFRA(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_SYSAXI_D2, 24),
 	GATE_INFRA0_TOP(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_TOP_F26M_SEL, 25),
-	GATE_INFRA0_TOP(CK_INFRA_TRNG_CK, "infra_trng", CK_TOP_SYSAXI_SEL, 26),
 	/* INFRA1 */
 	GATE_INFRA1_TOP(CK_INFRA_THERM_CK, "infra_therm", CK_TOP_F26M_SEL, 0),
 	GATE_INFRA1_TOP(CK_INFRA_I2C0_CK, "infra_i2co", CK_TOP_I2C_SEL, 1),
@@ -511,6 +510,8 @@ static const struct mtk_gate infracfg_ao_gates[] = {
 	GATE_INFRA2_TOP(CK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CK_TOP_XTAL, 13),
 	GATE_INFRA2_TOP(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_TOP_F26M_SEL, 14),
 	GATE_INFRA2_TOP(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_TOP_SYSAXI_SEL, 15),
+	/* upstream linux unordered */
+	GATE_INFRA0_TOP(CK_INFRA_TRNG_CK, "infra_trng", CK_TOP_SYSAXI_SEL, 26),
 };
 
 static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 7df13665900..39939f8e028 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -115,33 +115,33 @@
 #define CK_INFRA_SEJ_13M_CK		16
 #define CK_INFRA_THERM_CK		17
 #define CK_INFRA_I2C0_CK		18
-#define CK_INFRA_TRNG_CK		19
-#define CK_INFRA_UART0_CK		20
-#define CK_INFRA_UART1_CK		21
-#define CK_INFRA_UART2_CK		22
-#define CK_INFRA_NFI1_CK		23
-#define CK_INFRA_SPINFI1_CK		24
-#define CK_INFRA_NFI_HCK_CK		25
-#define CK_INFRA_SPI0_CK		26
-#define CK_INFRA_SPI1_CK		27
-#define CK_INFRA_SPI0_HCK_CK		28
-#define CK_INFRA_SPI1_HCK_CK		29
-#define CK_INFRA_FRTC_CK		30
-#define CK_INFRA_MSDC_CK		31
-#define CK_INFRA_MSDC_HCK_CK		32
-#define CK_INFRA_MSDC_133M_CK		33
-#define CK_INFRA_MSDC_66M_CK		34
-#define CK_INFRA_ADC_26M_CK		35
-#define CK_INFRA_ADC_FRC_CK		36
-#define CK_INFRA_FBIST2FPC_CK		37
-#define CK_INFRA_IUSB_133_CK		38
-#define CK_INFRA_IUSB_66M_CK		39
-#define CK_INFRA_IUSB_SYS_CK		40
-#define CK_INFRA_IUSB_CK		41
-#define CK_INFRA_IPCIE_CK		42
-#define CK_INFRA_IPCIE_PIPE_CK		43
-#define CK_INFRA_IPCIER_CK		44
-#define CK_INFRA_IPCIEB_CK		45
+#define CK_INFRA_UART0_CK		19
+#define CK_INFRA_UART1_CK		20
+#define CK_INFRA_UART2_CK		21
+#define CK_INFRA_NFI1_CK		22
+#define CK_INFRA_SPINFI1_CK		23
+#define CK_INFRA_NFI_HCK_CK		24
+#define CK_INFRA_SPI0_CK		25
+#define CK_INFRA_SPI1_CK		26
+#define CK_INFRA_SPI0_HCK_CK		27
+#define CK_INFRA_SPI1_HCK_CK		28
+#define CK_INFRA_FRTC_CK		29
+#define CK_INFRA_MSDC_CK		30
+#define CK_INFRA_MSDC_HCK_CK		31
+#define CK_INFRA_MSDC_133M_CK		32
+#define CK_INFRA_MSDC_66M_CK		33
+#define CK_INFRA_ADC_26M_CK		34
+#define CK_INFRA_ADC_FRC_CK		35
+#define CK_INFRA_FBIST2FPC_CK		36
+#define CK_INFRA_IUSB_133_CK		37
+#define CK_INFRA_IUSB_66M_CK		38
+#define CK_INFRA_IUSB_SYS_CK		39
+#define CK_INFRA_IUSB_CK		40
+#define CK_INFRA_IPCIE_CK		41
+#define CK_INFRA_IPCIE_PIPE_CK		42
+#define CK_INFRA_IPCIER_CK		43
+#define CK_INFRA_IPCIEB_CK		44
+#define CK_INFRA_TRNG_CK		45
 #define CLK_INFRA_AO_NR_CLK		46
 
 /* APMIXEDSYS */
-- 
2.45.2

[PATCH 13/15] clk: mediatek: mt7986: replace infracfg ID with upstream linux

[Christian Marangi]

Replace infracfg clk ID with upstream linux version.

The same format is used here with the factor first, then mux and then
gates.

To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7986.c      |   1 +
 include/dt-bindings/clock/mt7986-clk.h | 124 ++++++++++++-------------
 2 files changed, 59 insertions(+), 66 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 7476024f584..59b82ca7de1 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -533,6 +533,7 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
 static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
 	.fdivs_offs = CK_INFRA_SYSAXI_D2,
 	.muxes_offs = CK_INFRA_UART0_SEL,
+	.gates_offs = CK_INFRA_GPT_STA,
 	.fdivs = infra_fixed_divs,
 	.muxes = infra_muxes,
 	.flags = CLK_INFRASYS,
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 39939f8e028..1c28ab34dcf 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -8,11 +8,6 @@
 #ifndef _DT_BINDINGS_CLK_MT7986_H
 #define _DT_BINDINGS_CLK_MT7986_H
 
-/* INFRACFG */
-
-#define CK_INFRA_SYSAXI_D2		0
-#define CLK_INFRA_NR_CLK		1
-
 /* TOPCKGEN */
 
 #define CK_TOP_XTAL			0
@@ -81,68 +76,65 @@
 #define CK_TOP_AP2CNN_HOST_SEL		62
 #define CLK_TOP_NR_CLK			63
 
-/*
- * INFRACFG_AO
- * clock muxes need to be append to infracfg domain, and clock gates
- * need to be keep in infracgh_ao domain
- */
+/* INFRACFG */
 
-#define CK_INFRA_UART0_SEL		(0 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART1_SEL		(1 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART2_SEL		(2 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI0_SEL		(3 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI1_SEL		(4 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM1_SEL		(5 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM2_SEL		(6 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM_BSEL		(7 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PCIE_SEL		(8 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_GPT_STA		0
-#define CK_INFRA_PWM_HCK		1
-#define CK_INFRA_PWM_STA		2
-#define CK_INFRA_PWM1_CK		3
-#define CK_INFRA_PWM2_CK		4
-#define CK_INFRA_CQ_DMA_CK		5
-#define CK_INFRA_EIP97_CK		6
-#define CK_INFRA_AUD_BUS_CK		7
-#define CK_INFRA_AUD_26M_CK		8
-#define CK_INFRA_AUD_L_CK		9
-#define CK_INFRA_AUD_AUD_CK		10
-#define CK_INFRA_AUD_EG2_CK		11
-#define CK_INFRA_DRAMC_26M_CK		12
-#define CK_INFRA_DBG_CK			13
-#define CK_INFRA_AP_DMA_CK		14
-#define CK_INFRA_SEJ_CK			15
-#define CK_INFRA_SEJ_13M_CK		16
-#define CK_INFRA_THERM_CK		17
-#define CK_INFRA_I2C0_CK		18
-#define CK_INFRA_UART0_CK		19
-#define CK_INFRA_UART1_CK		20
-#define CK_INFRA_UART2_CK		21
-#define CK_INFRA_NFI1_CK		22
-#define CK_INFRA_SPINFI1_CK		23
-#define CK_INFRA_NFI_HCK_CK		24
-#define CK_INFRA_SPI0_CK		25
-#define CK_INFRA_SPI1_CK		26
-#define CK_INFRA_SPI0_HCK_CK		27
-#define CK_INFRA_SPI1_HCK_CK		28
-#define CK_INFRA_FRTC_CK		29
-#define CK_INFRA_MSDC_CK		30
-#define CK_INFRA_MSDC_HCK_CK		31
-#define CK_INFRA_MSDC_133M_CK		32
-#define CK_INFRA_MSDC_66M_CK		33
-#define CK_INFRA_ADC_26M_CK		34
-#define CK_INFRA_ADC_FRC_CK		35
-#define CK_INFRA_FBIST2FPC_CK		36
-#define CK_INFRA_IUSB_133_CK		37
-#define CK_INFRA_IUSB_66M_CK		38
-#define CK_INFRA_IUSB_SYS_CK		39
-#define CK_INFRA_IUSB_CK		40
-#define CK_INFRA_IPCIE_CK		41
-#define CK_INFRA_IPCIE_PIPE_CK		42
-#define CK_INFRA_IPCIER_CK		43
-#define CK_INFRA_IPCIEB_CK		44
-#define CK_INFRA_TRNG_CK		45
-#define CLK_INFRA_AO_NR_CLK		46
+#define CK_INFRA_SYSAXI_D2		0
+#define CK_INFRA_UART0_SEL		1
+#define CK_INFRA_UART1_SEL		2
+#define CK_INFRA_UART2_SEL		3
+#define CK_INFRA_SPI0_SEL		4
+#define CK_INFRA_SPI1_SEL		5
+#define CK_INFRA_PWM1_SEL		6
+#define CK_INFRA_PWM2_SEL		7
+#define CK_INFRA_PWM_BSEL		8
+#define CK_INFRA_PCIE_SEL		9
+#define CK_INFRA_GPT_STA		10
+#define CK_INFRA_PWM_HCK		11
+#define CK_INFRA_PWM_STA		12
+#define CK_INFRA_PWM1_CK		13
+#define CK_INFRA_PWM2_CK		14
+#define CK_INFRA_CQ_DMA_CK		15
+#define CK_INFRA_EIP97_CK		16
+#define CK_INFRA_AUD_BUS_CK		17
+#define CK_INFRA_AUD_26M_CK		18
+#define CK_INFRA_AUD_L_CK		19
+#define CK_INFRA_AUD_AUD_CK		20
+#define CK_INFRA_AUD_EG2_CK		21
+#define CK_INFRA_DRAMC_26M_CK		22
+#define CK_INFRA_DBG_CK		23
+#define CK_INFRA_AP_DMA_CK		24
+#define CK_INFRA_SEJ_CK		25
+#define CK_INFRA_SEJ_13M_CK		26
+#define CK_INFRA_THERM_CK		27
+#define CK_INFRA_I2C0_CK		28
+#define CK_INFRA_UART0_CK		29
+#define CK_INFRA_UART1_CK		30
+#define CK_INFRA_UART2_CK		31
+#define CK_INFRA_NFI1_CK		32
+#define CK_INFRA_SPINFI1_CK		33
+#define CK_INFRA_NFI_HCK_CK		34
+#define CK_INFRA_SPI0_CK		35
+#define CK_INFRA_SPI1_CK		36
+#define CK_INFRA_SPI0_HCK_CK		37
+#define CK_INFRA_SPI1_HCK_CK		38
+#define CK_INFRA_FRTC_CK		39
+#define CK_INFRA_MSDC_CK		40
+#define CK_INFRA_MSDC_HCK_CK		41
+#define CK_INFRA_MSDC_133M_CK		42
+#define CK_INFRA_MSDC_66M_CK		43
+#define CK_INFRA_ADC_26M_CK		44
+#define CK_INFRA_ADC_FRC_CK		45
+#define CK_INFRA_FBIST2FPC_CK		46
+#define CK_INFRA_IUSB_133_CK		47
+#define CK_INFRA_IUSB_66M_CK		48
+#define CK_INFRA_IUSB_SYS_CK		49
+#define CK_INFRA_IUSB_CK		50
+#define CK_INFRA_IPCIE_CK		51
+#define CK_INFRA_IPCIE_PIPE_CK		52
+#define CK_INFRA_IPCIER_CK		53
+#define CK_INFRA_IPCIEB_CK		54
+#define CK_INFRA_TRNG_CK		55
+#define CK_INFRA_AO_NR_CLK		46
 
 /* APMIXEDSYS */
 
-- 
2.45.2

[PATCH 14/15] clk: mediatek: mt7986: convert to unified infracfg gates + muxes

[Christian Marangi]

Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm/dts/mt7986.dtsi          | 31 ++++++++++++-------------------
 drivers/clk/mediatek/clk-mt7986.c | 26 +++-----------------------
 2 files changed, 15 insertions(+), 42 deletions(-)

diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index 187e1298fae..a44f5386390 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -115,13 +115,6 @@
 		#clock-cells = <1>;
 	};
 
-	infracfg_ao: infracfg_ao@10001000 {
-		compatible = "mediatek,mt7986-infracfg_ao";
-		reg = <0x10001000 0x68>;
-		clock-parent = <&infracfg>;
-		#clock-cells = <1>;
-	};
-
 	infracfg: infracfg@10001040 {
 		compatible = "mediatek,mt7986-infracfg";
 		reg = <0x10001000 0x1000>;
@@ -155,9 +148,9 @@
 		#pwm-cells = <2>;
 		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&topckgen CK_TOP_PWM_SEL>,
-			 <&infracfg_ao CK_INFRA_PWM_BSEL>,
-			 <&infracfg_ao CK_INFRA_PWM1_CK>,
-			 <&infracfg_ao CK_INFRA_PWM2_CK>;
+			 <&infracfg CK_INFRA_PWM_BSEL>,
+			 <&infracfg CK_INFRA_PWM1_CK>,
+			 <&infracfg CK_INFRA_PWM2_CK>;
 		assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
 				  <&infracfg CK_INFRA_PWM_BSEL>,
 				  <&infracfg CK_INFRA_PWM1_SEL>,
@@ -175,9 +168,9 @@
 		compatible = "mediatek,hsuart";
 		reg = <0x11002000 0x400>;
 		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
+		clocks = <&infracfg CK_INFRA_UART0_CK>;
 		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-				  <&infracfg_ao CK_INFRA_UART0_SEL>;
+				  <&infracfg CK_INFRA_UART0_SEL>;
 		assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
 					 <&topckgen CK_TOP_UART_SEL>;
 		mediatek,force-highspeed;
@@ -189,7 +182,7 @@
 		compatible = "mediatek,hsuart";
 		reg = <0x11003000 0x400>;
 		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
+		clocks = <&infracfg CK_INFRA_UART1_CK>;
 		assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
 		assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
 		mediatek,force-highspeed;
@@ -200,7 +193,7 @@
 		compatible = "mediatek,hsuart";
 		reg = <0x11004000 0x400>;
 		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
+		clocks = <&infracfg CK_INFRA_UART2_CK>;
 		assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
 		assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
 		mediatek,force-highspeed;
@@ -212,9 +205,9 @@
 		reg = <0x11005000 0x1000>,
 		      <0x11006000 0x1000>;
 		reg-names = "nfi", "ecc";
-		clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
-			 <&infracfg_ao CK_INFRA_NFI1_CK>,
-			 <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
+		clocks = <&infracfg CK_INFRA_SPINFI1_CK>,
+			 <&infracfg CK_INFRA_NFI1_CK>,
+			 <&infracfg CK_INFRA_NFI_HCK_CK>;
 		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
 		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
 				  <&topckgen CK_TOP_NFI1X_SEL>;
@@ -258,7 +251,7 @@
 	spi0: spi@1100a000 {
 		compatible = "mediatek,ipm-spi";
 		reg = <0x1100a000 0x100>;
-		clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
+		clocks = <&infracfg CK_INFRA_SPI0_CK>,
 			 <&topckgen CK_TOP_SPI_SEL>;
 		assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
 				  <&infracfg CK_INFRA_SPI0_SEL>;
@@ -283,7 +276,7 @@
 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
 			<&topckgen CK_TOP_EMMC_250M_SEL>,
-			<&infracfg_ao CK_INFRA_MSDC_CK>;
+			<&infracfg CK_INFRA_MSDC_CK>;
 		assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
 				  <&topckgen CK_TOP_EMMC_250M_SEL>;
 		assigned-clock-parents = <&fixed_plls CK_APMIXED_MPLL>,
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 59b82ca7de1..b163ffc9f1a 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -448,7 +448,7 @@ static const struct mtk_gate_regs infra_2_cg_regs = {
 
 /* INFRA GATE */
 
-static const struct mtk_gate infracfg_ao_gates[] = {
+static const struct mtk_gate infracfg_gates[] = {
 	/* INFRA0 */
 	GATE_INFRA0_INFRA(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_SYSAXI_D2, 0),
 	GATE_INFRA0_INFRA(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_SYSAXI_D2, 1),
@@ -536,6 +536,7 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
 	.gates_offs = CK_INFRA_GPT_STA,
 	.fdivs = infra_fixed_divs,
 	.muxes = infra_muxes,
+	.gates = infracfg_gates,
 	.flags = CLK_INFRASYS,
 };
 
@@ -590,20 +591,9 @@ static const struct udevice_id mt7986_infracfg_compat[] = {
 	{}
 };
 
-static const struct udevice_id mt7986_infracfg_ao_compat[] = {
-	{ .compatible = "mediatek,mt7986-infracfg_ao" },
-	{}
-};
-
 static int mt7986_infracfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree);
-}
-
-static int mt7986_infracfg_ao_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree,
-					infracfg_ao_gates);
+	return mtk_common_clk_infrasys_init(dev, &mt7986_infracfg_clk_tree);
 }
 
 U_BOOT_DRIVER(mtk_clk_infracfg) = {
@@ -616,16 +606,6 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
-	.name = "mt7986-clock-infracfg-ao",
-	.id = UCLASS_CLK,
-	.of_match = mt7986_infracfg_ao_compat,
-	.probe = mt7986_infracfg_ao_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-	.flags = DM_FLAG_PRE_RELOC,
-};
-
 /* ethsys */
 static const struct mtk_gate_regs eth_cg_regs = {
 	.sta_ofs = 0x30,
-- 
2.45.2

[PATCH 15/15] clk: mediatek: mt7986: rename CK to CLK

[Christian Marangi]

Rename each entry from CK to CLK to match the include in upstream kernel
linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm/dts/mt7986.dtsi               |  88 +++---
 drivers/clk/mediatek/clk-mt7986.c      | 404 ++++++++++++-------------
 include/dt-bindings/clock/mt7986-clk.h | 284 ++++++++---------
 3 files changed, 388 insertions(+), 388 deletions(-)

diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index a44f5386390..f871f2394c5 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -78,7 +78,7 @@
 		compatible = "mediatek,mt7986-timer";
 		reg = <0x10008000 0x1000>;
 		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CK_TOP_F26M_SEL>;
+		clocks = <&topckgen CLK_TOP_F26M_SEL>;
 		clock-names = "gpt-clk";
 		bootph-all;
 	};
@@ -147,18 +147,18 @@
 		#clock-cells = <1>;
 		#pwm-cells = <2>;
 		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CK_TOP_PWM_SEL>,
-			 <&infracfg CK_INFRA_PWM_BSEL>,
-			 <&infracfg CK_INFRA_PWM1_CK>,
-			 <&infracfg CK_INFRA_PWM2_CK>;
-		assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
-				  <&infracfg CK_INFRA_PWM_BSEL>,
-				  <&infracfg CK_INFRA_PWM1_SEL>,
-				  <&infracfg CK_INFRA_PWM2_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_MPLL_D4>,
-					 <&topckgen CK_TOP_PWM_SEL>,
-					 <&topckgen CK_TOP_PWM_SEL>,
-					 <&topckgen CK_TOP_PWM_SEL>;
+		clocks = <&topckgen CLK_TOP_PWM_SEL>,
+			 <&infracfg CLK_INFRA_PWM_BSEL>,
+			 <&infracfg CLK_INFRA_PWM1_CK>,
+			 <&infracfg CLK_INFRA_PWM2_CK>;
+		assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
+				  <&infracfg CLK_INFRA_PWM_BSEL>,
+				  <&infracfg CLK_INFRA_PWM1_SEL>,
+				  <&infracfg CLK_INFRA_PWM2_SEL>;
+		assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D4>,
+					 <&topckgen CLK_TOP_PWM_SEL>,
+					 <&topckgen CLK_TOP_PWM_SEL>,
+					 <&topckgen CLK_TOP_PWM_SEL>;
 		clock-names = "top", "main", "pwm1", "pwm2";
 		status = "disabled";
 		bootph-all;
@@ -168,11 +168,11 @@
 		compatible = "mediatek,hsuart";
 		reg = <0x11002000 0x400>;
 		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CK_INFRA_UART0_CK>;
-		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-				  <&infracfg CK_INFRA_UART0_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
-					 <&topckgen CK_TOP_UART_SEL>;
+		clocks = <&infracfg CLK_INFRA_UART0_CK>;
+		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+				  <&infracfg CLK_INFRA_UART0_SEL>;
+		assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+					 <&topckgen CLK_TOP_UART_SEL>;
 		mediatek,force-highspeed;
 		status = "disabled";
 		bootph-all;
@@ -182,9 +182,9 @@
 		compatible = "mediatek,hsuart";
 		reg = <0x11003000 0x400>;
 		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CK_INFRA_UART1_CK>;
-		assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
+		clocks = <&infracfg CLK_INFRA_UART1_CK>;
+		assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
+		assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
 		mediatek,force-highspeed;
 		status = "disabled";
 	};
@@ -193,9 +193,9 @@
 		compatible = "mediatek,hsuart";
 		reg = <0x11004000 0x400>;
 		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CK_INFRA_UART2_CK>;
-		assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
+		clocks = <&infracfg CLK_INFRA_UART2_CK>;
+		assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
+		assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
 		mediatek,force-highspeed;
 		status = "disabled";
 	};
@@ -205,14 +205,14 @@
 		reg = <0x11005000 0x1000>,
 		      <0x11006000 0x1000>;
 		reg-names = "nfi", "ecc";
-		clocks = <&infracfg CK_INFRA_SPINFI1_CK>,
-			 <&infracfg CK_INFRA_NFI1_CK>,
-			 <&infracfg CK_INFRA_NFI_HCK_CK>;
+		clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
+			 <&infracfg CLK_INFRA_NFI1_CK>,
+			 <&infracfg CLK_INFRA_NFI_HCK_CK>;
 		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
-				  <&topckgen CK_TOP_NFI1X_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_MPLL_D8>,
-					 <&topckgen CK_TOP_MPLL_D8>;
+		assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+				  <&topckgen CLK_TOP_NFI1X_SEL>;
+		assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
+					 <&topckgen CLK_TOP_MPLL_D8>;
 		status = "disabled";
 	};
 
@@ -251,12 +251,12 @@
 	spi0: spi@1100a000 {
 		compatible = "mediatek,ipm-spi";
 		reg = <0x1100a000 0x100>;
-		clocks = <&infracfg CK_INFRA_SPI0_CK>,
-			 <&topckgen CK_TOP_SPI_SEL>;
-		assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
-				  <&infracfg CK_INFRA_SPI0_SEL>;
-		assigned-clock-parents = <&topckgen CK_TOP_MPLL_D2>,
-					 <&topckgen CK_TOP_SPI_SEL>;
+		clocks = <&infracfg CLK_INFRA_SPI0_CK>,
+			 <&topckgen CLK_TOP_SPI_SEL>;
+		assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+				  <&infracfg CLK_INFRA_SPI0_SEL>;
+		assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D2>,
+					 <&topckgen CLK_TOP_SPI_SEL>;
 		clock-names = "sel-clk", "spi-clk";
 		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
@@ -274,13 +274,13 @@
 		reg = <0x11230000 0x1000>,
 		      <0x11C20000 0x1000>;
 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
-			<&topckgen CK_TOP_EMMC_250M_SEL>,
-			<&infracfg CK_INFRA_MSDC_CK>;
-		assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
-				  <&topckgen CK_TOP_EMMC_250M_SEL>;
-		assigned-clock-parents = <&fixed_plls CK_APMIXED_MPLL>,
-					 <&topckgen CK_TOP_NET1PLL_D5_D2>;
+		clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
+			<&topckgen CLK_TOP_EMMC_250M_SEL>,
+			<&infracfg CLK_INFRA_MSDC_CK>;
+		assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
+				  <&topckgen CLK_TOP_EMMC_250M_SEL>;
+		assigned-clock-parents = <&fixed_plls CLK_APMIXED_MPLL>,
+					 <&topckgen CLK_TOP_NET1PLL_D5_D2>;
 		clock-names = "source", "hclk", "source_cg";
 		status = "disabled";
 	};
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index b163ffc9f1a..c5cc77243d0 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -34,194 +34,194 @@
 
 /* FIXED PLLS */
 static const struct mtk_fixed_clk fixed_pll_clks[] = {
-	FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
-	FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
-	FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
-	FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
-	FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
-	FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
-	FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
-	FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
+	FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
+	FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+	FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
+	FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+	FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
+	FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+	FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
+	FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
 };
 
 /* TOPCKGEN FIXED CLK */
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CK_TOP_XTAL, CLK_XTAL, 40000000),
+	FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),
 };
 
 /* TOPCKGEN FIXED DIV */
 static const struct mtk_fixed_factor top_fixed_divs[] = {
 	/* TOP Factors */
-	TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL,
+	TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL,
 		   1, 2),
-	TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
+	TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1,
 		   1250),
-	TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
+	TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1,
 		   1220),
 	/* Not defined upstream and not used */
-	/* TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1), */
+	/* TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 2, 1), */
 	/* MPLL */
-	PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
-	PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
-	PLL_FACTOR(CK_TOP_MPLL_D8, "mpll_d8", CK_APMIXED_MPLL, 1, 8),
-	PLL_FACTOR(CK_TOP_MPLL_D8_D2, "mpll_d8_d2", CK_APMIXED_MPLL, 1, 16),
-	PLL_FACTOR(CK_TOP_MPLL_D3_D2, "mpll_d3_d2", CK_APMIXED_MPLL, 1, 2),
+	PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2),
+	PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4),
+	PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8),
+	PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16),
+	PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2),
 	/* MMPLL */
-	PLL_FACTOR(CK_TOP_MMPLL_D2, "mmpll_d2", CK_APMIXED_MMPLL, 1, 2),
-	PLL_FACTOR(CK_TOP_MMPLL_D4, "mmpll_d4", CK_APMIXED_MMPLL, 1, 4),
-	PLL_FACTOR(CK_TOP_MMPLL_D8, "mmpll_d8", CK_APMIXED_MMPLL, 1, 8),
-	PLL_FACTOR(CK_TOP_MMPLL_D8_D2, "mmpll_d8_d2", CK_APMIXED_MMPLL, 1, 16),
-	PLL_FACTOR(CK_TOP_MMPLL_D3_D8, "mmpll_d3_d8", CK_APMIXED_MMPLL, 1, 8),
-	PLL_FACTOR(CK_TOP_MMPLL_U2PHYD, "mmpll_u2phy", CK_APMIXED_MMPLL, 1, 30),
+	PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
+	PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4),
+	PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8),
+	PLL_FACTOR(CLK_TOP_MMPLL_D8_D2, "mmpll_d8_d2", CLK_APMIXED_MMPLL, 1, 16),
+	PLL_FACTOR(CLK_TOP_MMPLL_D3_D8, "mmpll_d3_d8", CLK_APMIXED_MMPLL, 1, 8),
+	PLL_FACTOR(CLK_TOP_MMPLL_U2PHYD, "mmpll_u2phy", CLK_APMIXED_MMPLL, 1, 30),
 	/* APLL2 */
-	PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
+	PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
 	/* NET1PLL */
-	PLL_FACTOR(CK_TOP_NET1PLL_D4, "net1pll_d4", CK_APMIXED_NET1PLL, 1, 4),
-	PLL_FACTOR(CK_TOP_NET1PLL_D5, "net1pll_d5", CK_APMIXED_NET1PLL, 1, 5),
-	PLL_FACTOR(CK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
-	PLL_FACTOR(CK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
-	PLL_FACTOR(CK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
-	PLL_FACTOR(CK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
+	PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4),
+	PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5),
+	PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
+	PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
+	PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
+	PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
 	/* NET2PLL */
-	PLL_FACTOR(CK_TOP_NET2PLL_D4, "net2pll_d4", CK_APMIXED_NET2PLL, 1, 4),
-	PLL_FACTOR(CK_TOP_NET2PLL_D4_D2, "net2pll_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
-	PLL_FACTOR(CK_TOP_NET2PLL_D3_D2, "net2pll_d3_d2", CK_APMIXED_NET2PLL, 1, 2),
+	PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4),
+	PLL_FACTOR(CLK_TOP_NET2PLL_D4_D2, "net2pll_d4_d2", CLK_APMIXED_NET2PLL, 1, 8),
+	PLL_FACTOR(CLK_TOP_NET2PLL_D3_D2, "net2pll_d3_d2", CLK_APMIXED_NET2PLL, 1, 2),
 	/* WEDMCUPLL */
-	PLL_FACTOR(CK_TOP_WEDMCUPLL_D5_D2, "wedmcupll_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
+	PLL_FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "wedmcupll_d5_d2", CLK_APMIXED_WEDMCUPLL, 1,
 		   10),
 };
 
 /* TOPCKGEN MUX PARENTS */
 static const struct mtk_parent nfi1x_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D8),
-	TOP_PARENT(CK_TOP_NET1PLL_D8_D2), TOP_PARENT(CK_TOP_NET2PLL_D3_D2),
-	TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_MMPLL_D8_D2),
-	TOP_PARENT(CK_TOP_WEDMCUPLL_D5_D2), TOP_PARENT(CK_TOP_MPLL_D8),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D8),
+	TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2),
+	TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8_D2),
+	TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2), TOP_PARENT(CLK_TOP_MPLL_D8),
 };
 
 static const struct mtk_parent spinfi_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_XTAL),
-	TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
-	TOP_PARENT(CK_TOP_MMPLL_D8_D2), TOP_PARENT(CK_TOP_WEDMCUPLL_D5_D2),
-	TOP_PARENT(CK_TOP_MMPLL_D3_D8), TOP_PARENT(CK_TOP_MPLL_D8),
+	TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL),
+	TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+	TOP_PARENT(CLK_TOP_MMPLL_D8_D2), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D3_D8), TOP_PARENT(CLK_TOP_MPLL_D8),
 };
 
 static const struct mtk_parent spi_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
-	TOP_PARENT(CK_TOP_MMPLL_D8), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
-	TOP_PARENT(CK_TOP_NET2PLL_D3_D2), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
-	TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_WEDMCUPLL_D5_D2),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+	TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+	TOP_PARENT(CLK_TOP_NET2PLL_D3_D2), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+	TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2),
 };
 
 static const struct mtk_parent uart_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D8),
-	TOP_PARENT(CK_TOP_MPLL_D8_D2),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8),
+	TOP_PARENT(CLK_TOP_MPLL_D8_D2),
 };
 
 static const struct mtk_parent pwm_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
-	TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+	TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
 };
 
 static const struct mtk_parent i2c_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
-	TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+	TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
 };
 
 static const struct mtk_parent pextp_tl_ck_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
-	TOP_PARENT(CK_TOP_NET2PLL_D4_D2), TOP_PARENT(CK_TOP_RTC_32K),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+	TOP_PARENT(CLK_TOP_NET2PLL_D4_D2), TOP_PARENT(CLK_TOP_RTC_32K),
 };
 
 static const struct mtk_parent emmc_250m_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
 };
 
 static const struct mtk_parent emmc_416m_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_MPLL),
+	TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MPLL),
 };
 
 static const struct mtk_parent f_26m_adc_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D8_D2),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
 };
 
 static const struct mtk_parent dramc_md32_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
 };
 
 static const struct mtk_parent sysaxi_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
-	TOP_PARENT(CK_TOP_NET2PLL_D4),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+	TOP_PARENT(CLK_TOP_NET2PLL_D4),
 };
 
 static const struct mtk_parent sysapb_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D3_D2),
-	TOP_PARENT(CK_TOP_NET2PLL_D4_D2),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2),
+	TOP_PARENT(CLK_TOP_NET2PLL_D4_D2),
 };
 
 static const struct mtk_parent arm_db_main_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D3_D2),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2),
 };
 
 static const struct mtk_parent arm_db_jtsel_parents[] = {
-	VOID_PARENT, TOP_PARENT(CK_TOP_XTAL),
+	VOID_PARENT, TOP_PARENT(CLK_TOP_XTAL),
 };
 
 static const struct mtk_parent netsys_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D4),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4),
 };
 
 static const struct mtk_parent netsys_500m_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
 };
 
 static const struct mtk_parent netsys_mcu_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_WEDMCUPLL),
-	TOP_PARENT(CK_TOP_MMPLL_D2), TOP_PARENT(CK_TOP_NET1PLL_D4),
-	TOP_PARENT(CK_TOP_NET1PLL_D5),
+	TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL),
+	TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+	TOP_PARENT(CLK_TOP_NET1PLL_D5),
 };
 
 static const struct mtk_parent netsys_2x_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_APMIXED_NET2PLL),
-	APMIXED_PARENT(CK_APMIXED_WEDMCUPLL), TOP_PARENT(CK_TOP_MMPLL_D2),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_APMIXED_NET2PLL),
+	APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL), TOP_PARENT(CLK_TOP_MMPLL_D2),
 };
 
 static const struct mtk_parent sgm_325m_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_SGMPLL),
+	TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
 };
 
 static const struct mtk_parent sgm_reg_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
 };
 
 static const struct mtk_parent a1sys_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_APLL2_D4),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
 };
 
 static const struct mtk_parent conn_mcusys_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D2),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D2),
 };
 
 static const struct mtk_parent eip_b_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
+	TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
 };
 
 static const struct mtk_parent aud_l_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_APLL2),
-	TOP_PARENT(CK_TOP_MPLL_D8_D2),
+	TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
+	TOP_PARENT(CLK_TOP_MPLL_D8_D2),
 };
 
 static const struct mtk_parent a_tuner_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_APLL2_D4),
-	TOP_PARENT(CK_TOP_MPLL_D8_D2),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
+	TOP_PARENT(CLK_TOP_MPLL_D8_D2),
 };
 
 static const struct mtk_parent u2u3_sys_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
 };
 
 static const struct mtk_parent da_u2_refsel_parents[] = {
-	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_U2PHYD),
+	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_U2PHYD),
 };
 
 #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,    \
@@ -239,126 +239,126 @@ static const struct mtk_parent da_u2_refsel_parents[] = {
 /* TOPCKGEN MUX_GATE */
 static const struct mtk_composite top_muxes[] = {
 	/* CLK_CFG_0 */
-	TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
+	TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
 		0x008, 0, 3, 7, 0x1C0, 0),
-	TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
+	TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
 		0x008, 8, 3, 15, 0x1C0, 1),
-	TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
+	TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
 		3, 23, 0x1C0, 2),
-	TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
+	TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
 		0x008, 24, 3, 31, 0x1C0, 3),
 	/* CLK_CFG_1 */
-	TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
+	TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
 		0, 2, 7, 0x1C0, 4),
-	TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
+	TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
 		2, 15, 0x1C0, 5),
-	TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
+	TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
 		2, 23, 0x1C0, 6),
-	TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+	TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
 		0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7),
 	/* CLK_CFG_2 */
-	TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
+	TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
 		0x024, 0x028, 0, 1, 7, 0x1C0, 8),
-	TOP_MUX(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
+	TOP_MUX(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
 		0x024, 0x028, 8, 1, 15, 0x1C0, 9),
-	TOP_MUX(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
+	TOP_MUX(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
 		0x024, 0x028, 16, 1, 23, 0x1C0, 10),
-	TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
+	TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
 		0x028, 24, 1, 31, 0x1C0, 11),
 	/* CLK_CFG_3 */
-	TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+	TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
 		0x030, 0x034, 0x038, 0, 1, 7, 0x1C0, 12),
-	TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
+	TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
 		0x038, 8, 2, 15, 0x1C0, 13),
-	TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
+	TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
 		0x038, 16, 2, 23, 0x1C0, 14),
-	TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
+	TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
 		0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15),
 	/* CLK_CFG_4 */
-	TOP_MUX(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
+	TOP_MUX(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
 		0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16),
-	TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
+	TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
 		0x048, 8, 1, 15, 0x1C0, 17),
-	TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+	TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
 		0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
-	TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+	TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
 		0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
 	/* CLK_CFG_5 */
-	TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
+	TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
 		0x054, 0x058, 0, 2, 7, 0x1C0, 20),
-	TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
+	TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
 		0x054, 0x058, 8, 1, 15, 0x1C0, 21),
-	TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
+	TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
 		0x054, 0x058, 16, 1, 23, 0x1C0, 22),
-	TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
+	TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
 		0x058, 24, 1, 31, 0x1C0, 23),
 	/* CLK_CFG_6 */
-	TOP_MUX(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
+	TOP_MUX(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
 		0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
-	TOP_MUX(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
+	TOP_MUX(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
 		0x068, 8, 1, 15, 0x1C0, 25),
-	TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
+	TOP_MUX(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
 		0x064, 0x068, 16, 1, 23, 0x1C0, 26),
-	TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
+	TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
 		0x064, 0x068, 24, 1, 31, 0x1C0, 27),
 	/* CLK_CFG_7 */
-	TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
+	TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
 		0x074, 0x078, 0, 1, 7, 0x1C0, 28),
-	TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
+	TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
 		0x078, 8, 2, 15, 0x1C0, 29),
-	TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
+	TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
 		0x074, 0x078, 16, 2, 23, 0x1C0, 30),
-	TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
+	TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
 		0x078, 24, 1, 31, 0x1C4, 0),
 	/* CLK_CFG_8 */
-	TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
+	TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
 		0x084, 0x088, 0, 1, 7, 0x1C4, 1),
-	TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
+	TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
 		0x084, 0x088, 8, 1, 15, 0x1C4, 2),
-	TOP_MUX(CK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
+	TOP_MUX(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
 		0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3),
-	TOP_MUX(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
+	TOP_MUX(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
 		0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
 	/* CLK_CFG_9 */
-	TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
+	TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
 		0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
 };
 
 /* INFRA FIXED DIV */
 static const struct mtk_fixed_factor infra_fixed_divs[] = {
-	TOP_FACTOR(CK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", CK_TOP_SYSAXI_SEL, 1, 2),
+	TOP_FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", CLK_TOP_SYSAXI_SEL, 1, 2),
 };
 
 /* INFRASYS MUX PARENTS */
 
 
 static const struct mtk_parent infra_uart0_parents[] = {
-	TOP_PARENT(CK_TOP_F26M_SEL),
-	TOP_PARENT(CK_TOP_UART_SEL)
+	TOP_PARENT(CLK_TOP_F26M_SEL),
+	TOP_PARENT(CLK_TOP_UART_SEL)
 };
 
 static const struct mtk_parent infra_spi0_parents[] = {
-	TOP_PARENT(CK_TOP_I2C_SEL),
-	TOP_PARENT(CK_TOP_SPI_SEL)
+	TOP_PARENT(CLK_TOP_I2C_SEL),
+	TOP_PARENT(CLK_TOP_SPI_SEL)
 };
 
 static const struct mtk_parent infra_spi1_parents[] = {
-	TOP_PARENT(CK_TOP_I2C_SEL),
-	TOP_PARENT(CK_TOP_SPINFI_SEL)
+	TOP_PARENT(CLK_TOP_I2C_SEL),
+	TOP_PARENT(CLK_TOP_SPINFI_SEL)
 };
 
 static const struct mtk_parent infra_pwm_bsel_parents[] = {
-	TOP_PARENT(CK_TOP_RTC_32P7K),
-	TOP_PARENT(CK_TOP_F26M_SEL),
-	INFRA_PARENT(CK_INFRA_SYSAXI_D2),
-	TOP_PARENT(CK_TOP_PWM_SEL)
+	TOP_PARENT(CLK_TOP_RTC_32P7K),
+	TOP_PARENT(CLK_TOP_F26M_SEL),
+	INFRA_PARENT(CLK_INFRA_SYSAXI_D2),
+	TOP_PARENT(CLK_TOP_PWM_SEL)
 };
 
 static const struct mtk_parent infra_pcie_parents[] = {
-	TOP_PARENT(CK_TOP_RTC_32P7K),
-	TOP_PARENT(CK_TOP_F26M_SEL),
-	TOP_PARENT(CK_TOP_XTAL),
-	TOP_PARENT(CK_TOP_PEXTP_TL_SEL)
+	TOP_PARENT(CLK_TOP_RTC_32P7K),
+	TOP_PARENT(CLK_TOP_F26M_SEL),
+	TOP_PARENT(CLK_TOP_XTAL),
+	TOP_PARENT(CLK_TOP_PEXTP_TL_SEL)
 };
 
 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width)                  \
@@ -374,24 +374,24 @@ static const struct mtk_parent infra_pcie_parents[] = {
 
 static const struct mtk_composite infra_muxes[] = {
 	/* MODULE_CLK_SEL_0 */
-	INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
+	INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
 		  0x10, 0, 1),
-	INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
+	INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
 		  0x10, 1, 1),
-	INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
+	INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
 		  0x10, 2, 1),
-	INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
+	INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
 		  4, 1),
-	INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
+	INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
 		  5, 1),
-	INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
+	INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
 		  0x10, 9, 2),
-	INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
+	INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
 		  0x10, 11, 2),
-	INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
+	INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
 		  0x10, 13, 2),
 	/* MODULE_CLK_SEL_1 */
-	INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
+	INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
 		  0, 2),
 };
 
@@ -450,68 +450,68 @@ static const struct mtk_gate_regs infra_2_cg_regs = {
 
 static const struct mtk_gate infracfg_gates[] = {
 	/* INFRA0 */
-	GATE_INFRA0_INFRA(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_SYSAXI_D2, 0),
-	GATE_INFRA0_INFRA(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_SYSAXI_D2, 1),
-	GATE_INFRA0_INFRA(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BSEL, 2),
-	GATE_INFRA0_INFRA(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM1_SEL, 3),
-	GATE_INFRA0_INFRA(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM2_SEL, 4),
-	GATE_INFRA0_TOP(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_TOP_SYSAXI_SEL, 6),
-	GATE_INFRA0_TOP(CK_INFRA_EIP97_CK, "infra_eip97", CK_TOP_EIP_B_SEL, 7),
-	GATE_INFRA0_TOP(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_TOP_SYSAXI_SEL, 8),
-	GATE_INFRA0_TOP(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_TOP_F26M_SEL, 9),
-	GATE_INFRA0_TOP(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_TOP_AUD_L_SEL, 10),
-	GATE_INFRA0_TOP(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_TOP_A1SYS_SEL,
+	GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_SYSAXI_D2, 0),
+	GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_SYSAXI_D2, 1),
+	GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2),
+	GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3),
+	GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4),
+	GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI_SEL, 6),
+	GATE_INFRA0_TOP(CLK_INFRA_EIP97_CK, "infra_eip97", CLK_TOP_EIP_B_SEL, 7),
+	GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI_SEL, 8),
+	GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9),
+	GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L_SEL, 10),
+	GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS_SEL,
 			11),
-	GATE_INFRA0_TOP(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_TOP_A_TUNER_SEL,
+	GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER_SEL,
 			13),
-	GATE_INFRA0_TOP(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_TOP_F26M_SEL,
+	GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL,
 			14),
-	GATE_INFRA0_INFRA(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_SYSAXI_D2, 15),
-	GATE_INFRA0_INFRA(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_SYSAXI_D2, 16),
-	GATE_INFRA0_INFRA(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_SYSAXI_D2, 24),
-	GATE_INFRA0_TOP(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_TOP_F26M_SEL, 25),
+	GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_SYSAXI_D2, 15),
+	GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_SYSAXI_D2, 16),
+	GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_SYSAXI_D2, 24),
+	GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25),
 	/* INFRA1 */
-	GATE_INFRA1_TOP(CK_INFRA_THERM_CK, "infra_therm", CK_TOP_F26M_SEL, 0),
-	GATE_INFRA1_TOP(CK_INFRA_I2C0_CK, "infra_i2co", CK_TOP_I2C_SEL, 1),
-	GATE_INFRA1_INFRA(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_UART0_SEL, 2),
-	GATE_INFRA1_INFRA(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_UART1_SEL, 3),
-	GATE_INFRA1_INFRA(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_UART2_SEL, 4),
-	GATE_INFRA1_TOP(CK_INFRA_NFI1_CK, "infra_nfi1", CK_TOP_NFI1X_SEL, 8),
-	GATE_INFRA1_TOP(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_TOP_SPINFI_SEL,
+	GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0),
+	GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2co", CLK_TOP_I2C_SEL, 1),
+	GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2),
+	GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3),
+	GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4),
+	GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X_SEL, 8),
+	GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_SEL,
 			9),
-	GATE_INFRA1_INFRA(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_SYSAXI_D2, 10),
-	GATE_INFRA1_INFRA(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_SPI0_SEL, 11),
-	GATE_INFRA1_INFRA(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_SPI1_SEL, 12),
-	GATE_INFRA1_INFRA(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_SYSAXI_D2,
+	GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_SYSAXI_D2, 10),
+	GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11),
+	GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12),
+	GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_SYSAXI_D2,
 			  13),
-	GATE_INFRA1_INFRA(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_SYSAXI_D2,
+	GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_SYSAXI_D2,
 			  14),
-	GATE_INFRA1_TOP(CK_INFRA_FRTC_CK, "infra_frtc", CK_TOP_RTC_32K, 15),
-	GATE_INFRA1_TOP(CK_INFRA_MSDC_CK, "infra_msdc", CK_TOP_EMMC_416M_SEL, 16),
-	GATE_INFRA1_TOP(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
-			CK_TOP_EMMC_250M_SEL, 17),
-	GATE_INFRA1_TOP(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
-			CK_TOP_SYSAXI_SEL, 18),
-	GATE_INFRA1_INFRA(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_SYSAXI_D2,
+	GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_RTC_32K, 15),
+	GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_416M_SEL, 16),
+	GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
+			CLK_TOP_EMMC_250M_SEL, 17),
+	GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
+			CLK_TOP_SYSAXI_SEL, 18),
+	GATE_INFRA1_INFRA(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_INFRA_SYSAXI_D2,
 			  19),
-	GATE_INFRA1_INFRA(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_ADC_FRC_CK, 20),
-	GATE_INFRA1_TOP(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M_SEL, 21),
-	GATE_INFRA1_TOP(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_TOP_NFI1X_SEL,
+	GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20),
+	GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M_SEL, 21),
+	GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X_SEL,
 			23),
 	/* INFRA2 */
-	GATE_INFRA2_TOP(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_TOP_SYSAXI_SEL,
+	GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI_SEL,
 			0),
-	GATE_INFRA2_INFRA(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_SYSAXI_D2,
+	GATE_INFRA2_INFRA(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_INFRA_SYSAXI_D2,
 			  1),
-	GATE_INFRA2_TOP(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_TOP_U2U3_SYS_SEL,
+	GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS_SEL,
 			2),
-	GATE_INFRA2_TOP(CK_INFRA_IUSB_CK, "infra_iusb", CK_TOP_U2U3_SEL, 3),
-	GATE_INFRA2_TOP(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_TOP_PEXTP_TL_SEL, 12),
-	GATE_INFRA2_TOP(CK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CK_TOP_XTAL, 13),
-	GATE_INFRA2_TOP(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_TOP_F26M_SEL, 14),
-	GATE_INFRA2_TOP(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_TOP_SYSAXI_SEL, 15),
+	GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_SEL, 3),
+	GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL_SEL, 12),
+	GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_XTAL, 13),
+	GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M_SEL, 14),
+	GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI_SEL, 15),
 	/* upstream linux unordered */
-	GATE_INFRA0_TOP(CK_INFRA_TRNG_CK, "infra_trng", CK_TOP_SYSAXI_SEL, 26),
+	GATE_INFRA0_TOP(CLK_INFRA_TRNG_CK, "infra_trng", CLK_TOP_SYSAXI_SEL, 26),
 };
 
 static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
@@ -522,8 +522,8 @@ static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
 };
 
 static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
-	.fdivs_offs = CK_TOP_XTAL_D2,
-	.muxes_offs = CK_TOP_NFI1X_SEL,
+	.fdivs_offs = CLK_TOP_XTAL_D2,
+	.muxes_offs = CLK_TOP_NFI1X_SEL,
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
 	.muxes = top_muxes,
@@ -531,9 +531,9 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
 };
 
 static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
-	.fdivs_offs = CK_INFRA_SYSAXI_D2,
-	.muxes_offs = CK_INFRA_UART0_SEL,
-	.gates_offs = CK_INFRA_GPT_STA,
+	.fdivs_offs = CLK_INFRA_SYSAXI_D2,
+	.muxes_offs = CLK_INFRA_UART0_SEL,
+	.gates_offs = CLK_INFRA_GPT_STA,
 	.fdivs = infra_fixed_divs,
 	.muxes = infra_muxes,
 	.gates = infracfg_gates,
@@ -619,11 +619,11 @@ static const struct mtk_gate_regs eth_cg_regs = {
 	}
 
 static const struct mtk_gate eth_cgs[] = {
-	GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X_SEL, 7),
-	GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M_SEL, 8),
-	GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M_SEL, 8),
-	GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_MCU_SEL, 14),
-	GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_MCU_SEL, 15),
+	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X_SEL, 7),
+	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M_SEL, 8),
+	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M_SEL, 8),
+	GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", CLK_TOP_NETSYS_MCU_SEL, 14),
+	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_MCU_SEL, 15),
 };
 
 static int mt7986_ethsys_probe(struct udevice *dev)
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 1c28ab34dcf..5da260386fd 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -10,167 +10,167 @@
 
 /* TOPCKGEN */
 
-#define CK_TOP_XTAL			0
-#define CK_TOP_XTAL_D2			1
-#define CK_TOP_RTC_32K			2
-#define CK_TOP_RTC_32P7K		3
-/* #define CK_TOP_A_TUNER		4 */
-#define CK_TOP_MPLL_D2			4
-#define CK_TOP_MPLL_D4			5
-#define CK_TOP_MPLL_D8			6
-#define CK_TOP_MPLL_D8_D2		7
-#define CK_TOP_MPLL_D3_D2		8
-#define CK_TOP_MMPLL_D2			9
-#define CK_TOP_MMPLL_D4			10
-#define CK_TOP_MMPLL_D8			11
-#define CK_TOP_MMPLL_D8_D2		12
-#define CK_TOP_MMPLL_D3_D8		13
-#define CK_TOP_MMPLL_U2PHYD		14
-#define CK_TOP_APLL2_D4			15
-#define CK_TOP_NET1PLL_D4		16
-#define CK_TOP_NET1PLL_D5		17
-#define CK_TOP_NET1PLL_D5_D2		18
-#define CK_TOP_NET1PLL_D5_D4		19
-#define CK_TOP_NET1PLL_D8_D2		20
-#define CK_TOP_NET1PLL_D8_D4		21
-#define CK_TOP_NET2PLL_D4		22
-#define CK_TOP_NET2PLL_D4_D2		23
-#define CK_TOP_NET2PLL_D3_D2		24
-#define CK_TOP_WEDMCUPLL_D5_D2		25
-#define CK_TOP_NFI1X_SEL		26
-#define CK_TOP_SPINFI_SEL		27
-#define CK_TOP_SPI_SEL			28
-#define CK_TOP_SPIM_MST_SEL		29
-#define CK_TOP_UART_SEL			30
-#define CK_TOP_PWM_SEL			31
-#define CK_TOP_I2C_SEL			32
-#define CK_TOP_PEXTP_TL_SEL		33
-#define CK_TOP_EMMC_250M_SEL		34
-#define CK_TOP_EMMC_416M_SEL		35
-#define CK_TOP_F_26M_ADC_SEL		36
-#define CK_TOP_DRAMC_SEL		37
-#define CK_TOP_DRAMC_MD32_SEL		38
-#define CK_TOP_SYSAXI_SEL		39
-#define CK_TOP_SYSAPB_SEL		40
-#define CK_TOP_ARM_DB_MAIN_SEL		41
-#define CK_TOP_ARM_DB_JTSEL		42
-#define CK_TOP_NETSYS_SEL		43
-#define CK_TOP_NETSYS_500M_SEL		44
-#define CK_TOP_NETSYS_MCU_SEL		45
-#define CK_TOP_NETSYS_2X_SEL		46
-#define CK_TOP_SGM_325M_SEL		47
-#define CK_TOP_SGM_REG_SEL		48
-#define CK_TOP_A1SYS_SEL		49
-#define CK_TOP_CONN_MCUSYS_SEL		50
-#define CK_TOP_EIP_B_SEL		51
-#define CK_TOP_PCIE_PHY_SEL		52
-#define CK_TOP_USB3_PHY_SEL		53
-#define CK_TOP_F26M_SEL			54
-#define CK_TOP_AUD_L_SEL		55
-#define CK_TOP_A_TUNER_SEL		56
-#define CK_TOP_U2U3_SEL			57
-#define CK_TOP_U2U3_SYS_SEL		58
-#define CK_TOP_U2U3_XHCI_SEL		59
-#define CK_TOP_DA_U2_REFSEL		60
-#define CK_TOP_DA_U2_CK_1P_SEL		61
-#define CK_TOP_AP2CNN_HOST_SEL		62
+#define CLK_TOP_XTAL			0
+#define CLK_TOP_XTAL_D2			1
+#define CLK_TOP_RTC_32K			2
+#define CLK_TOP_RTC_32P7K		3
+/* #define CLK_TOP_A_TUNER		4 */
+#define CLK_TOP_MPLL_D2			4
+#define CLK_TOP_MPLL_D4			5
+#define CLK_TOP_MPLL_D8			6
+#define CLK_TOP_MPLL_D8_D2		7
+#define CLK_TOP_MPLL_D3_D2		8
+#define CLK_TOP_MMPLL_D2			9
+#define CLK_TOP_MMPLL_D4			10
+#define CLK_TOP_MMPLL_D8			11
+#define CLK_TOP_MMPLL_D8_D2		12
+#define CLK_TOP_MMPLL_D3_D8		13
+#define CLK_TOP_MMPLL_U2PHYD		14
+#define CLK_TOP_APLL2_D4			15
+#define CLK_TOP_NET1PLL_D4		16
+#define CLK_TOP_NET1PLL_D5		17
+#define CLK_TOP_NET1PLL_D5_D2		18
+#define CLK_TOP_NET1PLL_D5_D4		19
+#define CLK_TOP_NET1PLL_D8_D2		20
+#define CLK_TOP_NET1PLL_D8_D4		21
+#define CLK_TOP_NET2PLL_D4		22
+#define CLK_TOP_NET2PLL_D4_D2		23
+#define CLK_TOP_NET2PLL_D3_D2		24
+#define CLK_TOP_WEDMCUPLL_D5_D2		25
+#define CLK_TOP_NFI1X_SEL		26
+#define CLK_TOP_SPINFI_SEL		27
+#define CLK_TOP_SPI_SEL			28
+#define CLK_TOP_SPIM_MST_SEL		29
+#define CLK_TOP_UART_SEL			30
+#define CLK_TOP_PWM_SEL			31
+#define CLK_TOP_I2C_SEL			32
+#define CLK_TOP_PEXTP_TL_SEL		33
+#define CLK_TOP_EMMC_250M_SEL		34
+#define CLK_TOP_EMMC_416M_SEL		35
+#define CLK_TOP_F_26M_ADC_SEL		36
+#define CLK_TOP_DRAMC_SEL		37
+#define CLK_TOP_DRAMC_MD32_SEL		38
+#define CLK_TOP_SYSAXI_SEL		39
+#define CLK_TOP_SYSAPB_SEL		40
+#define CLK_TOP_ARM_DB_MAIN_SEL		41
+#define CLK_TOP_ARM_DB_JTSEL		42
+#define CLK_TOP_NETSYS_SEL		43
+#define CLK_TOP_NETSYS_500M_SEL		44
+#define CLK_TOP_NETSYS_MCU_SEL		45
+#define CLK_TOP_NETSYS_2X_SEL		46
+#define CLK_TOP_SGM_325M_SEL		47
+#define CLK_TOP_SGM_REG_SEL		48
+#define CLK_TOP_A1SYS_SEL		49
+#define CLK_TOP_CONN_MCUSYS_SEL		50
+#define CLK_TOP_EIP_B_SEL		51
+#define CLK_TOP_PCIE_PHY_SEL		52
+#define CLK_TOP_USB3_PHY_SEL		53
+#define CLK_TOP_F26M_SEL			54
+#define CLK_TOP_AUD_L_SEL		55
+#define CLK_TOP_A_TUNER_SEL		56
+#define CLK_TOP_U2U3_SEL			57
+#define CLK_TOP_U2U3_SYS_SEL		58
+#define CLK_TOP_U2U3_XHCI_SEL		59
+#define CLK_TOP_DA_U2_REFSEL		60
+#define CLK_TOP_DA_U2_CK_1P_SEL		61
+#define CLK_TOP_AP2CNN_HOST_SEL		62
 #define CLK_TOP_NR_CLK			63
 
 /* INFRACFG */
 
-#define CK_INFRA_SYSAXI_D2		0
-#define CK_INFRA_UART0_SEL		1
-#define CK_INFRA_UART1_SEL		2
-#define CK_INFRA_UART2_SEL		3
-#define CK_INFRA_SPI0_SEL		4
-#define CK_INFRA_SPI1_SEL		5
-#define CK_INFRA_PWM1_SEL		6
-#define CK_INFRA_PWM2_SEL		7
-#define CK_INFRA_PWM_BSEL		8
-#define CK_INFRA_PCIE_SEL		9
-#define CK_INFRA_GPT_STA		10
-#define CK_INFRA_PWM_HCK		11
-#define CK_INFRA_PWM_STA		12
-#define CK_INFRA_PWM1_CK		13
-#define CK_INFRA_PWM2_CK		14
-#define CK_INFRA_CQ_DMA_CK		15
-#define CK_INFRA_EIP97_CK		16
-#define CK_INFRA_AUD_BUS_CK		17
-#define CK_INFRA_AUD_26M_CK		18
-#define CK_INFRA_AUD_L_CK		19
-#define CK_INFRA_AUD_AUD_CK		20
-#define CK_INFRA_AUD_EG2_CK		21
-#define CK_INFRA_DRAMC_26M_CK		22
-#define CK_INFRA_DBG_CK		23
-#define CK_INFRA_AP_DMA_CK		24
-#define CK_INFRA_SEJ_CK		25
-#define CK_INFRA_SEJ_13M_CK		26
-#define CK_INFRA_THERM_CK		27
-#define CK_INFRA_I2C0_CK		28
-#define CK_INFRA_UART0_CK		29
-#define CK_INFRA_UART1_CK		30
-#define CK_INFRA_UART2_CK		31
-#define CK_INFRA_NFI1_CK		32
-#define CK_INFRA_SPINFI1_CK		33
-#define CK_INFRA_NFI_HCK_CK		34
-#define CK_INFRA_SPI0_CK		35
-#define CK_INFRA_SPI1_CK		36
-#define CK_INFRA_SPI0_HCK_CK		37
-#define CK_INFRA_SPI1_HCK_CK		38
-#define CK_INFRA_FRTC_CK		39
-#define CK_INFRA_MSDC_CK		40
-#define CK_INFRA_MSDC_HCK_CK		41
-#define CK_INFRA_MSDC_133M_CK		42
-#define CK_INFRA_MSDC_66M_CK		43
-#define CK_INFRA_ADC_26M_CK		44
-#define CK_INFRA_ADC_FRC_CK		45
-#define CK_INFRA_FBIST2FPC_CK		46
-#define CK_INFRA_IUSB_133_CK		47
-#define CK_INFRA_IUSB_66M_CK		48
-#define CK_INFRA_IUSB_SYS_CK		49
-#define CK_INFRA_IUSB_CK		50
-#define CK_INFRA_IPCIE_CK		51
-#define CK_INFRA_IPCIE_PIPE_CK		52
-#define CK_INFRA_IPCIER_CK		53
-#define CK_INFRA_IPCIEB_CK		54
-#define CK_INFRA_TRNG_CK		55
-#define CK_INFRA_AO_NR_CLK		46
+#define CLK_INFRA_SYSAXI_D2		0
+#define CLK_INFRA_UART0_SEL		1
+#define CLK_INFRA_UART1_SEL		2
+#define CLK_INFRA_UART2_SEL		3
+#define CLK_INFRA_SPI0_SEL		4
+#define CLK_INFRA_SPI1_SEL		5
+#define CLK_INFRA_PWM1_SEL		6
+#define CLK_INFRA_PWM2_SEL		7
+#define CLK_INFRA_PWM_BSEL		8
+#define CLK_INFRA_PCIE_SEL		9
+#define CLK_INFRA_GPT_STA		10
+#define CLK_INFRA_PWM_HCK		11
+#define CLK_INFRA_PWM_STA		12
+#define CLK_INFRA_PWM1_CK		13
+#define CLK_INFRA_PWM2_CK		14
+#define CLK_INFRA_CQ_DMA_CK		15
+#define CLK_INFRA_EIP97_CK		16
+#define CLK_INFRA_AUD_BUS_CK		17
+#define CLK_INFRA_AUD_26M_CK		18
+#define CLK_INFRA_AUD_L_CK		19
+#define CLK_INFRA_AUD_AUD_CK		20
+#define CLK_INFRA_AUD_EG2_CK		21
+#define CLK_INFRA_DRAMC_26M_CK		22
+#define CLK_INFRA_DBG_CK		23
+#define CLK_INFRA_AP_DMA_CK		24
+#define CLK_INFRA_SEJ_CK		25
+#define CLK_INFRA_SEJ_13M_CK		26
+#define CLK_INFRA_THERM_CK		27
+#define CLK_INFRA_I2C0_CK		28
+#define CLK_INFRA_UART0_CK		29
+#define CLK_INFRA_UART1_CK		30
+#define CLK_INFRA_UART2_CK		31
+#define CLK_INFRA_NFI1_CK		32
+#define CLK_INFRA_SPINFI1_CK		33
+#define CLK_INFRA_NFI_HCK_CK		34
+#define CLK_INFRA_SPI0_CK		35
+#define CLK_INFRA_SPI1_CK		36
+#define CLK_INFRA_SPI0_HCK_CK		37
+#define CLK_INFRA_SPI1_HCK_CK		38
+#define CLK_INFRA_FRTC_CK		39
+#define CLK_INFRA_MSDC_CK		40
+#define CLK_INFRA_MSDC_HCK_CK		41
+#define CLK_INFRA_MSDC_133M_CK		42
+#define CLK_INFRA_MSDC_66M_CK		43
+#define CLK_INFRA_ADC_26M_CK		44
+#define CLK_INFRA_ADC_FRC_CK		45
+#define CLK_INFRA_FBIST2FPC_CK		46
+#define CLK_INFRA_IUSB_133_CK		47
+#define CLK_INFRA_IUSB_66M_CK		48
+#define CLK_INFRA_IUSB_SYS_CK		49
+#define CLK_INFRA_IUSB_CK		50
+#define CLK_INFRA_IPCIE_CK		51
+#define CLK_INFRA_IPCIE_PIPE_CK		52
+#define CLK_INFRA_IPCIER_CK		53
+#define CLK_INFRA_IPCIEB_CK		54
+#define CLK_INFRA_TRNG_CK		55
+#define CLK_INFRA_AO_NR_CLK		46
 
 /* APMIXEDSYS */
 
-#define CK_APMIXED_ARMPLL		0
-#define CK_APMIXED_NET2PLL		1
-#define CK_APMIXED_MMPLL		2
-#define CK_APMIXED_SGMPLL		3
-#define CK_APMIXED_WEDMCUPLL		4
-#define CK_APMIXED_NET1PLL		5
-#define CK_APMIXED_MPLL			6
-#define CK_APMIXED_APLL2		7
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_NET2PLL		1
+#define CLK_APMIXED_MMPLL		2
+#define CLK_APMIXED_SGMPLL		3
+#define CLK_APMIXED_WEDMCUPLL		4
+#define CLK_APMIXED_NET1PLL		5
+#define CLK_APMIXED_MPLL			6
+#define CLK_APMIXED_APLL2		7
 #define CLK_APMIXED_NR_CLK		8
 
 /* SGMIISYS_0 */
 
-#define CK_SGM0_TX_EN			0
-#define CK_SGM0_RX_EN			1
-#define CK_SGM0_CK0_EN			2
-#define CK_SGM0_CDR_CK0_EN		3
+#define CLK_SGM0_TX_EN			0
+#define CLK_SGM0_RX_EN			1
+#define CLK_SGM0_CK0_EN			2
+#define CLK_SGM0_CDR_CK0_EN		3
 #define CLK_SGMII0_NR_CLK		4
 
 /* SGMIISYS_1 */
 
-#define CK_SGM1_TX_EN			0
-#define CK_SGM1_RX_EN			1
-#define CK_SGM1_CK1_EN			2
-#define CK_SGM1_CDR_CK1_EN		3
+#define CLK_SGM1_TX_EN			0
+#define CLK_SGM1_RX_EN			1
+#define CLK_SGM1_CK1_EN			2
+#define CLK_SGM1_CDR_CK1_EN		3
 #define CLK_SGMII1_NR_CLK		4
 
 /* ETHSYS */
 
-#define CK_ETH_FE_EN			0
-#define CK_ETH_GP2_EN			1
-#define CK_ETH_GP1_EN			2
-#define CK_ETH_WOCPU1_EN		3
-#define CK_ETH_WOCPU0_EN		4
+#define CLK_ETH_FE_EN			0
+#define CLK_ETH_GP2_EN			1
+#define CLK_ETH_GP1_EN			2
+#define CLK_ETH_WOCPU1_EN		3
+#define CLK_ETH_WOCPU0_EN		4
 #define CLK_ETH_NR_CLK			5
 
 #endif
-- 
2.45.2

Aw: [PATCH 15/15] clk: mediatek: mt7986: rename CK to CLK

[Frank Wunderlich]

Hi

tested on r3 and r3mini

does not break downstream dts and works with slightly modified upstream dts.

tested mmc,usb,network,spi,pci/nvme

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank


> Gesendet: Samstag, 03. August 2024 um 10:40 Uhr
> Von: "Christian Marangi" <ansuelsmth@gmail.com>
> An: "Tom Rini" <trini@konsulko.com>, "Lukasz Majewski" <lukma@denx.de>, "Sean Anderson" <seanga2@gmail.com>, "Ryder Lee" <ryder.lee@mediatek.com>, "Weijie Gao" <weijie.gao@mediatek.com>, "Chunfeng Yun" <chunfeng.yun@mediatek.com>, "GSS_MTK_Uboot_upstream" <GSS_MTK_Uboot_upstream@mediatek.com>, "Christian Marangi" <ansuelsmth@gmail.com>, u-boot@lists.denx.de
> Betreff: [PATCH 15/15] clk: mediatek: mt7986: rename CK to CLK
>
> Rename each entry from CK to CLK to match the include in upstream kernel
> linux.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
>  arch/arm/dts/mt7986.dtsi               |  88 +++---
>  drivers/clk/mediatek/clk-mt7986.c      | 404 ++++++++++++-------------
>  include/dt-bindings/clock/mt7986-clk.h | 284 ++++++++---------
>  3 files changed, 388 insertions(+), 388 deletions(-)
>
> diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
> index a44f5386390..f871f2394c5 100644
> --- a/arch/arm/dts/mt7986.dtsi
> +++ b/arch/arm/dts/mt7986.dtsi
> @@ -78,7 +78,7 @@
>  		compatible = "mediatek,mt7986-timer";
>  		reg = <0x10008000 0x1000>;
>  		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&topckgen CK_TOP_F26M_SEL>;
> +		clocks = <&topckgen CLK_TOP_F26M_SEL>;
>  		clock-names = "gpt-clk";
>  		bootph-all;
>  	};
> @@ -147,18 +147,18 @@
>  		#clock-cells = <1>;
>  		#pwm-cells = <2>;
>  		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&topckgen CK_TOP_PWM_SEL>,
> -			 <&infracfg CK_INFRA_PWM_BSEL>,
> -			 <&infracfg CK_INFRA_PWM1_CK>,
> -			 <&infracfg CK_INFRA_PWM2_CK>;
> -		assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
> -				  <&infracfg CK_INFRA_PWM_BSEL>,
> -				  <&infracfg CK_INFRA_PWM1_SEL>,
> -				  <&infracfg CK_INFRA_PWM2_SEL>;
> -		assigned-clock-parents = <&topckgen CK_TOP_MPLL_D4>,
> -					 <&topckgen CK_TOP_PWM_SEL>,
> -					 <&topckgen CK_TOP_PWM_SEL>,
> -					 <&topckgen CK_TOP_PWM_SEL>;
> +		clocks = <&topckgen CLK_TOP_PWM_SEL>,
> +			 <&infracfg CLK_INFRA_PWM_BSEL>,
> +			 <&infracfg CLK_INFRA_PWM1_CK>,
> +			 <&infracfg CLK_INFRA_PWM2_CK>;
> +		assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
> +				  <&infracfg CLK_INFRA_PWM_BSEL>,
> +				  <&infracfg CLK_INFRA_PWM1_SEL>,
> +				  <&infracfg CLK_INFRA_PWM2_SEL>;
> +		assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D4>,
> +					 <&topckgen CLK_TOP_PWM_SEL>,
> +					 <&topckgen CLK_TOP_PWM_SEL>,
> +					 <&topckgen CLK_TOP_PWM_SEL>;
>  		clock-names = "top", "main", "pwm1", "pwm2";
>  		status = "disabled";
>  		bootph-all;
> @@ -168,11 +168,11 @@
>  		compatible = "mediatek,hsuart";
>  		reg = <0x11002000 0x400>;
>  		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&infracfg CK_INFRA_UART0_CK>;
> -		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
> -				  <&infracfg CK_INFRA_UART0_SEL>;
> -		assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
> -					 <&topckgen CK_TOP_UART_SEL>;
> +		clocks = <&infracfg CLK_INFRA_UART0_CK>;
> +		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
> +				  <&infracfg CLK_INFRA_UART0_SEL>;
> +		assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
> +					 <&topckgen CLK_TOP_UART_SEL>;
>  		mediatek,force-highspeed;
>  		status = "disabled";
>  		bootph-all;
> @@ -182,9 +182,9 @@
>  		compatible = "mediatek,hsuart";
>  		reg = <0x11003000 0x400>;
>  		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&infracfg CK_INFRA_UART1_CK>;
> -		assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
> -		assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
> +		clocks = <&infracfg CLK_INFRA_UART1_CK>;
> +		assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
> +		assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
>  		mediatek,force-highspeed;
>  		status = "disabled";
>  	};
> @@ -193,9 +193,9 @@
>  		compatible = "mediatek,hsuart";
>  		reg = <0x11004000 0x400>;
>  		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&infracfg CK_INFRA_UART2_CK>;
> -		assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
> -		assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
> +		clocks = <&infracfg CLK_INFRA_UART2_CK>;
> +		assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
> +		assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
>  		mediatek,force-highspeed;
>  		status = "disabled";
>  	};
> @@ -205,14 +205,14 @@
>  		reg = <0x11005000 0x1000>,
>  		      <0x11006000 0x1000>;
>  		reg-names = "nfi", "ecc";
> -		clocks = <&infracfg CK_INFRA_SPINFI1_CK>,
> -			 <&infracfg CK_INFRA_NFI1_CK>,
> -			 <&infracfg CK_INFRA_NFI_HCK_CK>;
> +		clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
> +			 <&infracfg CLK_INFRA_NFI1_CK>,
> +			 <&infracfg CLK_INFRA_NFI_HCK_CK>;
>  		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
> -		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
> -				  <&topckgen CK_TOP_NFI1X_SEL>;
> -		assigned-clock-parents = <&topckgen CK_TOP_MPLL_D8>,
> -					 <&topckgen CK_TOP_MPLL_D8>;
> +		assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
> +				  <&topckgen CLK_TOP_NFI1X_SEL>;
> +		assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
> +					 <&topckgen CLK_TOP_MPLL_D8>;
>  		status = "disabled";
>  	};
>
> @@ -251,12 +251,12 @@
>  	spi0: spi@1100a000 {
>  		compatible = "mediatek,ipm-spi";
>  		reg = <0x1100a000 0x100>;
> -		clocks = <&infracfg CK_INFRA_SPI0_CK>,
> -			 <&topckgen CK_TOP_SPI_SEL>;
> -		assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
> -				  <&infracfg CK_INFRA_SPI0_SEL>;
> -		assigned-clock-parents = <&topckgen CK_TOP_MPLL_D2>,
> -					 <&topckgen CK_TOP_SPI_SEL>;
> +		clocks = <&infracfg CLK_INFRA_SPI0_CK>,
> +			 <&topckgen CLK_TOP_SPI_SEL>;
> +		assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
> +				  <&infracfg CLK_INFRA_SPI0_SEL>;
> +		assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D2>,
> +					 <&topckgen CLK_TOP_SPI_SEL>;
>  		clock-names = "sel-clk", "spi-clk";
>  		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
> @@ -274,13 +274,13 @@
>  		reg = <0x11230000 0x1000>,
>  		      <0x11C20000 0x1000>;
>  		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
> -			<&topckgen CK_TOP_EMMC_250M_SEL>,
> -			<&infracfg CK_INFRA_MSDC_CK>;
> -		assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
> -				  <&topckgen CK_TOP_EMMC_250M_SEL>;
> -		assigned-clock-parents = <&fixed_plls CK_APMIXED_MPLL>,
> -					 <&topckgen CK_TOP_NET1PLL_D5_D2>;
> +		clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
> +			<&topckgen CLK_TOP_EMMC_250M_SEL>,
> +			<&infracfg CLK_INFRA_MSDC_CK>;
> +		assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
> +				  <&topckgen CLK_TOP_EMMC_250M_SEL>;
> +		assigned-clock-parents = <&fixed_plls CLK_APMIXED_MPLL>,
> +					 <&topckgen CLK_TOP_NET1PLL_D5_D2>;
>  		clock-names = "source", "hclk", "source_cg";
>  		status = "disabled";
>  	};
> diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
> index b163ffc9f1a..c5cc77243d0 100644
> --- a/drivers/clk/mediatek/clk-mt7986.c
> +++ b/drivers/clk/mediatek/clk-mt7986.c
> @@ -34,194 +34,194 @@
>
>  /* FIXED PLLS */
>  static const struct mtk_fixed_clk fixed_pll_clks[] = {
> -	FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
> -	FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
> -	FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
> -	FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
> -	FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
> -	FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
> -	FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
> -	FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
> +	FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
> +	FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
> +	FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
> +	FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
> +	FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
> +	FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
> +	FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
> +	FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
>  };
>
>  /* TOPCKGEN FIXED CLK */
>  static const struct mtk_fixed_clk top_fixed_clks[] = {
> -	FIXED_CLK(CK_TOP_XTAL, CLK_XTAL, 40000000),
> +	FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),
>  };
>
>  /* TOPCKGEN FIXED DIV */
>  static const struct mtk_fixed_factor top_fixed_divs[] = {
>  	/* TOP Factors */
> -	TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL,
> +	TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL,
>  		   1, 2),
> -	TOP_FACTOR(CK_TOP_RTC_32K, "rtc_32k", CK_TOP_XTAL, 1,
> +	TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1,
>  		   1250),
> -	TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
> +	TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1,
>  		   1220),
>  	/* Not defined upstream and not used */
> -	/* TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1), */
> +	/* TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 2, 1), */
>  	/* MPLL */
> -	PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
> -	PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
> -	PLL_FACTOR(CK_TOP_MPLL_D8, "mpll_d8", CK_APMIXED_MPLL, 1, 8),
> -	PLL_FACTOR(CK_TOP_MPLL_D8_D2, "mpll_d8_d2", CK_APMIXED_MPLL, 1, 16),
> -	PLL_FACTOR(CK_TOP_MPLL_D3_D2, "mpll_d3_d2", CK_APMIXED_MPLL, 1, 2),
> +	PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2),
> +	PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4),
> +	PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8),
> +	PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16),
> +	PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2),
>  	/* MMPLL */
> -	PLL_FACTOR(CK_TOP_MMPLL_D2, "mmpll_d2", CK_APMIXED_MMPLL, 1, 2),
> -	PLL_FACTOR(CK_TOP_MMPLL_D4, "mmpll_d4", CK_APMIXED_MMPLL, 1, 4),
> -	PLL_FACTOR(CK_TOP_MMPLL_D8, "mmpll_d8", CK_APMIXED_MMPLL, 1, 8),
> -	PLL_FACTOR(CK_TOP_MMPLL_D8_D2, "mmpll_d8_d2", CK_APMIXED_MMPLL, 1, 16),
> -	PLL_FACTOR(CK_TOP_MMPLL_D3_D8, "mmpll_d3_d8", CK_APMIXED_MMPLL, 1, 8),
> -	PLL_FACTOR(CK_TOP_MMPLL_U2PHYD, "mmpll_u2phy", CK_APMIXED_MMPLL, 1, 30),
> +	PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
> +	PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4),
> +	PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8),
> +	PLL_FACTOR(CLK_TOP_MMPLL_D8_D2, "mmpll_d8_d2", CLK_APMIXED_MMPLL, 1, 16),
> +	PLL_FACTOR(CLK_TOP_MMPLL_D3_D8, "mmpll_d3_d8", CLK_APMIXED_MMPLL, 1, 8),
> +	PLL_FACTOR(CLK_TOP_MMPLL_U2PHYD, "mmpll_u2phy", CLK_APMIXED_MMPLL, 1, 30),
>  	/* APLL2 */
> -	PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
> +	PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
>  	/* NET1PLL */
> -	PLL_FACTOR(CK_TOP_NET1PLL_D4, "net1pll_d4", CK_APMIXED_NET1PLL, 1, 4),
> -	PLL_FACTOR(CK_TOP_NET1PLL_D5, "net1pll_d5", CK_APMIXED_NET1PLL, 1, 5),
> -	PLL_FACTOR(CK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
> -	PLL_FACTOR(CK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
> -	PLL_FACTOR(CK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
> -	PLL_FACTOR(CK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
> +	PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4),
> +	PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5),
> +	PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
> +	PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
> +	PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
> +	PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
>  	/* NET2PLL */
> -	PLL_FACTOR(CK_TOP_NET2PLL_D4, "net2pll_d4", CK_APMIXED_NET2PLL, 1, 4),
> -	PLL_FACTOR(CK_TOP_NET2PLL_D4_D2, "net2pll_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
> -	PLL_FACTOR(CK_TOP_NET2PLL_D3_D2, "net2pll_d3_d2", CK_APMIXED_NET2PLL, 1, 2),
> +	PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4),
> +	PLL_FACTOR(CLK_TOP_NET2PLL_D4_D2, "net2pll_d4_d2", CLK_APMIXED_NET2PLL, 1, 8),
> +	PLL_FACTOR(CLK_TOP_NET2PLL_D3_D2, "net2pll_d3_d2", CLK_APMIXED_NET2PLL, 1, 2),
>  	/* WEDMCUPLL */
> -	PLL_FACTOR(CK_TOP_WEDMCUPLL_D5_D2, "wedmcupll_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
> +	PLL_FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "wedmcupll_d5_d2", CLK_APMIXED_WEDMCUPLL, 1,
>  		   10),
>  };
>
>  /* TOPCKGEN MUX PARENTS */
>  static const struct mtk_parent nfi1x_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D8),
> -	TOP_PARENT(CK_TOP_NET1PLL_D8_D2), TOP_PARENT(CK_TOP_NET2PLL_D3_D2),
> -	TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_MMPLL_D8_D2),
> -	TOP_PARENT(CK_TOP_WEDMCUPLL_D5_D2), TOP_PARENT(CK_TOP_MPLL_D8),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D8),
> +	TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2),
> +	TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8_D2),
> +	TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2), TOP_PARENT(CLK_TOP_MPLL_D8),
>  };
>
>  static const struct mtk_parent spinfi_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL_D2), TOP_PARENT(CK_TOP_XTAL),
> -	TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
> -	TOP_PARENT(CK_TOP_MMPLL_D8_D2), TOP_PARENT(CK_TOP_WEDMCUPLL_D5_D2),
> -	TOP_PARENT(CK_TOP_MMPLL_D3_D8), TOP_PARENT(CK_TOP_MPLL_D8),
> +	TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL),
> +	TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
> +	TOP_PARENT(CLK_TOP_MMPLL_D8_D2), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2),
> +	TOP_PARENT(CLK_TOP_MMPLL_D3_D8), TOP_PARENT(CLK_TOP_MPLL_D8),
>  };
>
>  static const struct mtk_parent spi_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
> -	TOP_PARENT(CK_TOP_MMPLL_D8), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
> -	TOP_PARENT(CK_TOP_NET2PLL_D3_D2), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
> -	TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_WEDMCUPLL_D5_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
> +	TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
> +	TOP_PARENT(CLK_TOP_NET2PLL_D3_D2), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
> +	TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2),
>  };
>
>  static const struct mtk_parent uart_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D8),
> -	TOP_PARENT(CK_TOP_MPLL_D8_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8),
> +	TOP_PARENT(CLK_TOP_MPLL_D8_D2),
>  };
>
>  static const struct mtk_parent pwm_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
> -	TOP_PARENT(CK_TOP_NET1PLL_D5_D4), TOP_PARENT(CK_TOP_MPLL_D4),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
> +	TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
>  };
>
>  static const struct mtk_parent i2c_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
> -	TOP_PARENT(CK_TOP_MPLL_D4), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
> +	TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
>  };
>
>  static const struct mtk_parent pextp_tl_ck_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
> -	TOP_PARENT(CK_TOP_NET2PLL_D4_D2), TOP_PARENT(CK_TOP_RTC_32K),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
> +	TOP_PARENT(CLK_TOP_NET2PLL_D4_D2), TOP_PARENT(CLK_TOP_RTC_32K),
>  };
>
>  static const struct mtk_parent emmc_250m_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
>  };
>
>  static const struct mtk_parent emmc_416m_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_MPLL),
> +	TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MPLL),
>  };
>
>  static const struct mtk_parent f_26m_adc_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D8_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
>  };
>
>  static const struct mtk_parent dramc_md32_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
>  };
>
>  static const struct mtk_parent sysaxi_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D2),
> -	TOP_PARENT(CK_TOP_NET2PLL_D4),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
> +	TOP_PARENT(CLK_TOP_NET2PLL_D4),
>  };
>
>  static const struct mtk_parent sysapb_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MPLL_D3_D2),
> -	TOP_PARENT(CK_TOP_NET2PLL_D4_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2),
> +	TOP_PARENT(CLK_TOP_NET2PLL_D4_D2),
>  };
>
>  static const struct mtk_parent arm_db_main_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET2PLL_D3_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2),
>  };
>
>  static const struct mtk_parent arm_db_jtsel_parents[] = {
> -	VOID_PARENT, TOP_PARENT(CK_TOP_XTAL),
> +	VOID_PARENT, TOP_PARENT(CLK_TOP_XTAL),
>  };
>
>  static const struct mtk_parent netsys_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D4),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4),
>  };
>
>  static const struct mtk_parent netsys_500m_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
>  };
>
>  static const struct mtk_parent netsys_mcu_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_WEDMCUPLL),
> -	TOP_PARENT(CK_TOP_MMPLL_D2), TOP_PARENT(CK_TOP_NET1PLL_D4),
> -	TOP_PARENT(CK_TOP_NET1PLL_D5),
> +	TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL),
> +	TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D4),
> +	TOP_PARENT(CLK_TOP_NET1PLL_D5),
>  };
>
>  static const struct mtk_parent netsys_2x_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_APMIXED_NET2PLL),
> -	APMIXED_PARENT(CK_APMIXED_WEDMCUPLL), TOP_PARENT(CK_TOP_MMPLL_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_APMIXED_NET2PLL),
> +	APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL), TOP_PARENT(CLK_TOP_MMPLL_D2),
>  };
>
>  static const struct mtk_parent sgm_325m_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_SGMPLL),
> +	TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
>  };
>
>  static const struct mtk_parent sgm_reg_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D8_D4),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
>  };
>
>  static const struct mtk_parent a1sys_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_APLL2_D4),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
>  };
>
>  static const struct mtk_parent conn_mcusys_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D2),
>  };
>
>  static const struct mtk_parent eip_b_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_NET2PLL),
> +	TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
>  };
>
>  static const struct mtk_parent aud_l_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), APMIXED_PARENT(CK_APMIXED_APLL2),
> -	TOP_PARENT(CK_TOP_MPLL_D8_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
> +	TOP_PARENT(CLK_TOP_MPLL_D8_D2),
>  };
>
>  static const struct mtk_parent a_tuner_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_APLL2_D4),
> -	TOP_PARENT(CK_TOP_MPLL_D8_D2),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
> +	TOP_PARENT(CLK_TOP_MPLL_D8_D2),
>  };
>
>  static const struct mtk_parent u2u3_sys_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_NET1PLL_D5_D4),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
>  };
>
>  static const struct mtk_parent da_u2_refsel_parents[] = {
> -	TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_MMPLL_U2PHYD),
> +	TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_U2PHYD),
>  };
>
>  #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,    \
> @@ -239,126 +239,126 @@ static const struct mtk_parent da_u2_refsel_parents[] = {
>  /* TOPCKGEN MUX_GATE */
>  static const struct mtk_composite top_muxes[] = {
>  	/* CLK_CFG_0 */
> -	TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
> +	TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
>  		0x008, 0, 3, 7, 0x1C0, 0),
> -	TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
> +	TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
>  		0x008, 8, 3, 15, 0x1C0, 1),
> -	TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
> +	TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
>  		3, 23, 0x1C0, 2),
> -	TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
> +	TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
>  		0x008, 24, 3, 31, 0x1C0, 3),
>  	/* CLK_CFG_1 */
> -	TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
> +	TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
>  		0, 2, 7, 0x1C0, 4),
> -	TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
> +	TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
>  		2, 15, 0x1C0, 5),
> -	TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
> +	TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
>  		2, 23, 0x1C0, 6),
> -	TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
> +	TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
>  		0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7),
>  	/* CLK_CFG_2 */
> -	TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
> +	TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
>  		0x024, 0x028, 0, 1, 7, 0x1C0, 8),
> -	TOP_MUX(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
> +	TOP_MUX(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
>  		0x024, 0x028, 8, 1, 15, 0x1C0, 9),
> -	TOP_MUX(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
> +	TOP_MUX(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
>  		0x024, 0x028, 16, 1, 23, 0x1C0, 10),
> -	TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
> +	TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
>  		0x028, 24, 1, 31, 0x1C0, 11),
>  	/* CLK_CFG_3 */
> -	TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
> +	TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
>  		0x030, 0x034, 0x038, 0, 1, 7, 0x1C0, 12),
> -	TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
> +	TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
>  		0x038, 8, 2, 15, 0x1C0, 13),
> -	TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
> +	TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
>  		0x038, 16, 2, 23, 0x1C0, 14),
> -	TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
> +	TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
>  		0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15),
>  	/* CLK_CFG_4 */
> -	TOP_MUX(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
> +	TOP_MUX(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
>  		0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16),
> -	TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
> +	TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
>  		0x048, 8, 1, 15, 0x1C0, 17),
> -	TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
> +	TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
>  		0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
> -	TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
> +	TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
>  		0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
>  	/* CLK_CFG_5 */
> -	TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
> +	TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
>  		0x054, 0x058, 0, 2, 7, 0x1C0, 20),
> -	TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
> +	TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
>  		0x054, 0x058, 8, 1, 15, 0x1C0, 21),
> -	TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
> +	TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
>  		0x054, 0x058, 16, 1, 23, 0x1C0, 22),
> -	TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
> +	TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
>  		0x058, 24, 1, 31, 0x1C0, 23),
>  	/* CLK_CFG_6 */
> -	TOP_MUX(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
> +	TOP_MUX(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
>  		0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
> -	TOP_MUX(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
> +	TOP_MUX(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
>  		0x068, 8, 1, 15, 0x1C0, 25),
> -	TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
> +	TOP_MUX(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
>  		0x064, 0x068, 16, 1, 23, 0x1C0, 26),
> -	TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
> +	TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
>  		0x064, 0x068, 24, 1, 31, 0x1C0, 27),
>  	/* CLK_CFG_7 */
> -	TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
> +	TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
>  		0x074, 0x078, 0, 1, 7, 0x1C0, 28),
> -	TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
> +	TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
>  		0x078, 8, 2, 15, 0x1C0, 29),
> -	TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
> +	TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
>  		0x074, 0x078, 16, 2, 23, 0x1C0, 30),
> -	TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
> +	TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
>  		0x078, 24, 1, 31, 0x1C4, 0),
>  	/* CLK_CFG_8 */
> -	TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
> +	TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
>  		0x084, 0x088, 0, 1, 7, 0x1C4, 1),
> -	TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
> +	TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
>  		0x084, 0x088, 8, 1, 15, 0x1C4, 2),
> -	TOP_MUX(CK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
> +	TOP_MUX(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
>  		0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3),
> -	TOP_MUX(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
> +	TOP_MUX(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
>  		0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
>  	/* CLK_CFG_9 */
> -	TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
> +	TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
>  		0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
>  };
>
>  /* INFRA FIXED DIV */
>  static const struct mtk_fixed_factor infra_fixed_divs[] = {
> -	TOP_FACTOR(CK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", CK_TOP_SYSAXI_SEL, 1, 2),
> +	TOP_FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", CLK_TOP_SYSAXI_SEL, 1, 2),
>  };
>
>  /* INFRASYS MUX PARENTS */
>
>
>  static const struct mtk_parent infra_uart0_parents[] = {
> -	TOP_PARENT(CK_TOP_F26M_SEL),
> -	TOP_PARENT(CK_TOP_UART_SEL)
> +	TOP_PARENT(CLK_TOP_F26M_SEL),
> +	TOP_PARENT(CLK_TOP_UART_SEL)
>  };
>
>  static const struct mtk_parent infra_spi0_parents[] = {
> -	TOP_PARENT(CK_TOP_I2C_SEL),
> -	TOP_PARENT(CK_TOP_SPI_SEL)
> +	TOP_PARENT(CLK_TOP_I2C_SEL),
> +	TOP_PARENT(CLK_TOP_SPI_SEL)
>  };
>
>  static const struct mtk_parent infra_spi1_parents[] = {
> -	TOP_PARENT(CK_TOP_I2C_SEL),
> -	TOP_PARENT(CK_TOP_SPINFI_SEL)
> +	TOP_PARENT(CLK_TOP_I2C_SEL),
> +	TOP_PARENT(CLK_TOP_SPINFI_SEL)
>  };
>
>  static const struct mtk_parent infra_pwm_bsel_parents[] = {
> -	TOP_PARENT(CK_TOP_RTC_32P7K),
> -	TOP_PARENT(CK_TOP_F26M_SEL),
> -	INFRA_PARENT(CK_INFRA_SYSAXI_D2),
> -	TOP_PARENT(CK_TOP_PWM_SEL)
> +	TOP_PARENT(CLK_TOP_RTC_32P7K),
> +	TOP_PARENT(CLK_TOP_F26M_SEL),
> +	INFRA_PARENT(CLK_INFRA_SYSAXI_D2),
> +	TOP_PARENT(CLK_TOP_PWM_SEL)
>  };
>
>  static const struct mtk_parent infra_pcie_parents[] = {
> -	TOP_PARENT(CK_TOP_RTC_32P7K),
> -	TOP_PARENT(CK_TOP_F26M_SEL),
> -	TOP_PARENT(CK_TOP_XTAL),
> -	TOP_PARENT(CK_TOP_PEXTP_TL_SEL)
> +	TOP_PARENT(CLK_TOP_RTC_32P7K),
> +	TOP_PARENT(CLK_TOP_F26M_SEL),
> +	TOP_PARENT(CLK_TOP_XTAL),
> +	TOP_PARENT(CLK_TOP_PEXTP_TL_SEL)
>  };
>
>  #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width)                  \
> @@ -374,24 +374,24 @@ static const struct mtk_parent infra_pcie_parents[] = {
>
>  static const struct mtk_composite infra_muxes[] = {
>  	/* MODULE_CLK_SEL_0 */
> -	INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
> +	INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
>  		  0x10, 0, 1),
> -	INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
> +	INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
>  		  0x10, 1, 1),
> -	INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
> +	INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
>  		  0x10, 2, 1),
> -	INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
> +	INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
>  		  4, 1),
> -	INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
> +	INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
>  		  5, 1),
> -	INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
> +	INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
>  		  0x10, 9, 2),
> -	INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
> +	INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
>  		  0x10, 11, 2),
> -	INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
> +	INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
>  		  0x10, 13, 2),
>  	/* MODULE_CLK_SEL_1 */
> -	INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
> +	INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
>  		  0, 2),
>  };
>
> @@ -450,68 +450,68 @@ static const struct mtk_gate_regs infra_2_cg_regs = {
>
>  static const struct mtk_gate infracfg_gates[] = {
>  	/* INFRA0 */
> -	GATE_INFRA0_INFRA(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_SYSAXI_D2, 0),
> -	GATE_INFRA0_INFRA(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_SYSAXI_D2, 1),
> -	GATE_INFRA0_INFRA(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BSEL, 2),
> -	GATE_INFRA0_INFRA(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM1_SEL, 3),
> -	GATE_INFRA0_INFRA(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM2_SEL, 4),
> -	GATE_INFRA0_TOP(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_TOP_SYSAXI_SEL, 6),
> -	GATE_INFRA0_TOP(CK_INFRA_EIP97_CK, "infra_eip97", CK_TOP_EIP_B_SEL, 7),
> -	GATE_INFRA0_TOP(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_TOP_SYSAXI_SEL, 8),
> -	GATE_INFRA0_TOP(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_TOP_F26M_SEL, 9),
> -	GATE_INFRA0_TOP(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_TOP_AUD_L_SEL, 10),
> -	GATE_INFRA0_TOP(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_TOP_A1SYS_SEL,
> +	GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_SYSAXI_D2, 0),
> +	GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_SYSAXI_D2, 1),
> +	GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2),
> +	GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3),
> +	GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4),
> +	GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI_SEL, 6),
> +	GATE_INFRA0_TOP(CLK_INFRA_EIP97_CK, "infra_eip97", CLK_TOP_EIP_B_SEL, 7),
> +	GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI_SEL, 8),
> +	GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9),
> +	GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L_SEL, 10),
> +	GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS_SEL,
>  			11),
> -	GATE_INFRA0_TOP(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_TOP_A_TUNER_SEL,
> +	GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER_SEL,
>  			13),
> -	GATE_INFRA0_TOP(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_TOP_F26M_SEL,
> +	GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL,
>  			14),
> -	GATE_INFRA0_INFRA(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_SYSAXI_D2, 15),
> -	GATE_INFRA0_INFRA(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_SYSAXI_D2, 16),
> -	GATE_INFRA0_INFRA(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_SYSAXI_D2, 24),
> -	GATE_INFRA0_TOP(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_TOP_F26M_SEL, 25),
> +	GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_SYSAXI_D2, 15),
> +	GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_SYSAXI_D2, 16),
> +	GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_SYSAXI_D2, 24),
> +	GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25),
>  	/* INFRA1 */
> -	GATE_INFRA1_TOP(CK_INFRA_THERM_CK, "infra_therm", CK_TOP_F26M_SEL, 0),
> -	GATE_INFRA1_TOP(CK_INFRA_I2C0_CK, "infra_i2co", CK_TOP_I2C_SEL, 1),
> -	GATE_INFRA1_INFRA(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_UART0_SEL, 2),
> -	GATE_INFRA1_INFRA(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_UART1_SEL, 3),
> -	GATE_INFRA1_INFRA(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_UART2_SEL, 4),
> -	GATE_INFRA1_TOP(CK_INFRA_NFI1_CK, "infra_nfi1", CK_TOP_NFI1X_SEL, 8),
> -	GATE_INFRA1_TOP(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_TOP_SPINFI_SEL,
> +	GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0),
> +	GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2co", CLK_TOP_I2C_SEL, 1),
> +	GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2),
> +	GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3),
> +	GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4),
> +	GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X_SEL, 8),
> +	GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_SEL,
>  			9),
> -	GATE_INFRA1_INFRA(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_SYSAXI_D2, 10),
> -	GATE_INFRA1_INFRA(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_SPI0_SEL, 11),
> -	GATE_INFRA1_INFRA(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_SPI1_SEL, 12),
> -	GATE_INFRA1_INFRA(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_SYSAXI_D2,
> +	GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_SYSAXI_D2, 10),
> +	GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11),
> +	GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12),
> +	GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_SYSAXI_D2,
>  			  13),
> -	GATE_INFRA1_INFRA(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_SYSAXI_D2,
> +	GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_SYSAXI_D2,
>  			  14),
> -	GATE_INFRA1_TOP(CK_INFRA_FRTC_CK, "infra_frtc", CK_TOP_RTC_32K, 15),
> -	GATE_INFRA1_TOP(CK_INFRA_MSDC_CK, "infra_msdc", CK_TOP_EMMC_416M_SEL, 16),
> -	GATE_INFRA1_TOP(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
> -			CK_TOP_EMMC_250M_SEL, 17),
> -	GATE_INFRA1_TOP(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
> -			CK_TOP_SYSAXI_SEL, 18),
> -	GATE_INFRA1_INFRA(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_SYSAXI_D2,
> +	GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_RTC_32K, 15),
> +	GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_416M_SEL, 16),
> +	GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
> +			CLK_TOP_EMMC_250M_SEL, 17),
> +	GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
> +			CLK_TOP_SYSAXI_SEL, 18),
> +	GATE_INFRA1_INFRA(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_INFRA_SYSAXI_D2,
>  			  19),
> -	GATE_INFRA1_INFRA(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_ADC_FRC_CK, 20),
> -	GATE_INFRA1_TOP(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M_SEL, 21),
> -	GATE_INFRA1_TOP(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_TOP_NFI1X_SEL,
> +	GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20),
> +	GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M_SEL, 21),
> +	GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X_SEL,
>  			23),
>  	/* INFRA2 */
> -	GATE_INFRA2_TOP(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_TOP_SYSAXI_SEL,
> +	GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI_SEL,
>  			0),
> -	GATE_INFRA2_INFRA(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_SYSAXI_D2,
> +	GATE_INFRA2_INFRA(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_INFRA_SYSAXI_D2,
>  			  1),
> -	GATE_INFRA2_TOP(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_TOP_U2U3_SYS_SEL,
> +	GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS_SEL,
>  			2),
> -	GATE_INFRA2_TOP(CK_INFRA_IUSB_CK, "infra_iusb", CK_TOP_U2U3_SEL, 3),
> -	GATE_INFRA2_TOP(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_TOP_PEXTP_TL_SEL, 12),
> -	GATE_INFRA2_TOP(CK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CK_TOP_XTAL, 13),
> -	GATE_INFRA2_TOP(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_TOP_F26M_SEL, 14),
> -	GATE_INFRA2_TOP(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_TOP_SYSAXI_SEL, 15),
> +	GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_SEL, 3),
> +	GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL_SEL, 12),
> +	GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_XTAL, 13),
> +	GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M_SEL, 14),
> +	GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI_SEL, 15),
>  	/* upstream linux unordered */
> -	GATE_INFRA0_TOP(CK_INFRA_TRNG_CK, "infra_trng", CK_TOP_SYSAXI_SEL, 26),
> +	GATE_INFRA0_TOP(CLK_INFRA_TRNG_CK, "infra_trng", CLK_TOP_SYSAXI_SEL, 26),
>  };
>
>  static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
> @@ -522,8 +522,8 @@ static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
>  };
>
>  static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
> -	.fdivs_offs = CK_TOP_XTAL_D2,
> -	.muxes_offs = CK_TOP_NFI1X_SEL,
> +	.fdivs_offs = CLK_TOP_XTAL_D2,
> +	.muxes_offs = CLK_TOP_NFI1X_SEL,
>  	.fclks = top_fixed_clks,
>  	.fdivs = top_fixed_divs,
>  	.muxes = top_muxes,
> @@ -531,9 +531,9 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
>  };
>
>  static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
> -	.fdivs_offs = CK_INFRA_SYSAXI_D2,
> -	.muxes_offs = CK_INFRA_UART0_SEL,
> -	.gates_offs = CK_INFRA_GPT_STA,
> +	.fdivs_offs = CLK_INFRA_SYSAXI_D2,
> +	.muxes_offs = CLK_INFRA_UART0_SEL,
> +	.gates_offs = CLK_INFRA_GPT_STA,
>  	.fdivs = infra_fixed_divs,
>  	.muxes = infra_muxes,
>  	.gates = infracfg_gates,
> @@ -619,11 +619,11 @@ static const struct mtk_gate_regs eth_cg_regs = {
>  	}
>
>  static const struct mtk_gate eth_cgs[] = {
> -	GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X_SEL, 7),
> -	GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M_SEL, 8),
> -	GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M_SEL, 8),
> -	GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_MCU_SEL, 14),
> -	GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_MCU_SEL, 15),
> +	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X_SEL, 7),
> +	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M_SEL, 8),
> +	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M_SEL, 8),
> +	GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", CLK_TOP_NETSYS_MCU_SEL, 14),
> +	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_MCU_SEL, 15),
>  };
>
>  static int mt7986_ethsys_probe(struct udevice *dev)
> diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
> index 1c28ab34dcf..5da260386fd 100644
> --- a/include/dt-bindings/clock/mt7986-clk.h
> +++ b/include/dt-bindings/clock/mt7986-clk.h
> @@ -10,167 +10,167 @@
>
>  /* TOPCKGEN */
>
> -#define CK_TOP_XTAL			0
> -#define CK_TOP_XTAL_D2			1
> -#define CK_TOP_RTC_32K			2
> -#define CK_TOP_RTC_32P7K		3
> -/* #define CK_TOP_A_TUNER		4 */
> -#define CK_TOP_MPLL_D2			4
> -#define CK_TOP_MPLL_D4			5
> -#define CK_TOP_MPLL_D8			6
> -#define CK_TOP_MPLL_D8_D2		7
> -#define CK_TOP_MPLL_D3_D2		8
> -#define CK_TOP_MMPLL_D2			9
> -#define CK_TOP_MMPLL_D4			10
> -#define CK_TOP_MMPLL_D8			11
> -#define CK_TOP_MMPLL_D8_D2		12
> -#define CK_TOP_MMPLL_D3_D8		13
> -#define CK_TOP_MMPLL_U2PHYD		14
> -#define CK_TOP_APLL2_D4			15
> -#define CK_TOP_NET1PLL_D4		16
> -#define CK_TOP_NET1PLL_D5		17
> -#define CK_TOP_NET1PLL_D5_D2		18
> -#define CK_TOP_NET1PLL_D5_D4		19
> -#define CK_TOP_NET1PLL_D8_D2		20
> -#define CK_TOP_NET1PLL_D8_D4		21
> -#define CK_TOP_NET2PLL_D4		22
> -#define CK_TOP_NET2PLL_D4_D2		23
> -#define CK_TOP_NET2PLL_D3_D2		24
> -#define CK_TOP_WEDMCUPLL_D5_D2		25
> -#define CK_TOP_NFI1X_SEL		26
> -#define CK_TOP_SPINFI_SEL		27
> -#define CK_TOP_SPI_SEL			28
> -#define CK_TOP_SPIM_MST_SEL		29
> -#define CK_TOP_UART_SEL			30
> -#define CK_TOP_PWM_SEL			31
> -#define CK_TOP_I2C_SEL			32
> -#define CK_TOP_PEXTP_TL_SEL		33
> -#define CK_TOP_EMMC_250M_SEL		34
> -#define CK_TOP_EMMC_416M_SEL		35
> -#define CK_TOP_F_26M_ADC_SEL		36
> -#define CK_TOP_DRAMC_SEL		37
> -#define CK_TOP_DRAMC_MD32_SEL		38
> -#define CK_TOP_SYSAXI_SEL		39
> -#define CK_TOP_SYSAPB_SEL		40
> -#define CK_TOP_ARM_DB_MAIN_SEL		41
> -#define CK_TOP_ARM_DB_JTSEL		42
> -#define CK_TOP_NETSYS_SEL		43
> -#define CK_TOP_NETSYS_500M_SEL		44
> -#define CK_TOP_NETSYS_MCU_SEL		45
> -#define CK_TOP_NETSYS_2X_SEL		46
> -#define CK_TOP_SGM_325M_SEL		47
> -#define CK_TOP_SGM_REG_SEL		48
> -#define CK_TOP_A1SYS_SEL		49
> -#define CK_TOP_CONN_MCUSYS_SEL		50
> -#define CK_TOP_EIP_B_SEL		51
> -#define CK_TOP_PCIE_PHY_SEL		52
> -#define CK_TOP_USB3_PHY_SEL		53
> -#define CK_TOP_F26M_SEL			54
> -#define CK_TOP_AUD_L_SEL		55
> -#define CK_TOP_A_TUNER_SEL		56
> -#define CK_TOP_U2U3_SEL			57
> -#define CK_TOP_U2U3_SYS_SEL		58
> -#define CK_TOP_U2U3_XHCI_SEL		59
> -#define CK_TOP_DA_U2_REFSEL		60
> -#define CK_TOP_DA_U2_CK_1P_SEL		61
> -#define CK_TOP_AP2CNN_HOST_SEL		62
> +#define CLK_TOP_XTAL			0
> +#define CLK_TOP_XTAL_D2			1
> +#define CLK_TOP_RTC_32K			2
> +#define CLK_TOP_RTC_32P7K		3
> +/* #define CLK_TOP_A_TUNER		4 */
> +#define CLK_TOP_MPLL_D2			4
> +#define CLK_TOP_MPLL_D4			5
> +#define CLK_TOP_MPLL_D8			6
> +#define CLK_TOP_MPLL_D8_D2		7
> +#define CLK_TOP_MPLL_D3_D2		8
> +#define CLK_TOP_MMPLL_D2			9
> +#define CLK_TOP_MMPLL_D4			10
> +#define CLK_TOP_MMPLL_D8			11
> +#define CLK_TOP_MMPLL_D8_D2		12
> +#define CLK_TOP_MMPLL_D3_D8		13
> +#define CLK_TOP_MMPLL_U2PHYD		14
> +#define CLK_TOP_APLL2_D4			15
> +#define CLK_TOP_NET1PLL_D4		16
> +#define CLK_TOP_NET1PLL_D5		17
> +#define CLK_TOP_NET1PLL_D5_D2		18
> +#define CLK_TOP_NET1PLL_D5_D4		19
> +#define CLK_TOP_NET1PLL_D8_D2		20
> +#define CLK_TOP_NET1PLL_D8_D4		21
> +#define CLK_TOP_NET2PLL_D4		22
> +#define CLK_TOP_NET2PLL_D4_D2		23
> +#define CLK_TOP_NET2PLL_D3_D2		24
> +#define CLK_TOP_WEDMCUPLL_D5_D2		25
> +#define CLK_TOP_NFI1X_SEL		26
> +#define CLK_TOP_SPINFI_SEL		27
> +#define CLK_TOP_SPI_SEL			28
> +#define CLK_TOP_SPIM_MST_SEL		29
> +#define CLK_TOP_UART_SEL			30
> +#define CLK_TOP_PWM_SEL			31
> +#define CLK_TOP_I2C_SEL			32
> +#define CLK_TOP_PEXTP_TL_SEL		33
> +#define CLK_TOP_EMMC_250M_SEL		34
> +#define CLK_TOP_EMMC_416M_SEL		35
> +#define CLK_TOP_F_26M_ADC_SEL		36
> +#define CLK_TOP_DRAMC_SEL		37
> +#define CLK_TOP_DRAMC_MD32_SEL		38
> +#define CLK_TOP_SYSAXI_SEL		39
> +#define CLK_TOP_SYSAPB_SEL		40
> +#define CLK_TOP_ARM_DB_MAIN_SEL		41
> +#define CLK_TOP_ARM_DB_JTSEL		42
> +#define CLK_TOP_NETSYS_SEL		43
> +#define CLK_TOP_NETSYS_500M_SEL		44
> +#define CLK_TOP_NETSYS_MCU_SEL		45
> +#define CLK_TOP_NETSYS_2X_SEL		46
> +#define CLK_TOP_SGM_325M_SEL		47
> +#define CLK_TOP_SGM_REG_SEL		48
> +#define CLK_TOP_A1SYS_SEL		49
> +#define CLK_TOP_CONN_MCUSYS_SEL		50
> +#define CLK_TOP_EIP_B_SEL		51
> +#define CLK_TOP_PCIE_PHY_SEL		52
> +#define CLK_TOP_USB3_PHY_SEL		53
> +#define CLK_TOP_F26M_SEL			54
> +#define CLK_TOP_AUD_L_SEL		55
> +#define CLK_TOP_A_TUNER_SEL		56
> +#define CLK_TOP_U2U3_SEL			57
> +#define CLK_TOP_U2U3_SYS_SEL		58
> +#define CLK_TOP_U2U3_XHCI_SEL		59
> +#define CLK_TOP_DA_U2_REFSEL		60
> +#define CLK_TOP_DA_U2_CK_1P_SEL		61
> +#define CLK_TOP_AP2CNN_HOST_SEL		62
>  #define CLK_TOP_NR_CLK			63
>
>  /* INFRACFG */
>
> -#define CK_INFRA_SYSAXI_D2		0
> -#define CK_INFRA_UART0_SEL		1
> -#define CK_INFRA_UART1_SEL		2
> -#define CK_INFRA_UART2_SEL		3
> -#define CK_INFRA_SPI0_SEL		4
> -#define CK_INFRA_SPI1_SEL		5
> -#define CK_INFRA_PWM1_SEL		6
> -#define CK_INFRA_PWM2_SEL		7
> -#define CK_INFRA_PWM_BSEL		8
> -#define CK_INFRA_PCIE_SEL		9
> -#define CK_INFRA_GPT_STA		10
> -#define CK_INFRA_PWM_HCK		11
> -#define CK_INFRA_PWM_STA		12
> -#define CK_INFRA_PWM1_CK		13
> -#define CK_INFRA_PWM2_CK		14
> -#define CK_INFRA_CQ_DMA_CK		15
> -#define CK_INFRA_EIP97_CK		16
> -#define CK_INFRA_AUD_BUS_CK		17
> -#define CK_INFRA_AUD_26M_CK		18
> -#define CK_INFRA_AUD_L_CK		19
> -#define CK_INFRA_AUD_AUD_CK		20
> -#define CK_INFRA_AUD_EG2_CK		21
> -#define CK_INFRA_DRAMC_26M_CK		22
> -#define CK_INFRA_DBG_CK		23
> -#define CK_INFRA_AP_DMA_CK		24
> -#define CK_INFRA_SEJ_CK		25
> -#define CK_INFRA_SEJ_13M_CK		26
> -#define CK_INFRA_THERM_CK		27
> -#define CK_INFRA_I2C0_CK		28
> -#define CK_INFRA_UART0_CK		29
> -#define CK_INFRA_UART1_CK		30
> -#define CK_INFRA_UART2_CK		31
> -#define CK_INFRA_NFI1_CK		32
> -#define CK_INFRA_SPINFI1_CK		33
> -#define CK_INFRA_NFI_HCK_CK		34
> -#define CK_INFRA_SPI0_CK		35
> -#define CK_INFRA_SPI1_CK		36
> -#define CK_INFRA_SPI0_HCK_CK		37
> -#define CK_INFRA_SPI1_HCK_CK		38
> -#define CK_INFRA_FRTC_CK		39
> -#define CK_INFRA_MSDC_CK		40
> -#define CK_INFRA_MSDC_HCK_CK		41
> -#define CK_INFRA_MSDC_133M_CK		42
> -#define CK_INFRA_MSDC_66M_CK		43
> -#define CK_INFRA_ADC_26M_CK		44
> -#define CK_INFRA_ADC_FRC_CK		45
> -#define CK_INFRA_FBIST2FPC_CK		46
> -#define CK_INFRA_IUSB_133_CK		47
> -#define CK_INFRA_IUSB_66M_CK		48
> -#define CK_INFRA_IUSB_SYS_CK		49
> -#define CK_INFRA_IUSB_CK		50
> -#define CK_INFRA_IPCIE_CK		51
> -#define CK_INFRA_IPCIE_PIPE_CK		52
> -#define CK_INFRA_IPCIER_CK		53
> -#define CK_INFRA_IPCIEB_CK		54
> -#define CK_INFRA_TRNG_CK		55
> -#define CK_INFRA_AO_NR_CLK		46
> +#define CLK_INFRA_SYSAXI_D2		0
> +#define CLK_INFRA_UART0_SEL		1
> +#define CLK_INFRA_UART1_SEL		2
> +#define CLK_INFRA_UART2_SEL		3
> +#define CLK_INFRA_SPI0_SEL		4
> +#define CLK_INFRA_SPI1_SEL		5
> +#define CLK_INFRA_PWM1_SEL		6
> +#define CLK_INFRA_PWM2_SEL		7
> +#define CLK_INFRA_PWM_BSEL		8
> +#define CLK_INFRA_PCIE_SEL		9
> +#define CLK_INFRA_GPT_STA		10
> +#define CLK_INFRA_PWM_HCK		11
> +#define CLK_INFRA_PWM_STA		12
> +#define CLK_INFRA_PWM1_CK		13
> +#define CLK_INFRA_PWM2_CK		14
> +#define CLK_INFRA_CQ_DMA_CK		15
> +#define CLK_INFRA_EIP97_CK		16
> +#define CLK_INFRA_AUD_BUS_CK		17
> +#define CLK_INFRA_AUD_26M_CK		18
> +#define CLK_INFRA_AUD_L_CK		19
> +#define CLK_INFRA_AUD_AUD_CK		20
> +#define CLK_INFRA_AUD_EG2_CK		21
> +#define CLK_INFRA_DRAMC_26M_CK		22
> +#define CLK_INFRA_DBG_CK		23
> +#define CLK_INFRA_AP_DMA_CK		24
> +#define CLK_INFRA_SEJ_CK		25
> +#define CLK_INFRA_SEJ_13M_CK		26
> +#define CLK_INFRA_THERM_CK		27
> +#define CLK_INFRA_I2C0_CK		28
> +#define CLK_INFRA_UART0_CK		29
> +#define CLK_INFRA_UART1_CK		30
> +#define CLK_INFRA_UART2_CK		31
> +#define CLK_INFRA_NFI1_CK		32
> +#define CLK_INFRA_SPINFI1_CK		33
> +#define CLK_INFRA_NFI_HCK_CK		34
> +#define CLK_INFRA_SPI0_CK		35
> +#define CLK_INFRA_SPI1_CK		36
> +#define CLK_INFRA_SPI0_HCK_CK		37
> +#define CLK_INFRA_SPI1_HCK_CK		38
> +#define CLK_INFRA_FRTC_CK		39
> +#define CLK_INFRA_MSDC_CK		40
> +#define CLK_INFRA_MSDC_HCK_CK		41
> +#define CLK_INFRA_MSDC_133M_CK		42
> +#define CLK_INFRA_MSDC_66M_CK		43
> +#define CLK_INFRA_ADC_26M_CK		44
> +#define CLK_INFRA_ADC_FRC_CK		45
> +#define CLK_INFRA_FBIST2FPC_CK		46
> +#define CLK_INFRA_IUSB_133_CK		47
> +#define CLK_INFRA_IUSB_66M_CK		48
> +#define CLK_INFRA_IUSB_SYS_CK		49
> +#define CLK_INFRA_IUSB_CK		50
> +#define CLK_INFRA_IPCIE_CK		51
> +#define CLK_INFRA_IPCIE_PIPE_CK		52
> +#define CLK_INFRA_IPCIER_CK		53
> +#define CLK_INFRA_IPCIEB_CK		54
> +#define CLK_INFRA_TRNG_CK		55
> +#define CLK_INFRA_AO_NR_CLK		46
>
>  /* APMIXEDSYS */
>
> -#define CK_APMIXED_ARMPLL		0
> -#define CK_APMIXED_NET2PLL		1
> -#define CK_APMIXED_MMPLL		2
> -#define CK_APMIXED_SGMPLL		3
> -#define CK_APMIXED_WEDMCUPLL		4
> -#define CK_APMIXED_NET1PLL		5
> -#define CK_APMIXED_MPLL			6
> -#define CK_APMIXED_APLL2		7
> +#define CLK_APMIXED_ARMPLL		0
> +#define CLK_APMIXED_NET2PLL		1
> +#define CLK_APMIXED_MMPLL		2
> +#define CLK_APMIXED_SGMPLL		3
> +#define CLK_APMIXED_WEDMCUPLL		4
> +#define CLK_APMIXED_NET1PLL		5
> +#define CLK_APMIXED_MPLL			6
> +#define CLK_APMIXED_APLL2		7
>  #define CLK_APMIXED_NR_CLK		8
>
>  /* SGMIISYS_0 */
>
> -#define CK_SGM0_TX_EN			0
> -#define CK_SGM0_RX_EN			1
> -#define CK_SGM0_CK0_EN			2
> -#define CK_SGM0_CDR_CK0_EN		3
> +#define CLK_SGM0_TX_EN			0
> +#define CLK_SGM0_RX_EN			1
> +#define CLK_SGM0_CK0_EN			2
> +#define CLK_SGM0_CDR_CK0_EN		3
>  #define CLK_SGMII0_NR_CLK		4
>
>  /* SGMIISYS_1 */
>
> -#define CK_SGM1_TX_EN			0
> -#define CK_SGM1_RX_EN			1
> -#define CK_SGM1_CK1_EN			2
> -#define CK_SGM1_CDR_CK1_EN		3
> +#define CLK_SGM1_TX_EN			0
> +#define CLK_SGM1_RX_EN			1
> +#define CLK_SGM1_CK1_EN			2
> +#define CLK_SGM1_CDR_CK1_EN		3
>  #define CLK_SGMII1_NR_CLK		4
>
>  /* ETHSYS */
>
> -#define CK_ETH_FE_EN			0
> -#define CK_ETH_GP2_EN			1
> -#define CK_ETH_GP1_EN			2
> -#define CK_ETH_WOCPU1_EN		3
> -#define CK_ETH_WOCPU0_EN		4
> +#define CLK_ETH_FE_EN			0
> +#define CLK_ETH_GP2_EN			1
> +#define CLK_ETH_GP1_EN			2
> +#define CLK_ETH_WOCPU1_EN		3
> +#define CLK_ETH_WOCPU0_EN		4
>  #define CLK_ETH_NR_CLK			5
>
>  #endif
> --
> 2.45.2
>
>

Re: [PATCH 00/15] clk: mediatek: mt7986: clk migration for OF_UPSTREAM

[Tom Rini]

On Sat, 03 Aug 2024 10:40:33 +0200, Christian Marangi wrote:

> These are all the required patches to migrate clk and correctly support
> OF_UPSTREAM. This will align the clk index to upstream to support the same
> clk implementation with downstream and upstream DTS.
> 
> Christian Marangi (15):
>   clk: mediatek: mt7986: fix wrong shift for PCIe clocks
>   clk: mediatek: mt7986: rename CB_CKSQ_40M to TOP_XTAL
>   clk: mediatek: mt7986: rename 66M_MCK to SYSAXI_D2
>   clk: mediatek: mt7986: fix wrong parent for INFRA_ADC_26M_CK
>   clk: mediatek: mt7986: drop 1/1 infracfg spurious factor
>   clk: mediatek: mt7986: add missing entry for IPCIE_PIPE_CK infra gate
>   clk: mediatek: mt7986: fix typo for infra_i2c0_ck
>   clk: mediatek: mt7986: rename TOPCKGEN factor clock to upstream naming
>   clk: mediatek: mt7986: reorder TOPCKGEN factor ID
>   clk: mediatek: mt7986: drop 1/1 spurious factor for topckgen
>   clk: mediatek: mt7986: comment out CK_TOP_A_TUNER as not used
>   clk: mediatek: mt7986: move INFRA_TRNG_CK to the bottom of the list
>   clk: mediatek: mt7986: replace infracfg ID with upstream linux
>   clk: mediatek: mt7986: convert to unified infracfg gates + muxes
>   clk: mediatek: mt7986: rename CK to CLK
> 
> [...]

Applied to u-boot/next, thanks!

-- 
Tom