From: Christian Marangi <ansuelsmth@gmail.com>
To: Tom Rini <trini@konsulko.com>, Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>,
Ryder Lee <ryder.lee@mediatek.com>,
Weijie Gao <weijie.gao@mediatek.com>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
Christian Marangi <ansuelsmth@gmail.com>,
u-boot@lists.denx.de
Subject: [PATCH 02/15] clk: mediatek: mt7986: rename CB_CKSQ_40M to TOP_XTAL
Date: Sat, 3 Aug 2024 10:40:35 +0200 [thread overview]
Message-ID: <20240803084050.449-3-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20240803084050.449-1-ansuelsmth@gmail.com>
Upstream kernel linux clock include use TOP_XTAL instead of CB_CKSQ_40M.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm/dts/mt7986.dtsi | 2 +-
drivers/clk/mediatek/clk-mt7986.c | 72 +++++++++++++-------------
include/dt-bindings/clock/mt7986-clk.h | 4 +-
3 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index 30b5a899701..276f82f2065 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -178,7 +178,7 @@
clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
<&infracfg CK_INFRA_UART>;
mediatek,force-highspeed;
status = "disabled";
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 1e8c3278346..67ed1768046 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -41,7 +41,7 @@ static const struct mtk_fixed_clk fixed_pll_clks[] = {
/* TOPCKGEN FIXED CLK */
static const struct mtk_fixed_clk top_fixed_clks[] = {
- FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
+ FIXED_CLK(CK_TOP_XTAL, CLK_XTAL, 40000000),
};
/* TOPCKGEN FIXED DIV */
@@ -77,18 +77,18 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
10),
PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- TOP_FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", CK_TOP_CB_CKSQ_40M,
+ TOP_FACTOR(CK_TOP_XTAL_D2, "xtal_d2", CK_TOP_XTAL,
1, 2),
- TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_XTAL, 1,
1250),
- TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_XTAL, 1,
1220),
TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_XTAL, 1,
1),
- TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
+ TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_XTAL, 1, 1),
+ TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_XTAL, 1, 1),
+ TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_XTAL, 1, 1),
TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
@@ -114,91 +114,91 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
};
/* TOPCKGEN MUX PARENTS */
-static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D8,
+static const int nfi1x_parents[] = { CK_TOP_XTAL, CK_TOP_CB_MM_D8,
CK_TOP_NET1_D8_D2, CK_TOP_NET2_D3_D2,
CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2,
CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 };
static const int spinfi_parents[] = {
- CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
+ CK_TOP_XTAL_D2, CK_TOP_XTAL, CK_TOP_NET1_D5_D4,
CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, CK_TOP_WEDMCU_D5_D2,
CK_TOP_MM_D3_D8, CK_TOP_CB_M_D8
};
-static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
+static const int spi_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D2,
CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D2,
CK_TOP_NET2_D3_D2, CK_TOP_NET1_D5_D4,
CK_TOP_CB_M_D4, CK_TOP_WEDMCU_D5_D2 };
-static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
+static const int uart_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D8,
CK_TOP_M_D8_D2 };
-static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
+static const int pwm_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D2,
CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 };
-static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
+static const int i2c_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D4,
CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
-static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int pextp_tl_ck_parents[] = { CK_TOP_XTAL,
CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2,
CK_TOP_CB_RTC_32K };
-static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int emmc_250m_parents[] = { CK_TOP_XTAL,
CK_TOP_NET1_D5_D2 };
-static const int emmc_416m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_416M };
+static const int emmc_416m_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_416M };
-static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
+static const int f_26m_adc_parents[] = { CK_TOP_XTAL, CK_TOP_M_D8_D2 };
-static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2 };
+static const int dramc_md32_parents[] = { CK_TOP_XTAL, CK_TOP_CB_M_D2 };
-static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
+static const int sysaxi_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D2,
CK_TOP_CB_NET2_D4 };
-static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2,
+static const int sysapb_parents[] = { CK_TOP_XTAL, CK_TOP_M_D3_D2,
CK_TOP_NET2_D4_D2 };
-static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int arm_db_main_parents[] = { CK_TOP_XTAL,
CK_TOP_NET2_D3_D2 };
-static const int arm_db_jtsel_parents[] = { -1, CK_TOP_CB_CKSQ_40M };
+static const int arm_db_jtsel_parents[] = { -1, CK_TOP_XTAL };
-static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4 };
+static const int netsys_parents[] = { CK_TOP_XTAL, CK_TOP_CB_MM_D4 };
-static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int netsys_500m_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_NET1_D5 };
-static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int netsys_mcu_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_WEDMCU_760M,
CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4,
CK_TOP_CB_NET1_D5 };
-static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int netsys_2x_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_NET2_800M,
CK_TOP_CB_WEDMCU_760M,
CK_TOP_CB_MM_D2 };
-static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int sgm_325m_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_SGM_325M };
-static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 };
+static const int sgm_reg_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D8_D4 };
-static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
+static const int a1sys_parents[] = { CK_TOP_XTAL, CK_TOP_APLL2_D4 };
-static const int conn_mcusys_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int conn_mcusys_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_MM_D2 };
-static const int eip_b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M };
+static const int eip_b_parents[] = { CK_TOP_XTAL, CK_TOP_CB_NET2_800M };
-static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
+static const int aud_l_parents[] = { CK_TOP_XTAL, CK_TOP_CB_APLL2_196M,
CK_TOP_M_D8_D2 };
-static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
+static const int a_tuner_parents[] = { CK_TOP_XTAL, CK_TOP_APLL2_D4,
CK_TOP_M_D8_D2 };
-static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+static const int u2u3_sys_parents[] = { CK_TOP_XTAL, CK_TOP_NET1_D5_D4 };
-static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M,
+static const int da_u2_refsel_parents[] = { CK_TOP_XTAL,
CK_TOP_CB_U2_PHYD_CK };
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 820f8631831..30720f9fb42 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -51,7 +51,7 @@
/* TOPCKGEN */
-#define CK_TOP_CB_CKSQ_40M 0
+#define CK_TOP_XTAL 0
#define CK_TOP_CB_M_416M 1
#define CK_TOP_CB_M_D2 2
#define CK_TOP_CB_M_D4 3
@@ -79,7 +79,7 @@
#define CK_TOP_CB_WEDMCU_760M 25
#define CK_TOP_WEDMCU_D5_D2 26
#define CK_TOP_CB_SGM_325M 27
-#define CK_TOP_CB_CKSQ_40M_D2 28
+#define CK_TOP_XTAL_D2 28
#define CK_TOP_CB_RTC_32K 29
#define CK_TOP_CB_RTC_32P7K 30
#define CK_TOP_NFI1X 31
--
2.45.2
next prev parent reply other threads:[~2024-08-03 11:10 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-03 8:40 [PATCH 00/15] clk: mediatek: mt7986: clk migration for OF_UPSTREAM Christian Marangi
2024-08-03 8:40 ` [PATCH 01/15] clk: mediatek: mt7986: fix wrong shift for PCIe clocks Christian Marangi
2024-08-03 8:40 ` Christian Marangi [this message]
2024-08-03 8:40 ` [PATCH 03/15] clk: mediatek: mt7986: rename 66M_MCK to SYSAXI_D2 Christian Marangi
2024-08-03 8:40 ` [PATCH 04/15] clk: mediatek: mt7986: fix wrong parent for INFRA_ADC_26M_CK Christian Marangi
2024-08-03 8:40 ` [PATCH 05/15] clk: mediatek: mt7986: drop 1/1 infracfg spurious factor Christian Marangi
2024-08-03 8:40 ` [PATCH 06/15] clk: mediatek: mt7986: add missing entry for IPCIE_PIPE_CK infra gate Christian Marangi
2024-08-03 8:40 ` [PATCH 07/15] clk: mediatek: mt7986: fix typo for infra_i2c0_ck Christian Marangi
2024-08-03 8:40 ` [PATCH 08/15] clk: mediatek: mt7986: rename TOPCKGEN factor clock to upstream naming Christian Marangi
2024-08-03 8:40 ` [PATCH 09/15] clk: mediatek: mt7986: reorder TOPCKGEN factor ID Christian Marangi
2024-08-03 8:40 ` [PATCH 10/15] clk: mediatek: mt7986: drop 1/1 spurious factor for topckgen Christian Marangi
2024-08-03 8:40 ` [PATCH 11/15] clk: mediatek: mt7986: comment out CK_TOP_A_TUNER as not used Christian Marangi
2024-08-03 8:40 ` [PATCH 12/15] clk: mediatek: mt7986: move INFRA_TRNG_CK to the bottom of the list Christian Marangi
2024-08-03 8:40 ` [PATCH 13/15] clk: mediatek: mt7986: replace infracfg ID with upstream linux Christian Marangi
2024-08-03 8:40 ` [PATCH 14/15] clk: mediatek: mt7986: convert to unified infracfg gates + muxes Christian Marangi
2024-08-03 8:40 ` [PATCH 15/15] clk: mediatek: mt7986: rename CK to CLK Christian Marangi
2024-08-10 13:31 ` Aw: " Frank Wunderlich
2024-08-20 0:29 ` [PATCH 00/15] clk: mediatek: mt7986: clk migration for OF_UPSTREAM Tom Rini
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