[PATCH v1 3/3] board: qemu-riscv: Override enable_caches

[Mayuresh Chitale <mchitale@ventanamicro.com>]

Define enable_caches function for the qemu-riscv board which probes for
the cbom-block-size dt property when RISCV_ISA_ZICBOM is enabled. Also
add flush_dcache_range and invalidate_dcache_range functions which use
the corresponding CBO ops.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
 board/emulation/qemu-riscv/qemu-riscv.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index e5193e31e3..1795d2f831 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -14,6 +14,7 @@
 #include <usb.h>
 #include <virtio_types.h>
 #include <virtio.h>
+#include <asm/cache.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -70,3 +71,18 @@ void *board_fdt_blob_setup(int *err)
 	/* Stored the DTB address there during our init */
 	return (void *)(ulong)gd->arch.firmware_fdt_addr;
 }
+
+void enable_caches(void)
+{
+	riscv_zicbom_init();
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+	cbo_flush(start, end);
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	cbo_inval(start, end);
+}
-- 
2.34.1