* [PATCH v4 1/9] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()
2024-08-29 1:30 [PATCH v4 0/9] Add Starfive JH7110 Cadence USB driver Minda Chen
@ 2024-08-29 1:30 ` Minda Chen
2024-08-30 1:11 ` Marek Vasut
2024-08-29 1:30 ` [PATCH v4 2/9] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver Minda Chen
` (7 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Minda Chen @ 2024-08-29 1:30 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
USB PHY maybe need to set PHY mode in different USB
dr mode. So translate USB PHY mode to generic PHY mode
and call generic_phy_set_mode().
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
drivers/usb/cdns3/drd.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c
index 47874fec29..cbb1334234 100644
--- a/drivers/usb/cdns3/drd.c
+++ b/drivers/usb/cdns3/drd.c
@@ -217,15 +217,19 @@ static int cdns3_init_otg_mode(struct cdns3 *cdns)
int cdns3_drd_update_mode(struct cdns3 *cdns)
{
int ret = 0;
+ int mode;
switch (cdns->dr_mode) {
case USB_DR_MODE_PERIPHERAL:
+ mode = PHY_MODE_USB_DEVICE;
ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL);
break;
case USB_DR_MODE_HOST:
+ mode = PHY_MODE_USB_HOST;
ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST);
break;
case USB_DR_MODE_OTG:
+ mode = PHY_MODE_USB_OTG;
ret = cdns3_init_otg_mode(cdns);
break;
default:
@@ -234,6 +238,16 @@ int cdns3_drd_update_mode(struct cdns3 *cdns)
return -EINVAL;
}
+ ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0);
+ if (ret) {
+ dev_err(cdns->dev, "Set usb 2.0 PHY mode failed %d\n", ret);
+ return ret;
+ }
+
+ ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0);
+ if (ret)
+ dev_err(cdns->dev, "Set usb 3.0 PHY mode failed %d\n", ret);
+
return ret;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 1/9] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()
2024-08-29 1:30 ` [PATCH v4 1/9] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() Minda Chen
@ 2024-08-30 1:11 ` Marek Vasut
0 siblings, 0 replies; 21+ messages in thread
From: Marek Vasut @ 2024-08-30 1:11 UTC (permalink / raw)
To: Minda Chen, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow
On 8/29/24 3:30 AM, Minda Chen wrote:
> USB PHY maybe need to set PHY mode in different USB
> dr mode. So translate USB PHY mode to generic PHY mode
> and call generic_phy_set_mode().
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Marek Vasut <marex@denx.de>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 2/9] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
2024-08-29 1:30 [PATCH v4 0/9] Add Starfive JH7110 Cadence USB driver Minda Chen
2024-08-29 1:30 ` [PATCH v4 1/9] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() Minda Chen
@ 2024-08-29 1:30 ` Minda Chen
2024-08-30 1:15 ` Marek Vasut
2024-08-29 1:30 ` [PATCH v4 3/9] phy: starfive: Add Starfive JH7110 PCIe " Minda Chen
` (6 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Minda Chen @ 2024-08-29 1:30 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add Starfive JH7110 USB 2.0 PHY driver, which is generic
PHY driver.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/starfive/Kconfig | 14 +++
drivers/phy/starfive/Makefile | 6 +
drivers/phy/starfive/phy-jh7110-usb2.c | 166 +++++++++++++++++++++++++
5 files changed, 188 insertions(+)
create mode 100644 drivers/phy/starfive/Kconfig
create mode 100644 drivers/phy/starfive/Makefile
create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e12347e8a0..f940648fe5 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -309,5 +309,6 @@ source "drivers/phy/cadence/Kconfig"
source "drivers/phy/ti/Kconfig"
source "drivers/phy/qcom/Kconfig"
source "drivers/phy/renesas/Kconfig"
+source "drivers/phy/starfive/Kconfig"
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 7a2b764492..6ac867350c 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -44,3 +44,4 @@ obj-y += cadence/
obj-y += ti/
obj-y += qcom/
obj-y += renesas/
+obj-y += starfive/
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
new file mode 100644
index 0000000000..f28529d1f9
--- /dev/null
+++ b/drivers/phy/starfive/Kconfig
@@ -0,0 +1,14 @@
+#
+# PHY drivers for Starfive platforms
+#
+
+menu "Starfive PHY driver"
+
+config PHY_STARFIVE_JH7110_USB2
+ bool "Starfive JH7110 USB 2.0 PHY driver"
+ select PHY
+ help
+ Enable this to support the Starfive JH7110 USB 2.0 PHY.
+ Generic PHY driver JH7110 USB 2.0.
+
+endmenu
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
new file mode 100644
index 0000000000..a405a75e34
--- /dev/null
+++ b/drivers/phy/starfive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Starfive
+#
+
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c b/drivers/phy/starfive/phy-jh7110-usb2.c
new file mode 100644
index 0000000000..6b5780e5fd
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb2.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <soc.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#define USB_LS_KEEPALIVE_OFF 0x4
+#define USB_LS_KEEPALIVE_ENABLE BIT(4)
+#define USB_PHY_CLK_RATE 125000000
+
+struct jh7110_usb2_phy {
+ struct phy *phy;
+ struct regmap *sys_syscon;
+ void __iomem *regs;
+ struct clk *usb_125m_clk;
+ struct clk *app_125m;
+ struct regmap_field *usb_split;
+ enum phy_mode mode;
+};
+
+static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set)
+{
+ /* Host mode enable the LS speed keep-alive signal */
+ if (set)
+ clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+ USB_LS_KEEPALIVE_ENABLE,
+ USB_LS_KEEPALIVE_ENABLE);
+ else
+ clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+ USB_LS_KEEPALIVE_ENABLE, 0);
+}
+
+static int usb2_phy_set_mode(struct phy *_phy,
+ enum phy_mode mode, int submode)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+ if (mode == phy->mode)
+ return 0;
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ dev_dbg(dev, "Changing phy to %d\n", mode);
+ phy->mode = mode;
+ usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE));
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* set default split usb 2.0 only mode */
+ regmap_field_write(phy->usb_split, true);
+
+ return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *_phy)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_set_rate(phy->usb_125m_clk, USB_PHY_CLK_RATE);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set 125m clock\n");
+ return ret;
+ }
+
+ return clk_prepare_enable(phy->app_125m);
+}
+
+static int jh7110_usb2_phy_exit(struct phy *_phy)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+ clk_disable_unprepare(phy->app_125m);
+
+ return 0;
+}
+
+struct phy_ops jh7110_usb2_phy_ops = {
+ .init = jh7110_usb2_phy_init,
+ .exit = jh7110_usb2_phy_exit,
+ .set_mode = usb2_phy_set_mode,
+};
+
+int jh7110_usb2_phy_probe(struct udevice *dev)
+{
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+ struct ofnode_phandle_args sys_phandle;
+ struct reg_field usb_split;
+ int ret;
+
+ phy->regs = dev_read_addr_ptr(dev);
+ if (!phy->regs)
+ return -EINVAL;
+
+ ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 1, 0,
+ &sys_phandle);
+
+ if (ret < 0) {
+ dev_err(dev, "Can't get sys cfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ phy->sys_syscon = syscon_node_to_regmap(sys_phandle.node);
+ if (IS_ERR(phy->sys_syscon)) {
+ dev_err(dev, "Can't get syscon regmap: %d\n", ret);
+ return PTR_ERR(phy->sys_syscon);
+ }
+
+ usb_split.reg = sys_phandle.args[0];
+ usb_split.lsb = 17;
+ usb_split.msb = 17;
+ phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split);
+ if (IS_ERR(phy->usb_split)) {
+ dev_err(dev, "USB split field init failed\n");
+ return PTR_ERR(phy->usb_split);
+ }
+
+ phy->usb_125m_clk = devm_clk_get(dev, "125m");
+ if (IS_ERR(phy->usb_125m_clk)) {
+ dev_err(dev, "Failed to get 125m clock\n");
+ return PTR_ERR(phy->usb_125m_clk);
+ }
+
+ phy->app_125m = devm_clk_get(dev, "app_125m");
+ if (IS_ERR(phy->app_125m)) {
+ dev_err(dev, "Failed to get app 125m clock\n");
+ return PTR_ERR(phy->app_125m);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id jh7110_usb2_phy[] = {
+ { .compatible = "starfive,jh7110-usb-phy"},
+ {},
+};
+
+U_BOOT_DRIVER(jh7110_usb2_phy) = {
+ .name = "jh7110_usb2_phy",
+ .id = UCLASS_PHY,
+ .of_match = jh7110_usb2_phy,
+ .probe = jh7110_usb2_phy_probe,
+ .ops = &jh7110_usb2_phy_ops,
+ .priv_auto = sizeof(struct jh7110_usb2_phy),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 2/9] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
2024-08-29 1:30 ` [PATCH v4 2/9] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver Minda Chen
@ 2024-08-30 1:15 ` Marek Vasut
2024-09-06 8:08 ` Minda Chen
0 siblings, 1 reply; 21+ messages in thread
From: Marek Vasut @ 2024-08-30 1:15 UTC (permalink / raw)
To: Minda Chen, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow
On 8/29/24 3:30 AM, Minda Chen wrote:
[...]
> +menu "Starfive PHY driver"
> +
> +config PHY_STARFIVE_JH7110_USB2
> + bool "Starfive JH7110 USB 2.0 PHY driver"
> + select PHY
Can this PHY_STARFIVE_JH7110_USB2 symbol be selected if CONFIG_PHY is
not set ? I think it cannot, so this 'select PHY' is unnecessary and
should be removed.
[...]
> +static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set)
> +{
> + /* Host mode enable the LS speed keep-alive signal */
> + if (set)
> + clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
> + USB_LS_KEEPALIVE_ENABLE,
> + USB_LS_KEEPALIVE_ENABLE);
> + else
> + clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
> + USB_LS_KEEPALIVE_ENABLE, 0);
Either use clrbits_le32() or use rework the function this way:
clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
USB_LS_KEEPALIVE_ENABLE,
set ? USB_LS_KEEPALIVE_ENABLE : 0);
[...]
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v4 2/9] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
2024-08-30 1:15 ` Marek Vasut
@ 2024-09-06 8:08 ` Minda Chen
2024-09-06 17:23 ` Marek Vasut
0 siblings, 1 reply; 21+ messages in thread
From: Minda Chen @ 2024-09-06 8:08 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot@lists.denx.de, Heinrich Schuchardt, Simon Glass, E Shattow
>
> On 8/29/24 3:30 AM, Minda Chen wrote:
>
> [...]
>
> > +menu "Starfive PHY driver"
> > +
> > +config PHY_STARFIVE_JH7110_USB2
> > + bool "Starfive JH7110 USB 2.0 PHY driver"
> > + select PHY
>
> Can this PHY_STARFIVE_JH7110_USB2 symbol be selected if CONFIG_PHY is not
> set ? I think it cannot, so this 'select PHY' is unnecessary and should be removed.
>
> [...]
>
Thanks. I will check it.
Other are format issues. I will modify them.
> > +static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool
> > +set) {
> > + /* Host mode enable the LS speed keep-alive signal */
> > + if (set)
> > + clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
> > + USB_LS_KEEPALIVE_ENABLE,
> > + USB_LS_KEEPALIVE_ENABLE);
> > + else
> > + clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
> > + USB_LS_KEEPALIVE_ENABLE, 0);
>
> Either use clrbits_le32() or use rework the function this way:
>
> clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
> USB_LS_KEEPALIVE_ENABLE,
> set ? USB_LS_KEEPALIVE_ENABLE : 0);
>
> [...]
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v4 2/9] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
2024-09-06 8:08 ` Minda Chen
@ 2024-09-06 17:23 ` Marek Vasut
0 siblings, 0 replies; 21+ messages in thread
From: Marek Vasut @ 2024-09-06 17:23 UTC (permalink / raw)
To: Minda Chen, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot@lists.denx.de, Heinrich Schuchardt, Simon Glass, E Shattow
On 9/6/24 10:08 AM, Minda Chen wrote:
>
>
>>
>> On 8/29/24 3:30 AM, Minda Chen wrote:
>>
>> [...]
>>
>>> +menu "Starfive PHY driver"
>>> +
>>> +config PHY_STARFIVE_JH7110_USB2
>>> + bool "Starfive JH7110 USB 2.0 PHY driver"
>>> + select PHY
>>
>> Can this PHY_STARFIVE_JH7110_USB2 symbol be selected if CONFIG_PHY is not
>> set ? I think it cannot, so this 'select PHY' is unnecessary and should be removed.
>>
>> [...]
>>
> Thanks. I will check it.
> Other are format issues. I will modify them.
Thank you
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 3/9] phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
2024-08-29 1:30 [PATCH v4 0/9] Add Starfive JH7110 Cadence USB driver Minda Chen
2024-08-29 1:30 ` [PATCH v4 1/9] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() Minda Chen
2024-08-29 1:30 ` [PATCH v4 2/9] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver Minda Chen
@ 2024-08-29 1:30 ` Minda Chen
2024-08-30 1:17 ` Marek Vasut
2024-08-29 1:30 ` [PATCH v4 4/9] usb: cdns: starfive: Add cdns USB driver Minda Chen
` (5 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Minda Chen @ 2024-08-29 1:30 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic
PHY driver and can be used as USB 3.0 driver.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
drivers/phy/starfive/Kconfig | 7 +
drivers/phy/starfive/Makefile | 1 +
drivers/phy/starfive/phy-jh7110-pcie.c | 237 +++++++++++++++++++++++++
3 files changed, 245 insertions(+)
create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index f28529d1f9..0843070b74 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -4,6 +4,13 @@
menu "Starfive PHY driver"
+config PHY_STARFIVE_JH7110_PCIE
+ bool "Starfive JH7110 PCIe 2.0 PHY driver"
+ select PHY
+ help
+ Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY.
+ Generic PHY driver JH7110 USB 3.0/ PCIe 2.0.
+
config PHY_STARFIVE_JH7110_USB2
bool "Starfive JH7110 USB 2.0 PHY driver"
select PHY
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index a405a75e34..82f25aa21b 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -3,4 +3,5 @@
# Copyright (C) 2023 Starfive
#
+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c
new file mode 100644
index 0000000000..d3b04cd166
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-pcie.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 PCIe 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <soc.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#define PCIE_KVCO_LEVEL_OFF 0x28
+#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c
+#define PCIE_USB3_PHY_SS_MODE BIT(4)
+#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80
+#define PHY_KVCO_FINE_TUNE_LEVEL 0x91
+#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc
+
+#define PCIE_USB3_PHY_MODE 0x1
+#define PCIE_BUS_WIDTH 0x2
+#define PCIE_USB3_PHY_ENABLE 0x1
+#define PCIE_USB3_PHY_SPLIT 0x1
+
+struct jh7110_pcie_phy {
+ struct phy *phy;
+ struct regmap *stg_syscon;
+ struct regmap *sys_syscon;
+ void __iomem *regs;
+ struct regmap_field *phy_mode;
+ struct regmap_field *bus_width;
+ struct regmap_field *usb3_phy_en;
+ struct regmap_field *usb_split;
+ enum phy_mode mode;
+};
+
+static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode)
+{
+ unsigned int phy_mode, width, usb3_phy, ss_mode, split;
+
+ /* default is PCIe mode */
+ if (!data->stg_syscon || !data->sys_syscon) {
+ if (usb_mode) {
+ dev_err(data->phy->dev, "doesn't support usb3 mode\n");
+ return -EINVAL;
+ }
+ return 0;
+ }
+
+ if (usb_mode) {
+ phy_mode = PCIE_USB3_PHY_MODE;
+ width = 0;
+ usb3_phy = PCIE_USB3_PHY_ENABLE;
+ ss_mode = PCIE_USB3_PHY_SS_MODE;
+ split = 0;
+ } else {
+ phy_mode = 0;
+ width = PCIE_BUS_WIDTH;
+ usb3_phy = 0;
+ ss_mode = 0;
+ split = PCIE_USB3_PHY_SPLIT;
+ }
+
+ regmap_field_write(data->phy_mode, phy_mode);
+ regmap_field_write(data->bus_width, width);
+ regmap_field_write(data->usb3_phy_en, usb3_phy);
+ clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF,
+ PCIE_USB3_PHY_SS_MODE, ss_mode);
+ regmap_field_write(data->usb_split, split);
+
+ return 0;
+}
+
+static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
+{
+ /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
+ writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
+ writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
+}
+
+static int jh7110_pcie_phy_set_mode(struct phy *_phy,
+ enum phy_mode mode, int submode)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ int ret;
+
+ if (mode == phy->mode)
+ return 0;
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ ret = phy_pcie_mode_set(phy, 1);
+ if (ret)
+ return ret;
+ break;
+ case PHY_MODE_PCIE:
+ phy_pcie_mode_set(phy, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dev_dbg(_phy->dev, "Changing phy mode to %d\n", mode);
+ phy->mode = mode;
+
+ return 0;
+}
+
+static const struct phy_ops jh7110_pcie_phy_ops = {
+ .set_mode = jh7110_pcie_phy_set_mode,
+};
+
+static int phy_stg_regfield_init(struct udevice *dev, int mode, int usb3)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ struct reg_field phy_mode = REG_FIELD(mode, 20, 21);
+ struct reg_field bus_width = REG_FIELD(usb3, 2, 3);
+ struct reg_field usb3_phy_en = REG_FIELD(usb3, 4, 4);
+
+ phy->phy_mode = devm_regmap_field_alloc(dev, phy->stg_syscon, phy_mode);
+ if (IS_ERR(phy->phy_mode)) {
+ dev_err(dev, "PHY mode reg field init failed\n");
+ return PTR_ERR(phy->phy_mode);
+ }
+
+ phy->bus_width = devm_regmap_field_alloc(dev, phy->stg_syscon, bus_width);
+ if (IS_ERR(phy->bus_width)) {
+ dev_err(dev, "PHY bus width reg field init failed\n");
+ return PTR_ERR(phy->bus_width);
+ }
+
+ phy->usb3_phy_en = devm_regmap_field_alloc(dev, phy->stg_syscon, usb3_phy_en);
+ if (IS_ERR(phy->usb3_phy_en)) {
+ dev_err(dev, "USB3 PHY enable field init failed\n");
+ return PTR_ERR(phy->bus_width);
+ }
+
+ return 0;
+}
+
+static int phy_sys_regfield_init(struct udevice *dev, int split)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ struct reg_field usb_split = REG_FIELD(split, 17, 17);
+
+ phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split);
+ if (IS_ERR(phy->usb_split)) {
+ dev_err(dev, "USB split field init failed\n");
+ return PTR_ERR(phy->usb_split);
+ }
+
+ return 0;
+}
+
+static int starfive_pcie_phy_get_syscon(struct udevice *dev)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ struct ofnode_phandle_args sys_phandle, stg_phandle;
+ int ret;
+
+ /* get corresponding syscon phandle */
+ ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 1, 0,
+ &sys_phandle);
+
+ if (ret < 0) {
+ dev_err(dev, "Can't get sys cfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 2, 0,
+ &stg_phandle);
+
+ if (ret < 0) {
+ dev_err(dev, "Can't get stg cfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ phy->sys_syscon = syscon_node_to_regmap(sys_phandle.node);
+ /* get syscon register offset */
+ if (!IS_ERR(phy->sys_syscon)) {
+ ret = phy_sys_regfield_init(dev, sys_phandle.args[0]);
+ if (ret)
+ return ret;
+ } else {
+ phy->sys_syscon = NULL;
+ }
+
+ phy->stg_syscon = syscon_node_to_regmap(stg_phandle.node);
+ if (!IS_ERR(phy->stg_syscon))
+ return phy_stg_regfield_init(dev, stg_phandle.args[0],
+ stg_phandle.args[1]);
+ else
+ phy->stg_syscon = NULL;
+
+ return 0;
+}
+
+int jh7110_pcie_phy_probe(struct udevice *dev)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ int rc;
+
+ phy->regs = dev_read_addr_ptr(dev);
+ if (!phy->regs)
+ return -EINVAL;
+
+ rc = starfive_pcie_phy_get_syscon(dev);
+ if (rc)
+ return rc;
+
+ phy_kvco_gain_set(phy);
+
+ return 0;
+}
+
+static const struct udevice_id jh7110_pcie_phy[] = {
+ { .compatible = "starfive,jh7110-pcie-phy"},
+ {},
+};
+
+U_BOOT_DRIVER(jh7110_pcie_phy) = {
+ .name = "jh7110_pcie_phy",
+ .id = UCLASS_PHY,
+ .of_match = jh7110_pcie_phy,
+ .probe = jh7110_pcie_phy_probe,
+ .ops = &jh7110_pcie_phy_ops,
+ .priv_auto = sizeof(struct jh7110_pcie_phy),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 3/9] phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
2024-08-29 1:30 ` [PATCH v4 3/9] phy: starfive: Add Starfive JH7110 PCIe " Minda Chen
@ 2024-08-30 1:17 ` Marek Vasut
0 siblings, 0 replies; 21+ messages in thread
From: Marek Vasut @ 2024-08-30 1:17 UTC (permalink / raw)
To: Minda Chen, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow
On 8/29/24 3:30 AM, Minda Chen wrote:
[...]
> +static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode)
> +{
> + unsigned int phy_mode, width, usb3_phy, ss_mode, split;
> +
> + /* default is PCIe mode */
> + if (!data->stg_syscon || !data->sys_syscon) {
> + if (usb_mode) {
> + dev_err(data->phy->dev, "doesn't support usb3 mode\n");
USB3 in capitals , USB is an abbreviation.
[...]
> +static int jh7110_pcie_phy_set_mode(struct phy *_phy,
Use plain 'phy' variable name, drop the leading underscore .
> + enum phy_mode mode, int submode)
> +{
> + struct udevice *dev = _phy->dev;
> + struct jh7110_pcie_phy *phy = dev_get_priv(dev);
> + int ret;
> +
> + if (mode == phy->mode)
> + return 0;
> +
> + switch (mode) {
> + case PHY_MODE_USB_HOST:
> + case PHY_MODE_USB_DEVICE:
> + case PHY_MODE_USB_OTG:
> + ret = phy_pcie_mode_set(phy, 1);
> + if (ret)
> + return ret;
> + break;
> + case PHY_MODE_PCIE:
> + phy_pcie_mode_set(phy, 0);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + dev_dbg(_phy->dev, "Changing phy mode to %d\n", mode);
PHY in capitals.
> + phy->mode = mode;
> +
> + return 0;
> +}
Looks pretty good, thanks !
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 4/9] usb: cdns: starfive: Add cdns USB driver
2024-08-29 1:30 [PATCH v4 0/9] Add Starfive JH7110 Cadence USB driver Minda Chen
` (2 preceding siblings ...)
2024-08-29 1:30 ` [PATCH v4 3/9] phy: starfive: Add Starfive JH7110 PCIe " Minda Chen
@ 2024-08-29 1:30 ` Minda Chen
2024-08-30 1:20 ` Marek Vasut
2024-08-29 1:30 ` [PATCH v4 5/9] spl: starfive: visionfive2: Disable USB overcurrent pin by default Minda Chen
` (4 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Minda Chen @ 2024-08-29 1:30 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add cdns USB3 wrapper driver.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
drivers/usb/cdns3/Kconfig | 7 ++
drivers/usb/cdns3/Makefile | 2 +
drivers/usb/cdns3/cdns3-starfive.c | 191 +++++++++++++++++++++++++++++
3 files changed, 200 insertions(+)
create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index 35b61497d9..f8f363982b 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -55,4 +55,11 @@ config USB_CDNS3_TI
help
Say 'Y' here if you are building for Texas Instruments
platforms that contain Cadence USB3 controller core. E.g.: J721e.
+
+config USB_CDNS3_STARFIVE
+ tristate "Cadence USB3 support on Starfive platforms"
+ default USB_CDNS3
+ help
+ Say 'Y' here if you are building for Starfive platforms
+ that contain Cadence USB3 controller core. E.g.: JH7110.
endif
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index 18d7190755..03d1eadb2f 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -9,3 +9,5 @@ cdns3-$(CONFIG_$(SPL_)USB_CDNS3_GADGET) += gadget.o ep0.o
cdns3-$(CONFIG_$(SPL_)USB_CDNS3_HOST) += host.o
obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
+
+obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o
diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
new file mode 100644
index 0000000000..839d72e4e1
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/usb/otg.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <malloc.h>
+
+#include "core.h"
+
+#define USB_STRAP_HOST BIT(17)
+#define USB_STRAP_DEVICE BIT(18)
+#define USB_STRAP_MASK GENMASK(18, 16)
+
+#define USB_SUSPENDM_HOST BIT(19)
+#define USB_SUSPENDM_MASK BIT(19)
+
+#define USB_MISC_CFG_MASK GENMASK(23, 20)
+#define USB_SUSPENDM_BYPS BIT(20)
+#define USB_PLL_EN BIT(22)
+#define USB_REFCLK_MODE BIT(23)
+
+struct cdns_starfive {
+ struct udevice *dev;
+ struct regmap *stg_syscon;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ u32 stg_usb_mode;
+ enum usb_dr_mode mode;
+};
+
+static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode)
+{
+ unsigned int strap, suspendm;
+
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_MISC_CFG_MASK,
+ USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
+
+ switch (mode) {
+ case USB_DR_MODE_HOST:
+ strap = USB_STRAP_HOST;
+ suspendm = USB_SUSPENDM_HOST;
+ break;
+
+ case USB_DR_MODE_PERIPHERAL:
+ strap = USB_STRAP_DEVICE;
+ suspendm = 0;
+ break;
+ default:
+ return;
+ }
+
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_STRAP_MASK, strap);
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_SUSPENDM_MASK, suspendm);
+}
+
+static void cdns_clk_rst_deinit(struct cdns_starfive *data)
+{
+ reset_assert_bulk(&data->resets);
+ clk_disable_bulk(&data->clks);
+}
+
+static int cdns_clk_rst_init(struct cdns_starfive *data)
+{
+ int ret;
+
+ ret = clk_get_bulk(data->dev, &data->clks);
+ if (ret)
+ return ret;
+
+ ret = reset_get_bulk(data->dev, &data->resets);
+ if (ret)
+ goto err_clk;
+
+ ret = clk_enable_bulk(&data->clks);
+ if (ret) {
+ dev_err(data->dev, "clk enable failed: %d\n", ret);
+ goto err_en_clk;
+ }
+
+ ret = reset_deassert_bulk(&data->resets);
+ if (ret) {
+ dev_err(data->dev, "reset deassert failed: %d\n", ret);
+ goto err_reset;
+ }
+
+ return 0;
+
+err_reset:
+ clk_disable_bulk(&data->clks);
+err_en_clk:
+ reset_release_bulk(&data->resets);
+err_clk:
+ clk_release_bulk(&data->clks);
+
+ return ret;
+}
+
+static int cdns_starfive_get_syscon(struct cdns_starfive *data)
+{
+ struct ofnode_phandle_args phandle;
+ int ret;
+
+ ret = dev_read_phandle_with_args(data->dev, "starfive,stg-syscon", NULL, 1, 0,
+ &phandle);
+ if (ret < 0) {
+ dev_err(data->dev, "Can't get stg cfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ data->stg_syscon = syscon_node_to_regmap(phandle.node);
+ if (IS_ERR(data->stg_syscon)) {
+ dev_err(data->dev, "fail to get regmap: %d\n", (int)PTR_ERR(data->stg_syscon));
+ return PTR_ERR(data->stg_syscon);
+ }
+
+ data->stg_usb_mode = phandle.args[0];
+
+ return 0;
+}
+
+static int cdns_starfive_probe(struct udevice *dev)
+{
+ struct cdns_starfive *data = dev_get_plat(dev);
+ enum usb_dr_mode dr_mode;
+ ofnode node;
+ int ret;
+
+ data->dev = dev;
+
+ ret = cdns_starfive_get_syscon(data);
+ if (ret)
+ return ret;
+
+ node = ofnode_by_compatible(dev_ofnode(dev), "cdns,usb3");
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "failed to get usb node\n");
+ return -ENODEV;
+ }
+
+ dr_mode = usb_get_dr_mode(node);
+
+ data->mode = dr_mode;
+ ret = cdns_clk_rst_init(data);
+ if (ret) {
+ dev_err(data->dev, "clk reset failed: %d\n", ret);
+ return ret;
+ }
+ cdns_mode_init(data, dr_mode);
+
+ return 0;
+}
+
+static int cdns_starfive_remove(struct udevice *dev)
+{
+ struct cdns_starfive *data = dev_get_plat(dev);
+
+ cdns_clk_rst_deinit(data);
+ return 0;
+}
+
+static const struct udevice_id cdns_starfive_of_match[] = {
+ { .compatible = "starfive,jh7110-usb", },
+ {},
+};
+
+U_BOOT_DRIVER(cdns_starfive) = {
+ .name = "cdns-starfive",
+ .id = UCLASS_NOP,
+ .of_match = cdns_starfive_of_match,
+ .bind = cdns3_bind,
+ .probe = cdns_starfive_probe,
+ .remove = cdns_starfive_remove,
+ .plat_auto = sizeof(struct cdns_starfive),
+ .flags = DM_FLAG_OS_PREPARE,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 4/9] usb: cdns: starfive: Add cdns USB driver
2024-08-29 1:30 ` [PATCH v4 4/9] usb: cdns: starfive: Add cdns USB driver Minda Chen
@ 2024-08-30 1:20 ` Marek Vasut
0 siblings, 0 replies; 21+ messages in thread
From: Marek Vasut @ 2024-08-30 1:20 UTC (permalink / raw)
To: Minda Chen, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow
On 8/29/24 3:30 AM, Minda Chen wrote:
> Add cdns USB3 wrapper driver.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> drivers/usb/cdns3/Kconfig | 7 ++
> drivers/usb/cdns3/Makefile | 2 +
> drivers/usb/cdns3/cdns3-starfive.c | 191 +++++++++++++++++++++++++++++
> 3 files changed, 200 insertions(+)
> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>
> diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
> index 35b61497d9..f8f363982b 100644
> --- a/drivers/usb/cdns3/Kconfig
> +++ b/drivers/usb/cdns3/Kconfig
> @@ -55,4 +55,11 @@ config USB_CDNS3_TI
> help
> Say 'Y' here if you are building for Texas Instruments
> platforms that contain Cadence USB3 controller core. E.g.: J721e.
> +
> +config USB_CDNS3_STARFIVE
> + tristate "Cadence USB3 support on Starfive platforms"
> + default USB_CDNS3
Should this be 'default y if SOMEPLATFORM' ?
[...]
> +static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode)
> +{
> + unsigned int strap, suspendm;
> +
> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
> + USB_MISC_CFG_MASK,
> + USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
> +
> + switch (mode) {
> + case USB_DR_MODE_HOST:
> + strap = USB_STRAP_HOST;
> + suspendm = USB_SUSPENDM_HOST;
> + break;
> +
> + case USB_DR_MODE_PERIPHERAL:
> + strap = USB_STRAP_DEVICE;
> + suspendm = 0;
> + break;
> + default:
> + return;
> + }
> +
> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
> + USB_STRAP_MASK, strap);
> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
> + USB_SUSPENDM_MASK, suspendm);
Are two consecutive writes to the same register mandatory here ?
> +}
[...]
> +static int cdns_starfive_probe(struct udevice *dev)
> +{
> + struct cdns_starfive *data = dev_get_plat(dev);
> + enum usb_dr_mode dr_mode;
> + ofnode node;
> + int ret;
> +
> + data->dev = dev;
> +
> + ret = cdns_starfive_get_syscon(data);
> + if (ret)
> + return ret;
> +
> + node = ofnode_by_compatible(dev_ofnode(dev), "cdns,usb3");
> + if (!ofnode_valid(node)) {
> + dev_err(dev, "failed to get usb node\n");
USB in capitals.
> + return -ENODEV;
> + }
> +
> + dr_mode = usb_get_dr_mode(node);
> +
> + data->mode = dr_mode;
> + ret = cdns_clk_rst_init(data);
> + if (ret) {
> + dev_err(data->dev, "clk reset failed: %d\n", ret);
> + return ret;
> + }
> + cdns_mode_init(data, dr_mode);
> +
> + return 0;
> +}
Looks pretty good, thanks .
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 5/9] spl: starfive: visionfive2: Disable USB overcurrent pin by default.
2024-08-29 1:30 [PATCH v4 0/9] Add Starfive JH7110 Cadence USB driver Minda Chen
` (3 preceding siblings ...)
2024-08-29 1:30 ` [PATCH v4 4/9] usb: cdns: starfive: Add cdns USB driver Minda Chen
@ 2024-08-29 1:30 ` Minda Chen
2024-10-26 16:23 ` E Shattow
2024-08-29 1:30 ` [PATCH v4 6/9] configs: starfive: Add visionfive2 cadence USB configuration Minda Chen
` (3 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Minda Chen @ 2024-08-29 1:30 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
For some JH7110 boards, USB host overcurent pin is not reserved,
To make USB host work, overcurrent pin must be disabled. So set the
pin default disabled in spl stage.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
arch/riscv/include/asm/arch-jh7110/gpio.h | 5 +++++
board/starfive/visionfive2/spl.c | 3 +++
2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h
index 90aa2f8a9e..be2a1e0d1c 100644
--- a/arch/riscv/include/asm/arch-jh7110/gpio.h
+++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
@@ -63,6 +63,11 @@ enum gpio_state {
GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+#define SYS_IOMUX_DIN_DISABLED(gpi)\
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
+ GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
+ ((0x1) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+
#define SYS_IOMUX_SET_DS(gpio, ds) \
clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index b794b73b6b..388a06e4d9 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -452,6 +452,9 @@ void board_init_f(ulong dummy)
JH7110_CLK_CPU_ROOT_MASK,
BIT(JH7110_CLK_CPU_ROOT_SHIFT));
+ /* Set USB overcurrent overflow pin disable */
+ SYS_IOMUX_DIN_DISABLED(2);
+
ret = spl_board_init_f();
if (ret) {
debug("spl_board_init_f init failed: %d\n", ret);
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 5/9] spl: starfive: visionfive2: Disable USB overcurrent pin by default.
2024-08-29 1:30 ` [PATCH v4 5/9] spl: starfive: visionfive2: Disable USB overcurrent pin by default Minda Chen
@ 2024-10-26 16:23 ` E Shattow
0 siblings, 0 replies; 21+ messages in thread
From: E Shattow @ 2024-10-26 16:23 UTC (permalink / raw)
To: Minda Chen
Cc: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon, u-boot, Heinrich Schuchardt, Simon Glass
On Wed, Aug 28, 2024 at 6:31 PM Minda Chen <minda.chen@starfivetech.com> wrote:
>
> For some JH7110 boards, USB host overcurent pin is not reserved,
> To make USB host work, overcurrent pin must be disabled. So set the
> pin default disabled in spl stage.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> arch/riscv/include/asm/arch-jh7110/gpio.h | 5 +++++
> board/starfive/visionfive2/spl.c | 3 +++
> 2 files changed, 8 insertions(+)
>
> diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h
> index 90aa2f8a9e..be2a1e0d1c 100644
> --- a/arch/riscv/include/asm/arch-jh7110/gpio.h
> +++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
> @@ -63,6 +63,11 @@ enum gpio_state {
> GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
> ((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
>
> +#define SYS_IOMUX_DIN_DISABLED(gpi)\
> + clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
> + GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
> + ((0x1) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
> +
> #define SYS_IOMUX_SET_DS(gpio, ds) \
> clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
> GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)
> diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
> index b794b73b6b..388a06e4d9 100644
> --- a/board/starfive/visionfive2/spl.c
> +++ b/board/starfive/visionfive2/spl.c
> @@ -452,6 +452,9 @@ void board_init_f(ulong dummy)
> JH7110_CLK_CPU_ROOT_MASK,
> BIT(JH7110_CLK_CPU_ROOT_SHIFT));
>
> + /* Set USB overcurrent overflow pin disable */
> + SYS_IOMUX_DIN_DISABLED(2);
> +
> ret = spl_board_init_f();
> if (ret) {
> debug("spl_board_init_f init failed: %d\n", ret);
> --
> 2.17.1
>
As tested, this patch is required for the operating system after
U-Boot to enable USB on at least Pine64 Star64 and Milk-V Mars CM Lite
even if U-Boot does not adopt the other patches in this series.
Can this be cherry-picked separate from the series?
Tested-by: E Shattow <lucent@gmail.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 6/9] configs: starfive: Add visionfive2 cadence USB configuration
2024-08-29 1:30 [PATCH v4 0/9] Add Starfive JH7110 Cadence USB driver Minda Chen
` (4 preceding siblings ...)
2024-08-29 1:30 ` [PATCH v4 5/9] spl: starfive: visionfive2: Disable USB overcurrent pin by default Minda Chen
@ 2024-08-29 1:30 ` Minda Chen
2024-08-29 1:30 ` [PATCH v4 7/9] dts: starfive: Add JH7110 Cadence USB dts node Minda Chen
` (2 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Minda Chen @ 2024-08-29 1:30 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add cadence USB confiuration.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
configs/starfive_visionfive2_defconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 174ac24dc7..35137eec59 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -69,6 +69,7 @@ CONFIG_SYS_EEPROM_SIZE=512
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_BIND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
@@ -112,6 +113,8 @@ CONFIG_NVME_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCIE_STARFIVE_JH7110=y
+CONFIG_PHY_STARFIVE_JH7110_PCIE=y
+CONFIG_PHY_STARFIVE_JH7110_USB2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
@@ -127,13 +130,19 @@ CONFIG_CADENCE_QSPI=y
CONFIG_SYSRESET=y
CONFIG_TIMER_EARLY=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_PCI=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+# CONFIG_USB_CDNS3_TI is not set
CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
# CONFIG_WATCHDOG is not set
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 7/9] dts: starfive: Add JH7110 Cadence USB dts node
2024-08-29 1:30 [PATCH v4 0/9] Add Starfive JH7110 Cadence USB driver Minda Chen
` (5 preceding siblings ...)
2024-08-29 1:30 ` [PATCH v4 6/9] configs: starfive: Add visionfive2 cadence USB configuration Minda Chen
@ 2024-08-29 1:30 ` Minda Chen
2024-08-29 4:47 ` Sumit Garg
2024-08-29 1:30 ` [PATCH v4 8/9] spl: starfive: star64: Setup USB fdt fixup function Minda Chen
2024-08-29 1:30 ` [PATCH v4 9/9] MAINTAINERS: Update Starfive visionfive2 maintain files Minda Chen
8 siblings, 1 reply; 21+ messages in thread
From: Minda Chen @ 2024-08-29 1:30 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add Jh7110 Cadence USB dts node, Visionfive2 default setting
is USB 2.0 device.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
.../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
arch/riscv/dts/jh7110.dtsi | 53 +++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index e11babc1cd..44785bbee3 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -378,3 +378,8 @@
};
};
};
+
+&usb_cdns3 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 2cdc683d49..7bf9b2a03a 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -371,6 +371,59 @@
status = "disabled";
};
+ usb0: usb@10100000 {
+ compatible = "starfive,jh7110-usb";
+ ranges = <0x0 0x0 0x10100000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ starfive,stg-syscon = <&stg_syscon 0x4>;
+ clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,
+ <&stgcrg JH7110_STGCLK_USB_STB>,
+ <&stgcrg JH7110_STGCLK_USB_APB>,
+ <&stgcrg JH7110_STGCLK_USB_AXI>,
+ <&stgcrg JH7110_STGCLK_USB_UTMI_APB>;
+ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
+ resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,
+ <&stgcrg JH7110_STGRST_USB_APB>,
+ <&stgcrg JH7110_STGRST_USB_AXI>,
+ <&stgcrg JH7110_STGRST_USB_UTMI_APB>;
+ reset-names = "pwrup", "apb", "axi", "utmi_apb";
+
+ usb_cdns3: usb@0 {
+ compatible = "cdns,usb3";
+ reg = <0x0 0x10000>,
+ <0x10000 0x10000>,
+ <0x20000 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <100>, <108>, <110>;
+ interrupt-names = "host", "peripheral", "otg";
+ phys = <&usbphy0>;
+ phy-names = "cdns3,usb2-phy";
+ };
+ };
+
+ usbphy0: phy@10200000 {
+ compatible = "starfive,jh7110-usb-phy";
+ reg = <0x0 0x10200000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+ <&stgcrg JH7110_STGCLK_USB_APP_125>;
+ clock-names = "125m", "app_125m";
+ starfive,sys-syscon = <&sys_syscon 0x18>;
+ #phy-cells = <0>;
+ };
+
+ pciephy0: phy@10210000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x0 0x10210000 0x0 0x10000>;
+ #phy-cells = <0>;
+ };
+
+ pciephy1: phy@10220000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x0 0x10220000 0x0 0x10000>;
+ #phy-cells = <0>;
+ };
+
stgcrg: clock-controller@10230000 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x10230000 0x0 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 7/9] dts: starfive: Add JH7110 Cadence USB dts node
2024-08-29 1:30 ` [PATCH v4 7/9] dts: starfive: Add JH7110 Cadence USB dts node Minda Chen
@ 2024-08-29 4:47 ` Sumit Garg
2024-08-29 4:57 ` E Shattow
0 siblings, 1 reply; 21+ messages in thread
From: Sumit Garg @ 2024-08-29 4:47 UTC (permalink / raw)
To: Minda Chen
Cc: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Mark Kettenis, Nishanth Menon,
u-boot, Heinrich Schuchardt, Simon Glass, E Shattow
Hi,
On Thu, 29 Aug 2024 at 07:01, Minda Chen <minda.chen@starfivetech.com> wrote:
>
> Add Jh7110 Cadence USB dts node, Visionfive2 default setting
> is USB 2.0 device.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> arch/riscv/dts/jh7110.dtsi | 53 +++++++++++++++++++
> 2 files changed, 58 insertions(+)
Can you try to evaluate if this SoC can support OF_UPSTREAM? I can see
corresponding DT sources well supported by dts/upstream. AFAICS, you
at least need to add a Makefile for RISC-V here:
dts/upstream/src/riscv/ for which you can reference
dts/upstream/src/arm64/Makefile.
This is not something to be considered as a blocker for this series
but kind of follow-up work.
-Sumit
>
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> index e11babc1cd..44785bbee3 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> @@ -378,3 +378,8 @@
> };
> };
> };
> +
> +&usb_cdns3 {
> + dr_mode = "peripheral";
> + status = "okay";
> +};
> diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> index 2cdc683d49..7bf9b2a03a 100644
> --- a/arch/riscv/dts/jh7110.dtsi
> +++ b/arch/riscv/dts/jh7110.dtsi
> @@ -371,6 +371,59 @@
> status = "disabled";
> };
>
> + usb0: usb@10100000 {
> + compatible = "starfive,jh7110-usb";
> + ranges = <0x0 0x0 0x10100000 0x100000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + starfive,stg-syscon = <&stg_syscon 0x4>;
> + clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,
> + <&stgcrg JH7110_STGCLK_USB_STB>,
> + <&stgcrg JH7110_STGCLK_USB_APB>,
> + <&stgcrg JH7110_STGCLK_USB_AXI>,
> + <&stgcrg JH7110_STGCLK_USB_UTMI_APB>;
> + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
> + resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,
> + <&stgcrg JH7110_STGRST_USB_APB>,
> + <&stgcrg JH7110_STGRST_USB_AXI>,
> + <&stgcrg JH7110_STGRST_USB_UTMI_APB>;
> + reset-names = "pwrup", "apb", "axi", "utmi_apb";
> +
> + usb_cdns3: usb@0 {
> + compatible = "cdns,usb3";
> + reg = <0x0 0x10000>,
> + <0x10000 0x10000>,
> + <0x20000 0x10000>;
> + reg-names = "otg", "xhci", "dev";
> + interrupts = <100>, <108>, <110>;
> + interrupt-names = "host", "peripheral", "otg";
> + phys = <&usbphy0>;
> + phy-names = "cdns3,usb2-phy";
> + };
> + };
> +
> + usbphy0: phy@10200000 {
> + compatible = "starfive,jh7110-usb-phy";
> + reg = <0x0 0x10200000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
> + <&stgcrg JH7110_STGCLK_USB_APP_125>;
> + clock-names = "125m", "app_125m";
> + starfive,sys-syscon = <&sys_syscon 0x18>;
> + #phy-cells = <0>;
> + };
> +
> + pciephy0: phy@10210000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x0 0x10210000 0x0 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> + pciephy1: phy@10220000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x0 0x10220000 0x0 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> stgcrg: clock-controller@10230000 {
> compatible = "starfive,jh7110-stgcrg";
> reg = <0x0 0x10230000 0x0 0x10000>;
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v4 7/9] dts: starfive: Add JH7110 Cadence USB dts node
2024-08-29 4:47 ` Sumit Garg
@ 2024-08-29 4:57 ` E Shattow
2024-08-30 5:52 ` Minda Chen
0 siblings, 1 reply; 21+ messages in thread
From: E Shattow @ 2024-08-29 4:57 UTC (permalink / raw)
To: Sumit Garg
Cc: Minda Chen, Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Mark Kettenis, Nishanth Menon,
u-boot, Heinrich Schuchardt, Simon Glass
On Wed, Aug 28, 2024 at 9:47 PM Sumit Garg <sumit.garg@linaro.org> wrote:
>
> Hi,
>
> On Thu, 29 Aug 2024 at 07:01, Minda Chen <minda.chen@starfivetech.com> wrote:
> >
> > Add Jh7110 Cadence USB dts node, Visionfive2 default setting
> > is USB 2.0 device.
> >
> > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > ---
> > .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> > arch/riscv/dts/jh7110.dtsi | 53 +++++++++++++++++++
> > 2 files changed, 58 insertions(+)
>
> Can you try to evaluate if this SoC can support OF_UPSTREAM? I can see
> corresponding DT sources well supported by dts/upstream. AFAICS, you
> at least need to add a Makefile for RISC-V here:
> dts/upstream/src/riscv/ for which you can reference
> dts/upstream/src/arm64/Makefile.
>
> This is not something to be considered as a blocker for this series
> but kind of follow-up work.
>
> -Sumit
>
> >
> > diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > index e11babc1cd..44785bbee3 100644
> > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > @@ -378,3 +378,8 @@
> > };
> > };
> > };
> > +
> > +&usb_cdns3 {
> > + dr_mode = "peripheral";
> > + status = "okay";
> > +};
> > diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> > index 2cdc683d49..7bf9b2a03a 100644
> > --- a/arch/riscv/dts/jh7110.dtsi
> > +++ b/arch/riscv/dts/jh7110.dtsi
> > @@ -371,6 +371,59 @@
> > status = "disabled";
> > };
> >
> > + usb0: usb@10100000 {
> > + compatible = "starfive,jh7110-usb";
> > + ranges = <0x0 0x0 0x10100000 0x100000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + starfive,stg-syscon = <&stg_syscon 0x4>;
> > + clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,
> > + <&stgcrg JH7110_STGCLK_USB_STB>,
> > + <&stgcrg JH7110_STGCLK_USB_APB>,
> > + <&stgcrg JH7110_STGCLK_USB_AXI>,
> > + <&stgcrg JH7110_STGCLK_USB_UTMI_APB>;
> > + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
> > + resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,
> > + <&stgcrg JH7110_STGRST_USB_APB>,
> > + <&stgcrg JH7110_STGRST_USB_AXI>,
> > + <&stgcrg JH7110_STGRST_USB_UTMI_APB>;
> > + reset-names = "pwrup", "apb", "axi", "utmi_apb";
> > +
> > + usb_cdns3: usb@0 {
> > + compatible = "cdns,usb3";
> > + reg = <0x0 0x10000>,
> > + <0x10000 0x10000>,
> > + <0x20000 0x10000>;
> > + reg-names = "otg", "xhci", "dev";
> > + interrupts = <100>, <108>, <110>;
> > + interrupt-names = "host", "peripheral", "otg";
> > + phys = <&usbphy0>;
> > + phy-names = "cdns3,usb2-phy";
> > + };
> > + };
> > +
> > + usbphy0: phy@10200000 {
> > + compatible = "starfive,jh7110-usb-phy";
> > + reg = <0x0 0x10200000 0x0 0x10000>;
> > + clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
> > + <&stgcrg JH7110_STGCLK_USB_APP_125>;
> > + clock-names = "125m", "app_125m";
> > + starfive,sys-syscon = <&sys_syscon 0x18>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + pciephy0: phy@10210000 {
> > + compatible = "starfive,jh7110-pcie-phy";
> > + reg = <0x0 0x10210000 0x0 0x10000>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + pciephy1: phy@10220000 {
> > + compatible = "starfive,jh7110-pcie-phy";
> > + reg = <0x0 0x10220000 0x0 0x10000>;
> > + #phy-cells = <0>;
> > + };
> > +
> > stgcrg: clock-controller@10230000 {
> > compatible = "starfive,jh7110-stgcrg";
> > reg = <0x0 0x10230000 0x0 0x10000>;
> > --
> > 2.17.1
> >
I note that Hal Feng saying earlier this week they would take on
OF_UPSTREAM of JH7110 boards:
https://lore.kernel.org/lkml/ZQ2PR01MB13073EF3BD7A64F2C098AA8FE6882@ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn/
It is a good time for this work to begin.
-E
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v4 7/9] dts: starfive: Add JH7110 Cadence USB dts node
2024-08-29 4:57 ` E Shattow
@ 2024-08-30 5:52 ` Minda Chen
0 siblings, 0 replies; 21+ messages in thread
From: Minda Chen @ 2024-08-30 5:52 UTC (permalink / raw)
To: E Shattow, Sumit Garg
Cc: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Mark Kettenis, Nishanth Menon,
u-boot@lists.denx.de, Heinrich Schuchardt, Simon Glass
>
> On Wed, Aug 28, 2024 at 9:47 PM Sumit Garg <sumit.garg@linaro.org> wrote:
> >
> > Hi,
> >
> > On Thu, 29 Aug 2024 at 07:01, Minda Chen <minda.chen@starfivetech.com>
> wrote:
> > >
> > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting is USB
> > > 2.0 device.
> > >
> > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > > ---
> > > .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> > > arch/riscv/dts/jh7110.dtsi | 53
> +++++++++++++++++++
> > > 2 files changed, 58 insertions(+)
> >
> > Can you try to evaluate if this SoC can support OF_UPSTREAM? I can see
> > corresponding DT sources well supported by dts/upstream. AFAICS, you
> > at least need to add a Makefile for RISC-V here:
> > dts/upstream/src/riscv/ for which you can reference
> > dts/upstream/src/arm64/Makefile.
> >
> > This is not something to be considered as a blocker for this series
> > but kind of follow-up work.
> >
> > -Sumit
> >
Yes. We will support OF_UPSTREAM .
Hal will do this job.
> > >
> > > diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > index e11babc1cd..44785bbee3 100644
> > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > @@ -378,3 +378,8 @@
> > > };
> > > };
> > > };
> > > +
> > > +&usb_cdns3 {
> > > + dr_mode = "peripheral";
> > > + status = "okay";
> > > +};
> > > diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> > > index 2cdc683d49..7bf9b2a03a 100644
> > > --- a/arch/riscv/dts/jh7110.dtsi
> > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > @@ -371,6 +371,59 @@
> > > status = "disabled";
> > > };
> > >
> > > + usb0: usb@10100000 {
> > > + compatible = "starfive,jh7110-usb";
> > > + ranges = <0x0 0x0 0x10100000 0x100000>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + starfive,stg-syscon = <&stg_syscon 0x4>;
> > > + clocks = <&stgcrg
> JH7110_STGCLK_USB_LPM>,
> > > + <&stgcrg
> JH7110_STGCLK_USB_STB>,
> > > + <&stgcrg
> JH7110_STGCLK_USB_APB>,
> > > + <&stgcrg
> JH7110_STGCLK_USB_AXI>,
> > > + <&stgcrg
> JH7110_STGCLK_USB_UTMI_APB>;
> > > + clock-names = "lpm", "stb", "apb", "axi",
> "utmi_apb";
> > > + resets = <&stgcrg
> JH7110_STGRST_USB_PWRUP>,
> > > + <&stgcrg
> JH7110_STGRST_USB_APB>,
> > > + <&stgcrg
> JH7110_STGRST_USB_AXI>,
> > > + <&stgcrg
> JH7110_STGRST_USB_UTMI_APB>;
> > > + reset-names = "pwrup", "apb", "axi",
> > > + "utmi_apb";
> > > +
> > > + usb_cdns3: usb@0 {
> > > + compatible = "cdns,usb3";
> > > + reg = <0x0 0x10000>,
> > > + <0x10000 0x10000>,
> > > + <0x20000 0x10000>;
> > > + reg-names = "otg", "xhci", "dev";
> > > + interrupts = <100>, <108>, <110>;
> > > + interrupt-names = "host",
> "peripheral", "otg";
> > > + phys = <&usbphy0>;
> > > + phy-names = "cdns3,usb2-phy";
> > > + };
> > > + };
> > > +
> > > + usbphy0: phy@10200000 {
> > > + compatible = "starfive,jh7110-usb-phy";
> > > + reg = <0x0 0x10200000 0x0 0x10000>;
> > > + clocks = <&syscrg
> JH7110_SYSCLK_USB_125M>,
> > > + <&stgcrg
> JH7110_STGCLK_USB_APP_125>;
> > > + clock-names = "125m", "app_125m";
> > > + starfive,sys-syscon = <&sys_syscon 0x18>;
> > > + #phy-cells = <0>;
> > > + };
> > > +
> > > + pciephy0: phy@10210000 {
> > > + compatible = "starfive,jh7110-pcie-phy";
> > > + reg = <0x0 0x10210000 0x0 0x10000>;
> > > + #phy-cells = <0>;
> > > + };
> > > +
> > > + pciephy1: phy@10220000 {
> > > + compatible = "starfive,jh7110-pcie-phy";
> > > + reg = <0x0 0x10220000 0x0 0x10000>;
> > > + #phy-cells = <0>;
> > > + };
> > > +
> > > stgcrg: clock-controller@10230000 {
> > > compatible = "starfive,jh7110-stgcrg";
> > > reg = <0x0 0x10230000 0x0 0x10000>;
> > > --
> > > 2.17.1
> > >
>
> I note that Hal Feng saying earlier this week they would take on OF_UPSTREAM
> of JH7110 boards:
> https://lore.kernel.org/lkml/ZQ2PR01MB13073EF3BD7A64F2C098AA8FE6882@
> ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn/
>
> It is a good time for this work to begin.
>
> -E
Yes， Hal Feng will do this job.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 8/9] spl: starfive: star64: Setup USB fdt fixup function
2024-08-29 1:30 [PATCH v4 0/9] Add Starfive JH7110 Cadence USB driver Minda Chen
` (6 preceding siblings ...)
2024-08-29 1:30 ` [PATCH v4 7/9] dts: starfive: Add JH7110 Cadence USB dts node Minda Chen
@ 2024-08-29 1:30 ` Minda Chen
2024-08-30 3:30 ` E Shattow
2024-08-29 1:30 ` [PATCH v4 9/9] MAINTAINERS: Update Starfive visionfive2 maintain files Minda Chen
8 siblings, 1 reply; 21+ messages in thread
From: Minda Chen @ 2024-08-29 1:30 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Setup star64 USB fdt fixup function. Set dr_mode to host,
and add vbus pin (GPIO25), and set USB 3.0 mode.
the functions can be used by other 7110 board like Milk-V
board.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
board/starfive/visionfive2/spl.c | 66 ++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 388a06e4d9..b3034b19a3 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -123,6 +123,69 @@ static const struct starfive_vf2_pro star64_pine64[] = {
"tx-internal-delay-ps", "300"},
};
+static void spl_fdt_fixup_usb_vbus_pin(void *fdt, int pin)
+{
+ int offset, pin_offset;
+
+ offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */
+ fdt_add_subnode(fdt, offset, "usb0-0");
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
+ "usb_pins", "/soc/pinctrl@13040000/usb0-0");
+ offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
+
+ /* usb_pins */
+ fdt_create_phandle(fdt, offset);
+ fdt_add_subnode(fdt, offset, "driver-vbus-pin");
+ offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
+ /* GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
+ fdt_setprop_u32(fdt, offset, "pinmux", (0xff07 << 16) | pin);
+ fdt_setprop_empty(fdt, offset, "bias-disable");
+ fdt_setprop_empty(fdt, offset, "input-disable");
+ fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
+ fdt_setprop_u32(fdt, offset, "slew-rate", 0);
+
+ offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
+ fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
+ pin_offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
+ fdt_setprop_u32(fdt, offset, "pinctrl-0",
+ fdt_get_phandle(fdt, pin_offset));
+}
+
+static void spl_fdt_fixup_usb_host(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*&usb_cdns3 */
+ fdt_setprop_string(fdt, offset, "dr_mode", "host");
+}
+
+static void spl_fdt_fixup_set_usb3(void *fdt)
+{
+ int offset, phy_offset;
+
+ /* disable pcie0 */
+ offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0 */
+ fdt_setprop_string(fdt, offset, "status", "disabled");
+
+ offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* &pciephy0 */
+ fdt_setprop_u32(fdt, offset, "starfive,sys-syscon", /* syscon */
+ fdt_get_phandle(fdt,
+ fdt_path_offset(fdt, "/soc/sys_syscon@13030000")));
+ fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18); /* append reg offset */
+ fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
+ fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/stg_syscon@10240000")));
+ /* append reg offset */
+ fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148);
+ fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4);
+
+ offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /* usb_cdns3 */
+ phy_offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* <&pciephy0> */
+ /* append <&pciephy0> */
+ fdt_appendprop_u32(fdt, offset, "phys", fdt_get_phandle(fdt, phy_offset));
+ fdt_setprop(fdt, offset, "phy-names", "cdns3,usb2-phy\0cdns3,usb3-phy",
+ sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
+}
+
void spl_fdt_fixup_mars(void *fdt)
{
static const char compat[] = "milkv,mars\0starfive,jh7110";
@@ -335,6 +398,9 @@ void spl_fdt_fixup_star64(void *fdt)
break;
}
}
+ spl_fdt_fixup_usb_host(fdt);
+ spl_fdt_fixup_usb_vbus_pin(fdt, 25);
+ spl_fdt_fixup_set_usb3(fdt);
}
void spl_perform_fixups(struct spl_image_info *spl_image)
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 8/9] spl: starfive: star64: Setup USB fdt fixup function
2024-08-29 1:30 ` [PATCH v4 8/9] spl: starfive: star64: Setup USB fdt fixup function Minda Chen
@ 2024-08-30 3:30 ` E Shattow
0 siblings, 0 replies; 21+ messages in thread
From: E Shattow @ 2024-08-30 3:30 UTC (permalink / raw)
To: Minda Chen
Cc: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon, u-boot, Heinrich Schuchardt, Simon Glass
Hi Minda,
On Wed, Aug 28, 2024 at 6:31 PM Minda Chen <minda.chen@starfivetech.com> wrote:
>
> Setup star64 USB fdt fixup function. Set dr_mode to host,
> and add vbus pin (GPIO25), and set USB 3.0 mode.
> the functions can be used by other 7110 board like Milk-V
> board.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> board/starfive/visionfive2/spl.c | 66 ++++++++++++++++++++++++++++++++
> 1 file changed, 66 insertions(+)
>
> diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
> index 388a06e4d9..b3034b19a3 100644
> --- a/board/starfive/visionfive2/spl.c
> +++ b/board/starfive/visionfive2/spl.c
> @@ -123,6 +123,69 @@ static const struct starfive_vf2_pro star64_pine64[] = {
> "tx-internal-delay-ps", "300"},
> };
>
> +static void spl_fdt_fixup_usb_vbus_pin(void *fdt, int pin)
> +{
> + int offset, pin_offset;
> +
> + offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */
> + fdt_add_subnode(fdt, offset, "usb0-0");
> + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
> + "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> + offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
> +
> + /* usb_pins */
> + fdt_create_phandle(fdt, offset);
> + fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> + offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> + /* GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
This comment may now be updated:
/* GPIOMUX(pin, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
Aside I am confused why we do not use the GPIOMUX macro directly here.
Can anyone say if that would be a problem to just use the macro
GPIOMUX what we are pretending to be here?
I think it will not be a problem here anymore when OF_UPSTREAM is
implemented to jh7110 boards in U-Boot so it is enough now to update
the comment about GPIOMUX.
> + fdt_setprop_u32(fdt, offset, "pinmux", (0xff07 << 16) | pin);
> + fdt_setprop_empty(fdt, offset, "bias-disable");
> + fdt_setprop_empty(fdt, offset, "input-disable");
> + fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> + fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> +
> + offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
> + fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> + pin_offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
> + fdt_setprop_u32(fdt, offset, "pinctrl-0",
> + fdt_get_phandle(fdt, pin_offset));
> +}
> +
> +static void spl_fdt_fixup_usb_host(void *fdt)
> +{
> + int offset;
> +
> + offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*&usb_cdns3 */
> + fdt_setprop_string(fdt, offset, "dr_mode", "host");
> +}
> +
> +static void spl_fdt_fixup_set_usb3(void *fdt)
> +{
> + int offset, phy_offset;
> +
> + /* disable pcie0 */
> + offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0 */
> + fdt_setprop_string(fdt, offset, "status", "disabled");
> +
> + offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* &pciephy0 */
> + fdt_setprop_u32(fdt, offset, "starfive,sys-syscon", /* syscon */
> + fdt_get_phandle(fdt,
> + fdt_path_offset(fdt, "/soc/sys_syscon@13030000")));
> + fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18); /* append reg offset */
> + fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
> + fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/stg_syscon@10240000")));
> + /* append reg offset */
> + fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148);
> + fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4);
> +
> + offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /* usb_cdns3 */
> + phy_offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* <&pciephy0> */
> + /* append <&pciephy0> */
> + fdt_appendprop_u32(fdt, offset, "phys", fdt_get_phandle(fdt, phy_offset));
> + fdt_setprop(fdt, offset, "phy-names", "cdns3,usb2-phy\0cdns3,usb3-phy",
> + sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
> +}
> +
Code readability can be better with fdt_appendprop_string helper. As:
fdt_setprop_string(fdt, offset, "phy-names", "cdns3,usb2-phy");
fdt_appendprop_string(fdt, offset, "phy-names", "cdns3,usb3-phy");
Some people prefer it to have "\0" and avoid the fdt_appendprop_string
helper. What you should do is not my choice here to make.
Anyway, and again, I think this will not be our problem after
OF_UPSTREAM is realized for JH7110 boards in U-Boot.
> void spl_fdt_fixup_mars(void *fdt)
> {
> static const char compat[] = "milkv,mars\0starfive,jh7110";
> @@ -335,6 +398,9 @@ void spl_fdt_fixup_star64(void *fdt)
> break;
> }
> }
> + spl_fdt_fixup_usb_host(fdt);
> + spl_fdt_fixup_usb_vbus_pin(fdt, 25);
> + spl_fdt_fixup_set_usb3(fdt);
> }
>
> void spl_perform_fixups(struct spl_image_info *spl_image)
> --
> 2.17.1
>
I have now tested Mars CM Lite:
+ spl_fdt_fixup_usb_host(fdt);
+ spl_fdt_fixup_usb_vbus_pin(fdt, 25);
added to the Milk-V Mars CM fix-up routine: in U-Boot there is both
working USB and PCIe. I would note also an error for PCIe in Linux if
continuing from U-Boot with the fdt of U-Boot into Grub2, then Linux:
Loading Linux 6.11-rc4-riscv64 ...
Loading initial ramdisk ...
[ 11.718961] pcie-starfive 2b000000.pcie: error -ENODEV: failed to
get valid pcie domain
[ 11.727238] cadence-qspi 13010000.spi: couldn't determine
trigger-address
[ 11.730479] pcie-starfive 2c000000.pcie: error -ENODEV: failed to
get valid pcie domain
[ 11.734112] cadence-qspi 13010000.spi: Cannot get mandatory OF
data.
Gave up waiting for suspend/resume device
This is only a problem when I force `fdtfile` path to be not found,
and U-Boot gives the internal fdt to the next boot software in
sequence (here this is Grub2, and then Debian Linux).
For now, Minda, the error with Mars CM Lite and U-Boot internal fdt
into 6.11-rc4 Linux causing PCIe to fail is something I consider a
regression if we do enable for Mars CM and Mars CM Lite. It is good
enough in this series with only the JH7110 boards that you have
available for testing.
Reviewed-by: E Shattow <lucent@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 9/9] MAINTAINERS: Update Starfive visionfive2 maintain files.
2024-08-29 1:30 [PATCH v4 0/9] Add Starfive JH7110 Cadence USB driver Minda Chen
` (7 preceding siblings ...)
2024-08-29 1:30 ` [PATCH v4 8/9] spl: starfive: star64: Setup USB fdt fixup function Minda Chen
@ 2024-08-29 1:30 ` Minda Chen
8 siblings, 0 replies; 21+ messages in thread
From: Minda Chen @ 2024-08-29 1:30 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Rick Chen, Leo,
Neil Armstrong, Alexey Romanov, Sumit Garg, Mark Kettenis,
Nishanth Menon
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add USB related files to Starfive visionfive2 MAINTAINERS.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Marek Vasut <marex@denx.de>
---
board/starfive/visionfive2/MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
index d7f638f9b4..1faf83f581 100644
--- a/board/starfive/visionfive2/MAINTAINERS
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -6,3 +6,5 @@ F: board/starfive/visionfive2/
F: include/configs/starfive-visionfive2.h
F: configs/starfive_visionfive2_defconfig
F: drivers/pci/pcie_starfive_jh7110.c
+F: drivers/phy/starfive/
+F: drivers/usb/cdns3/cdns3-starfive.c
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread