[PATCH 0/9] add support for Enclustra Mercury AA1 SoMs

[PATCH 0/9] add support for Enclustra Mercury AA1 SoMs

[Lothar Rubusch]

Introduce the support for three variants of Enclustra's Intel Mercury AA1 (with
Intel Arria10) SoMs and additional configs. This is supposed to be the first
step to upstream several of Enclustras SoC FPGA Modules. There are still things
to be modified. So, this is supposed to start the discussion and also to
clarify some of my open issues. I verified boot on SD card and emmc is booting,
as also checkpatch is mostly fine and I hope the git comments are reasonable.

Open Issues I still have:

- checkpatch.pl: CONFIG options for env settings in
  include/configs/socfpga_mercury_aa1.h show up as error at checkpatch.pl.
Additionally an env file as demo is provided, along with instructions.
Although, I noticed, when providing a uboot.env file as binary, this replaces
the default (socfpga) environment. Is there a way to just append some settings
by a compiled uboot.env? As this happens to be, when declared in
include/configs. Also other boards (still) used to have settings in board
header files in include/configs. So, do I need to remove CONFIG_ entries in
this file, or may it be acceptable?

- MAC address from secure eeprom: The implementation does not bring in a new
  driver. It uses actually the ATSHA204a driver following DM and already
existing in uboot. Function is verified. Is this usage ok?

- Si53338 driver: This is a new clock generator driver with partly generated
  code. To be honest, I'm not sure if this should be even be upstreamed. Fact
is, the SoMs work w/o this driver. Optional features may need that driver on
the system later. It's a nice to have, but also quite specific.

- DT: We don't have upstream kernel DT fragments, so that's also why we still
  use the classic location here. The bigger problem is, I have 3x (slightly)
different AA1 modules. All can be combined with three different baseboards.
Most of those combinations support several bootmodes (SD, eMMC, QSPI) with yet
another .dtsi fragment. What is the best way to deal with this situation? For
sure I don't like to bring in all combinations as particular new DT setups.
Hence, the current approach is to have a top level "enclustra-aa1.dts"
including particular .dtsi elements. In combination then using .dtbos and a
boot.scr approach. I feel a fit image can be part of the solution, but I'm
unsure. I'm unsure if this is part of the BSP later, say a yocto setup, or part
of the bootloader. Is it enough to just provide the .dtsi elementst or also an
.its file for a demo? In the documentation .rst file currently I refere to the
described. Do I need to improve this setup, and what would be the desired
approach for this situation?

- uImage: uImage was the classic approach at Enclustra. Anyway this goes into
  the same direction as above: A more advanced approach would involve a fit
image, as e.g. the "image.ub" Xilinx is doing. But is this needed? Doesn't it
also depend on the specific customer and project? Hence, a similar question, is
there anything missing? What would be additionally needed? Or, is the current
setup is enough?

- Maintainer: checkpatch.pl complains about a missing maintainer entry for the
  new board. So, I registered myself, since I have access to this hardware.
Unsure here, please let me know how to procede.

Lothar Rubusch (9):
  doc: board: enclustra: add Enclustra Intel AA1 SoM
  ARM: dts: socfpga: add Enclustra Intel AA1
  ARM: socfpga: add Enclustra AA1 SoM support
  ARM: socfpga: add Enclustra AA1 extra env settings
  ARM: socfpga: add Enclustra AA1 demo env files
  ARM: socfpga: add Enclustra AA1 boot scripts
  ARM: socfpga: AA1: support MAC from secure eeprom
  ARM: socfpga: add si5338 clock generator support
  ARM: socfpga: make AA1 use si5338 clock gen

 arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi    |  14 +
 arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi    |  14 +
 arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi    |  15 +
 arch/arm/dts/Makefile                         |   2 +
 arch/arm/dts/enclustra-aa1.dts                |  32 ++
 .../dts/socfpga_arria10_mercury_aa1_handoff.h | 307 ++++++++++++
 .../dts/socfpga_enclustra_mercury_aa1.dtsi    | 179 +++++++
 ...cfpga_enclustra_mercury_aa1_qspi_boot.dtsi |  18 +
 ...fpga_enclustra_mercury_aa1_sdmmc_boot.dtsi |  18 +
 .../dts/socfpga_enclustra_mercury_pe1.dtsi    |   7 +
 .../dts/socfpga_enclustra_mercury_pe3.dtsi    |   8 +
 .../dts/socfpga_enclustra_mercury_st1.dtsi    |   8 +
 arch/arm/mach-socfpga/Kconfig                 |   9 +
 board/enclustra/bootscripts/qspi-aa1.cmd      |  12 +
 board/enclustra/bootscripts/sd-aa1.cmd        |  10 +
 board/enclustra/common/Kconfig                |  24 +
 board/enclustra/common/Makefile               |   7 +
 board/enclustra/common/enclustra_mac.h        |  48 ++
 board/enclustra/common/mac_atsha204.c         |  97 ++++
 board/enclustra/common/mac_common.c           |  54 +++
 board/enclustra/common/mac_ds28.c             |  88 ++++
 board/enclustra/mercury_aa1/Kconfig           |  15 +
 board/enclustra/mercury_aa1/MAINTAINERS       |  10 +
 board/enclustra/mercury_aa1/Makefile          |   4 +
 board/enclustra/mercury_aa1/bitstream.its     |  32 ++
 board/enclustra/mercury_aa1/mercury_aa1.c     | 199 ++++++++
 board/enclustra/mercury_aa1/mercury_aa1.env   |  65 +++
 .../socfpga_enclustra_mercury_aa1_defconfig   |  81 ++++
 doc/board/enclustra/index.rst                 |   9 +
 doc/board/enclustra/mercury-aa1.rst           | 209 +++++++++
 doc/board/index.rst                           |   1 +
 drivers/clk/Kconfig                           |   1 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/skyworks/Kconfig                  |  10 +
 drivers/clk/skyworks/Makefile                 |   3 +
 drivers/clk/skyworks/Si5338-RevB-Registers.h  | 441 ++++++++++++++++++
 drivers/clk/skyworks/si5338_clkgen.c          | 177 +++++++
 drivers/clk/skyworks/si5338_clkgen.h          |  18 +
 drivers/misc/Kconfig                          |   2 +-
 include/configs/socfpga_mercury_aa1.h         |  68 +++
 40 files changed, 2316 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi
 create mode 100644 arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi
 create mode 100644 arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi
 create mode 100644 arch/arm/dts/enclustra-aa1.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_pe1.dtsi
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_pe3.dtsi
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_st1.dtsi
 create mode 100644 board/enclustra/bootscripts/qspi-aa1.cmd
 create mode 100644 board/enclustra/bootscripts/sd-aa1.cmd
 create mode 100644 board/enclustra/common/Kconfig
 create mode 100644 board/enclustra/common/Makefile
 create mode 100644 board/enclustra/common/enclustra_mac.h
 create mode 100644 board/enclustra/common/mac_atsha204.c
 create mode 100644 board/enclustra/common/mac_common.c
 create mode 100644 board/enclustra/common/mac_ds28.c
 create mode 100644 board/enclustra/mercury_aa1/Kconfig
 create mode 100644 board/enclustra/mercury_aa1/MAINTAINERS
 create mode 100644 board/enclustra/mercury_aa1/Makefile
 create mode 100644 board/enclustra/mercury_aa1/bitstream.its
 create mode 100644 board/enclustra/mercury_aa1/mercury_aa1.c
 create mode 100644 board/enclustra/mercury_aa1/mercury_aa1.env
 create mode 100644 configs/socfpga_enclustra_mercury_aa1_defconfig
 create mode 100644 doc/board/enclustra/index.rst
 create mode 100644 doc/board/enclustra/mercury-aa1.rst
 create mode 100644 drivers/clk/skyworks/Kconfig
 create mode 100644 drivers/clk/skyworks/Makefile
 create mode 100644 drivers/clk/skyworks/Si5338-RevB-Registers.h
 create mode 100644 drivers/clk/skyworks/si5338_clkgen.c
 create mode 100644 drivers/clk/skyworks/si5338_clkgen.h
 create mode 100644 include/configs/socfpga_mercury_aa1.h

-- 
2.25.1

[PATCH 1/9] doc: board: enclustra: add Enclustra Intel AA1 SoM

[Lothar Rubusch]

Start documentation section for Enclustra. Cover Enclustra Intel SoMs and
related carrier board setups.

- Mercury AA1 (Arria10)

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 doc/board/enclustra/index.rst       |   9 ++
 doc/board/enclustra/mercury-aa1.rst | 209 ++++++++++++++++++++++++++++
 doc/board/index.rst                 |   1 +
 3 files changed, 219 insertions(+)
 create mode 100644 doc/board/enclustra/index.rst
 create mode 100644 doc/board/enclustra/mercury-aa1.rst

diff --git a/doc/board/enclustra/index.rst b/doc/board/enclustra/index.rst
new file mode 100644
index 0000000000..00727d0861
--- /dev/null
+++ b/doc/board/enclustra/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Enclustra
+=========
+
+.. toctree::
+   :maxdepth: 2
+
+   mercury-aa1
diff --git a/doc/board/enclustra/mercury-aa1.rst b/doc/board/enclustra/mercury-aa1.rst
new file mode 100644
index 0000000000..0331756045
--- /dev/null
+++ b/doc/board/enclustra/mercury-aa1.rst
@@ -0,0 +1,209 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Lothar Rubusch <l.rubusch@gmail.com>
+
+Mercury AA1 Module (Arria1 10)
+==============================
+
+- SoM: https://www.enclustra.com/en/products/system-on-chip-modules/mercury-aa1/
+- Carrier board Mercury+ ST1: https://www.enclustra.com/en/products/base-boards/mercury-st1/
+- Carrier board Mercury+ PE1: https://www.enclustra.com/en/products/base-boards/mercury-pe1-200-300-400/
+- Carrier board Mercury+ PE3: https://www.enclustra.com/en/products/base-boards/mercury-pe3/
+
+There are slightly different variants of the AA1 SoM, going by the identifier.
+
+- Me-aa1-270-2i2-d11e-nfx3
+- Me-aa1-270-3e4-d11e-nfx3
+- Me-aa1-480-2i3-d12e-nfx3
+
+The u-boot setup is specific to a quartus design. Generate handoff files from
+the design. Pass them to a python script to produce a handoff.h file. This is
+needed as input for building the device-tree for u-boot. Eventually, building
+the final u-boot depends on the particular Quartus design, the particular
+carrier board, the selected boot media and boot mode.
+
+Enclustra provides reference design examples which can be built with yocto
+using their meta-layer.
+
+- Reference Design AA1 on ST1: https://github.com/enclustra/Mercury_AA1_ST1_Reference_Design
+- Reference Design AA1 on PE1: https://github.com/enclustra/Mercury_AA1_PE1_Reference_Design
+- Reference Design AA1 on PE3: https://github.com/enclustra/Mercury_AA1_PE3_Reference_Design
+- Yocto meta-layer: https://github.com/enclustra/meta-enclustra-socfpga
+
+Quick Start
+-----------
+
+- Setup and build a Quartus design project
+- Obtain the hps.xml file from the Quartus design project
+- Generate the handoff.h file for u-boot
+- Adjust the device-tree file according to your setup
+- Build u-boot
+- Flash u-boot
+
+Build U-Boot
+------------
+
+The Quartus design produces a design specific ``hps.xml``, an ``emif.xml`` and
+a corresponding ``id`` file contained in a folder ``handoff``.
+
+Generate the handoff.h file for u-boot, from a provided ``hps.xml`` using the
+script provided in u-boot.
+
+.. code-block:: bash
+
+    $ arch/arm/mach-socfpga/qts-filter-a10.sh <where you saved it>/hps.xml arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
+
+Adjust the device-tree file according to your setup. Follow the comments in the
+file.
+
+.. code-block:: bash
+
+    $ vi ./arch/arm/dts/enclustra-aa1.dts
+
+Build u-boot. Source your favorite toolchain for ARM first.
+
+.. code-block:: bash
+
+    $ make socfpga_enclustra_mercury_aa1_defconfig
+    $ make -j8
+
+Setup and compile a boot script as needed. Depending on the boot-mode select
+``sd-aa1.cmd`` for SD/eMMC, or ``qspi-aa1.cmd`` for QSPI flash. Also,
+optionally prepare an environment file. Examples of boot command files and
+environment files are provided.
+
+.. code-block:: bash
+
+    $ ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Uboot mmc startscript" -d board/enclustra/bootscripts/sd-aa1.cmd boot.scr
+    $ ./tools/mkenvimage -s 0x80000 -o uboot.env board/enclustra/mercury_aa1/mercury_aa1.env
+
+Device-Tree setup
+-----------------
+
+The basic u-boot device-tree fragments are provided here. The handoff tools
+will generate further u-boot device-tree fragments. The various .dtsi files
+then need to be included in a top-level .dts file.
+
+Flash the U-Boot Binary to a Micro SD Card
+------------------------------------------
+
+The following example describes the full approach. Prepare a micro SD card with
+three partitions as follows:
+
+* ``type=c, start=2048, size=409600``
+* ``type=a2, start=411648, size=14336``
+* ``type=83, start=425984, size=1619968``
+
+.. code-block:: bash
+
+    $ sudo fdisk /dev/sda
+        n,p,1,2048,+20M
+        t,1,c
+        n,p,2,409600,+1M
+        t,2,a2
+        n,p,3,425984,<REST>
+        t,3,83
+        w
+
+Note: The ``bitstream.itb`` is needed to start the bootloader. A kernel
+``devicetree.dtb`` is needed to boot into the system. Both are not part of
+u-boot, but are be provided through yocto using Enclustra's meta-layer.
+
+Generally the bitstream files depend on the logic design, but the meta-layer
+provides a demo design. Copy the ``bitstream.periph.rbf`` and
+``bitstream.core.rbf`` from your design or yocto's deploy folder. The
+``bitstream.its`` in board/enclustra then is used to bundle them.
+
+ .. code-block:: bash
+
+    $ cp bitstream.periph.rbf ./board/enclustra/mercury_aa1/
+    $ cp bitstream.core.rbf ./board/enclustra/mercury_aa1/
+    $ ./tools/mkimage -E -f ./board/enclustra/mercury_aa1/bitstream.its bitstream.itb
+
+Format the SD card, and copy the following artifacts to the mounted boot
+partition, e.g. on /dev/sda (check before).
+
+ .. code-block:: bash
+
+    $ mkfs.vfat -n boot /dev/sda1
+    $ mount /dev/sda1 /media/boot
+    $ cp ./{boot.scr,u-boot.img,uboot.env,bitstream.itb,Image,devicetree.dtb} /media/boot/
+    $ umount /dev/sda1
+
+Flash the SPL directly.
+
+ .. code-block:: bash
+
+    $ dd if=./spl/u-boot-splx4.sfp of=/dev/sda2 conv=fdatasync bs=4k status=progress
+
+Format and flash a rootfs from image or files to the third partition.
+
+ .. code-block:: bash
+
+    $ mkfs.ext4 -L rootfs /dev/sda3
+    $ mount /dev/sda3 /media/rootfs
+    $ tar xf ./rootfs.tar -C /media/rootfs
+    $ umount /dev/sda3
+
+Boot Media
+----------
+
+Alternative boot media are possible as officially documented by Enclustra.
+
+* Micro-SD card
+* eMMC
+* QSPI
+
+NB: eMMC and QSPI can be flashed from off the u-boot shell. Usually after
+flashing, the coorect boot mode needs to be set by a BSEL switch. Approaches
+are described consistently in the offical Enclustra documentation according to
+their releases mentioned as links.
+
+Before turning on the setup, make sure to have the correct voltage configured
+at the carrier board, using the jumpers on the voltage pin header. Also make
+sure to have switched to the correct boot media using typically some dip
+switches to be found on the carrier board.
+
+Boot Log
+--------
+
+The demo shows booting a AA1 + ST1 setup and stopping at the u-boot shell.
+
+Here is the console output::
+
+  U-Boot SPL 2024.10-rc4-00416-gf0b9c383e6c3 (Sep 08 2024 - 14:03:59 +0000)
+  FPGA: Checking FPGA configuration setting ...
+  FPGA: Start to program peripheral/full bitstream ...
+  FPGA: Early Release Succeeded.
+  FPGA: Checking FPGA configuration setting ...
+  FPGA: Start to program peripheral/full bitstream ...
+  FPGA: Early Release Succeeded.
+
+  U-Boot SPL 2024.10-rc4-00416-gf0b9c383e6c3 (Sep 08 2024 - 14:03:59 +0000)
+  DDRCAL: Success
+  DDRCAL: Scrubbing ECC RAM (2048 MiB).
+  DDRCAL: Scrubbing ECC RAM done.
+  FPGA: Checking FPGA configuration setting ...
+  FPGA: Start to program core bitstream ...
+  Full Configuration Succeeded.
+  FPGA: Enter user mode.
+  Trying to boot from MMC1
+
+
+  U-Boot 2024.10-rc4-00416-gf0b9c383e6c3 (Sep 08 2024 - 14:03:59 +0000)socfpga_arria10
+
+  CPU:   Altera SoCFPGA Arria 10
+  BOOT:  SD/MMC External Transceiver (1.8V)
+  Model: Enclustra Mercury+ AA1
+  DRAM:  2 GiB
+  Core:  80 devices, 20 uclasses, devicetree: separate
+  MMC:   dwmmc0@ff808000: 0
+  Loading Environment from FAT... OK
+  In:    serial
+  Out:   serial
+  Err:   serial
+  Model: Enclustra Mercury+ AA1
+  ethaddr set to 20:B0:F7:06:0D:BE
+  eth1addr set to 20:B0:F7:06:0D:BF
+  Net:   eth0: ethernet@ff800000
+  =>
+
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 417c128c7a..42244a689b 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -24,6 +24,7 @@ Board-specific doc
    congatec/index
    coreboot/index
    emulation/index
+   enclustra/index
    gateworks/index
    google/index
    highbank/index
-- 
2.25.1

[PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Lothar Rubusch]

Introduce device-tree files for Enclustra Intel AA1 SoMs and related
support.

- Mercury AA1

The setup depends on a selected boot mode. Various fragments for SD/MMC
and QSPI flash boot are provided.

In combination, the following Enclustra carrier boards are supported:

- ST1
- PE1
- PE3

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi    |  14 +
 arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi    |  14 +
 arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi    |  15 +
 arch/arm/dts/Makefile                         |   2 +
 arch/arm/dts/enclustra-aa1.dts                |  32 ++
 .../dts/socfpga_arria10_mercury_aa1_handoff.h | 307 ++++++++++++++++++
 .../dts/socfpga_enclustra_mercury_aa1.dtsi    | 179 ++++++++++
 ...cfpga_enclustra_mercury_aa1_qspi_boot.dtsi |  18 +
 ...fpga_enclustra_mercury_aa1_sdmmc_boot.dtsi |  18 +
 .../dts/socfpga_enclustra_mercury_pe1.dtsi    |   7 +
 .../dts/socfpga_enclustra_mercury_pe3.dtsi    |   8 +
 .../dts/socfpga_enclustra_mercury_st1.dtsi    |   8 +
 12 files changed, 622 insertions(+)
 create mode 100644 arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi
 create mode 100644 arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi
 create mode 100644 arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi
 create mode 100644 arch/arm/dts/enclustra-aa1.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_pe1.dtsi
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_pe3.dtsi
 create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_st1.dtsi

diff --git a/arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi b/arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi
new file mode 100644
index 0000000000..75550a77c9
--- /dev/null
+++ b/arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/ {
+	model = "Enclustra Mercury+ AA1";
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x80000000>; /* 2GB */
+	};
+};
diff --git a/arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi b/arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi
new file mode 100644
index 0000000000..75550a77c9
--- /dev/null
+++ b/arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/ {
+	model = "Enclustra Mercury+ AA1";
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x80000000>; /* 2GB */
+	};
+};
diff --git a/arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi b/arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi
new file mode 100644
index 0000000000..9ba850a84b
--- /dev/null
+++ b/arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/ {
+	model = "Enclustra Mercury+ AA1";
+
+	/* The module is equipped with 4Gbyte RAM but U-Boot limits the size to 2 Gbyte */
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x80000000>; /* 2GB */
+	};
+};
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 64007a20e6..2fcc4512ef 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -414,6 +414,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_n5x_socdk.dtb				\
 	socfpga_stratix10_socdk.dtb
 
+dtb-$(CONFIG_TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1) += enclustra-aa1.dtb
+
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb	\
 	dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
diff --git a/arch/arm/dts/enclustra-aa1.dts b/arch/arm/dts/enclustra-aa1.dts
new file mode 100644
index 0000000000..09df8c846a
--- /dev/null
+++ b/arch/arm/dts/enclustra-aa1.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+/* arria10 family - NB: keep the order of the includes */
+#include "socfpga_arria10.dtsi"
+#include "socfpga_arria10-u-boot.dtsi"
+
+/* The generated handoff.h goes here */
+#include "socfpga_arria10_mercury_aa1_handoff.h"
+
+/* Generic arria10 glue */
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_enclustra_mercury_aa1.dtsi"
+
+/* Select the boot mode: sd/mmc or qspi */
+//#include "socfpga_enclustra_mercury_aa1_qspi_boot.dtsi"
+#include "socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi"
+
+/* Select the carrier board */
+//#include "socfpga_enclustra_mercury_st1.dtsi"
+#include "socfpga_enclustra_mercury_pe1.dtsi"
+//#include "socfpga_enclustra_mercury_pe3.dtsi"
+
+/* Select the type of AA1 module */
+//#include "ME-AA1-270-2I2-D11E-NFX3.dtsi"
+//#include "ME-AA1-270-3E4-D11E-NFX3.dtsi"
+#include "ME-AA1-480-2I3-D12E-NFX3.dtsi"
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h b/arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
new file mode 100644
index 0000000000..46e7e3c18b
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
@@ -0,0 +1,307 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Intel Arria 10 SoCFPGA configuration
+ *
+ * Copyright (C) 2024 Enclustra GmbH
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 60000000
+#define EMAC0_CLK_HZ 250000000
+#define EMAC1_CLK_HZ 250000000
+#define EMAC2_CLK_HZ 250000000
+#define EOSC1_CLK_HZ 33333000
+#define F2H_FREE_CLK_HZ 200000000
+#define H2F_USER0_CLK_HZ 100000000
+#define H2F_USER1_CLK_HZ 50000000
+#define L3_MAIN_FREE_CLK_HZ 400000000
+#define SDMMC_CLK_HZ 200000000
+#define TPIU_CLK_HZ 100000000
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 9
+#define MAINPLLGRP_CNTR7CLK_CNT 19
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 39
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 1
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 32
+#define MAINPLLGRP_VCO1_NUMER 1980
+#define PERPLLGRP_CNTR2CLK_CNT 7
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 19
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 499
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 0
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 32
+#define PERPLLGRP_VCO1_NUMER 1980
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 4
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+	(ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+	(ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CONFIG_IO_10_INPUT_BUF_EN 1
+#define CONFIG_IO_10_PD_DRV_STRG 10
+#define CONFIG_IO_10_PD_SLW_RT 1
+#define CONFIG_IO_10_PU_DRV_STRG 8
+#define CONFIG_IO_10_PU_SLW_RT 1
+#define CONFIG_IO_10_RTRIM 1
+#define CONFIG_IO_10_WK_PU_EN 0
+#define CONFIG_IO_11_INPUT_BUF_EN 1
+#define CONFIG_IO_11_PD_DRV_STRG 10
+#define CONFIG_IO_11_PD_SLW_RT 1
+#define CONFIG_IO_11_PU_DRV_STRG 8
+#define CONFIG_IO_11_PU_SLW_RT 1
+#define CONFIG_IO_11_RTRIM 1
+#define CONFIG_IO_11_WK_PU_EN 0
+#define CONFIG_IO_12_INPUT_BUF_EN 1
+#define CONFIG_IO_12_PD_DRV_STRG 10
+#define CONFIG_IO_12_PD_SLW_RT 1
+#define CONFIG_IO_12_PU_DRV_STRG 8
+#define CONFIG_IO_12_PU_SLW_RT 1
+#define CONFIG_IO_12_RTRIM 1
+#define CONFIG_IO_12_WK_PU_EN 0
+#define CONFIG_IO_13_INPUT_BUF_EN 1
+#define CONFIG_IO_13_PD_DRV_STRG 10
+#define CONFIG_IO_13_PD_SLW_RT 1
+#define CONFIG_IO_13_PU_DRV_STRG 8
+#define CONFIG_IO_13_PU_SLW_RT 1
+#define CONFIG_IO_13_RTRIM 1
+#define CONFIG_IO_13_WK_PU_EN 0
+#define CONFIG_IO_14_INPUT_BUF_EN 1
+#define CONFIG_IO_14_PD_DRV_STRG 10
+#define CONFIG_IO_14_PD_SLW_RT 1
+#define CONFIG_IO_14_PU_DRV_STRG 8
+#define CONFIG_IO_14_PU_SLW_RT 1
+#define CONFIG_IO_14_RTRIM 1
+#define CONFIG_IO_14_WK_PU_EN 0
+#define CONFIG_IO_15_INPUT_BUF_EN 1
+#define CONFIG_IO_15_PD_DRV_STRG 10
+#define CONFIG_IO_15_PD_SLW_RT 1
+#define CONFIG_IO_15_PU_DRV_STRG 8
+#define CONFIG_IO_15_PU_SLW_RT 1
+#define CONFIG_IO_15_RTRIM 1
+#define CONFIG_IO_15_WK_PU_EN 0
+#define CONFIG_IO_16_INPUT_BUF_EN 0
+#define CONFIG_IO_16_PD_DRV_STRG 10
+#define CONFIG_IO_16_PD_SLW_RT 1
+#define CONFIG_IO_16_PU_DRV_STRG 8
+#define CONFIG_IO_16_PU_SLW_RT 1
+#define CONFIG_IO_16_RTRIM 1
+#define CONFIG_IO_16_WK_PU_EN 0
+#define CONFIG_IO_17_INPUT_BUF_EN 1
+#define CONFIG_IO_17_PD_DRV_STRG 10
+#define CONFIG_IO_17_PD_SLW_RT 1
+#define CONFIG_IO_17_PU_DRV_STRG 8
+#define CONFIG_IO_17_PU_SLW_RT 1
+#define CONFIG_IO_17_RTRIM 1
+#define CONFIG_IO_17_WK_PU_EN 0
+#define CONFIG_IO_1_INPUT_BUF_EN 1
+#define CONFIG_IO_1_PD_DRV_STRG 10
+#define CONFIG_IO_1_PD_SLW_RT 0
+#define CONFIG_IO_1_PU_DRV_STRG 8
+#define CONFIG_IO_1_PU_SLW_RT 0
+#define CONFIG_IO_1_RTRIM 1
+#define CONFIG_IO_1_WK_PU_EN 1
+#define CONFIG_IO_2_INPUT_BUF_EN 1
+#define CONFIG_IO_2_PD_DRV_STRG 10
+#define CONFIG_IO_2_PD_SLW_RT 0
+#define CONFIG_IO_2_PU_DRV_STRG 8
+#define CONFIG_IO_2_PU_SLW_RT 0
+#define CONFIG_IO_2_RTRIM 1
+#define CONFIG_IO_2_WK_PU_EN 1
+#define CONFIG_IO_3_INPUT_BUF_EN 1
+#define CONFIG_IO_3_PD_DRV_STRG 10
+#define CONFIG_IO_3_PD_SLW_RT 0
+#define CONFIG_IO_3_PU_DRV_STRG 8
+#define CONFIG_IO_3_PU_SLW_RT 0
+#define CONFIG_IO_3_RTRIM 1
+#define CONFIG_IO_3_WK_PU_EN 1
+#define CONFIG_IO_4_INPUT_BUF_EN 1
+#define CONFIG_IO_4_PD_DRV_STRG 10
+#define CONFIG_IO_4_PD_SLW_RT 1
+#define CONFIG_IO_4_PU_DRV_STRG 8
+#define CONFIG_IO_4_PU_SLW_RT 1
+#define CONFIG_IO_4_RTRIM 1
+#define CONFIG_IO_4_WK_PU_EN 0
+#define CONFIG_IO_5_INPUT_BUF_EN 1
+#define CONFIG_IO_5_PD_DRV_STRG 10
+#define CONFIG_IO_5_PD_SLW_RT 1
+#define CONFIG_IO_5_PU_DRV_STRG 8
+#define CONFIG_IO_5_PU_SLW_RT 1
+#define CONFIG_IO_5_RTRIM 1
+#define CONFIG_IO_5_WK_PU_EN 0
+#define CONFIG_IO_6_INPUT_BUF_EN 0
+#define CONFIG_IO_6_PD_DRV_STRG 10
+#define CONFIG_IO_6_PD_SLW_RT 1
+#define CONFIG_IO_6_PU_DRV_STRG 8
+#define CONFIG_IO_6_PU_SLW_RT 1
+#define CONFIG_IO_6_RTRIM 1
+#define CONFIG_IO_6_WK_PU_EN 0
+#define CONFIG_IO_7_INPUT_BUF_EN 1
+#define CONFIG_IO_7_PD_DRV_STRG 10
+#define CONFIG_IO_7_PD_SLW_RT 1
+#define CONFIG_IO_7_PU_DRV_STRG 8
+#define CONFIG_IO_7_PU_SLW_RT 1
+#define CONFIG_IO_7_RTRIM 1
+#define CONFIG_IO_7_WK_PU_EN 0
+#define CONFIG_IO_8_INPUT_BUF_EN 1
+#define CONFIG_IO_8_PD_DRV_STRG 10
+#define CONFIG_IO_8_PD_SLW_RT 1
+#define CONFIG_IO_8_PU_DRV_STRG 8
+#define CONFIG_IO_8_PU_SLW_RT 1
+#define CONFIG_IO_8_RTRIM 1
+#define CONFIG_IO_8_WK_PU_EN 0
+#define CONFIG_IO_9_INPUT_BUF_EN 1
+#define CONFIG_IO_9_PD_DRV_STRG 10
+#define CONFIG_IO_9_PD_SLW_RT 1
+#define CONFIG_IO_9_PU_DRV_STRG 8
+#define CONFIG_IO_9_PU_SLW_RT 1
+#define CONFIG_IO_9_RTRIM 1
+#define CONFIG_IO_9_WK_PU_EN 0
+#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define PINMUX_DEDICATED_IO_10_SEL 15
+#define PINMUX_DEDICATED_IO_11_SEL 15
+#define PINMUX_DEDICATED_IO_12_SEL 15
+#define PINMUX_DEDICATED_IO_13_SEL 15
+#define PINMUX_DEDICATED_IO_14_SEL 15
+#define PINMUX_DEDICATED_IO_15_SEL 15
+#define PINMUX_DEDICATED_IO_16_SEL 13
+#define PINMUX_DEDICATED_IO_17_SEL 13
+#define PINMUX_DEDICATED_IO_4_SEL 8
+#define PINMUX_DEDICATED_IO_5_SEL 8
+#define PINMUX_DEDICATED_IO_6_SEL 8
+#define PINMUX_DEDICATED_IO_7_SEL 8
+#define PINMUX_DEDICATED_IO_8_SEL 8
+#define PINMUX_DEDICATED_IO_9_SEL 8
+#define PINMUX_I2C0_USEFPGA_SEL 0
+#define PINMUX_I2C1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
+#define PINMUX_NAND_USEFPGA_SEL 0
+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
+#define PINMUX_QSPI_USEFPGA_SEL 0
+#define PINMUX_RGMII0_USEFPGA_SEL 0
+#define PINMUX_RGMII1_USEFPGA_SEL 0
+#define PINMUX_RGMII2_USEFPGA_SEL 0
+#define PINMUX_SDMMC_USEFPGA_SEL 0
+#define PINMUX_SHARED_IO_Q1_10_SEL 8
+#define PINMUX_SHARED_IO_Q1_11_SEL 8
+#define PINMUX_SHARED_IO_Q1_12_SEL 8
+#define PINMUX_SHARED_IO_Q1_1_SEL 8
+#define PINMUX_SHARED_IO_Q1_2_SEL 8
+#define PINMUX_SHARED_IO_Q1_3_SEL 8
+#define PINMUX_SHARED_IO_Q1_4_SEL 8
+#define PINMUX_SHARED_IO_Q1_5_SEL 8
+#define PINMUX_SHARED_IO_Q1_6_SEL 8
+#define PINMUX_SHARED_IO_Q1_7_SEL 8
+#define PINMUX_SHARED_IO_Q1_8_SEL 8
+#define PINMUX_SHARED_IO_Q1_9_SEL 8
+#define PINMUX_SHARED_IO_Q2_10_SEL 4
+#define PINMUX_SHARED_IO_Q2_11_SEL 4
+#define PINMUX_SHARED_IO_Q2_12_SEL 4
+#define PINMUX_SHARED_IO_Q2_1_SEL 4
+#define PINMUX_SHARED_IO_Q2_2_SEL 4
+#define PINMUX_SHARED_IO_Q2_3_SEL 4
+#define PINMUX_SHARED_IO_Q2_4_SEL 4
+#define PINMUX_SHARED_IO_Q2_5_SEL 4
+#define PINMUX_SHARED_IO_Q2_6_SEL 4
+#define PINMUX_SHARED_IO_Q2_7_SEL 4
+#define PINMUX_SHARED_IO_Q2_8_SEL 4
+#define PINMUX_SHARED_IO_Q2_9_SEL 4
+#define PINMUX_SHARED_IO_Q3_10_SEL 15
+#define PINMUX_SHARED_IO_Q3_11_SEL 1
+#define PINMUX_SHARED_IO_Q3_12_SEL 1
+#define PINMUX_SHARED_IO_Q3_1_SEL 15
+#define PINMUX_SHARED_IO_Q3_2_SEL 15
+#define PINMUX_SHARED_IO_Q3_3_SEL 15
+#define PINMUX_SHARED_IO_Q3_4_SEL 15
+#define PINMUX_SHARED_IO_Q3_5_SEL 15
+#define PINMUX_SHARED_IO_Q3_6_SEL 15
+#define PINMUX_SHARED_IO_Q3_7_SEL 0
+#define PINMUX_SHARED_IO_Q3_8_SEL 0
+#define PINMUX_SHARED_IO_Q3_9_SEL 15
+#define PINMUX_SHARED_IO_Q4_10_SEL 15
+#define PINMUX_SHARED_IO_Q4_11_SEL 15
+#define PINMUX_SHARED_IO_Q4_12_SEL 15
+#define PINMUX_SHARED_IO_Q4_1_SEL 10
+#define PINMUX_SHARED_IO_Q4_2_SEL 10
+#define PINMUX_SHARED_IO_Q4_3_SEL 10
+#define PINMUX_SHARED_IO_Q4_4_SEL 10
+#define PINMUX_SHARED_IO_Q4_5_SEL 10
+#define PINMUX_SHARED_IO_Q4_6_SEL 10
+#define PINMUX_SHARED_IO_Q4_7_SEL 15
+#define PINMUX_SHARED_IO_Q4_8_SEL 15
+#define PINMUX_SHARED_IO_Q4_9_SEL 15
+#define PINMUX_SPIM0_USEFPGA_SEL 0
+#define PINMUX_SPIM1_USEFPGA_SEL 0
+#define PINMUX_SPIS0_USEFPGA_SEL 0
+#define PINMUX_SPIS1_USEFPGA_SEL 0
+#define PINMUX_UART0_USEFPGA_SEL 0
+#define PINMUX_UART1_USEFPGA_SEL 0
+#define PINMUX_USB0_USEFPGA_SEL 0
+#define PINMUX_USB1_USEFPGA_SEL 0
+
+/* Bridge Configuration */
+#define F2H_AXI_SLAVE 0
+#define F2SDRAM0_AXI_SLAVE 0
+#define F2SDRAM1_AXI_SLAVE 0
+#define F2SDRAM2_AXI_SLAVE 0
+#define H2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 1
+
+/* Voltage Select for Config IO */
+#define CONFIG_IO_BANK_VSEL \
+	(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+	(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+
+/* Macro for Config IO bit mapping */
+#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0x7) << 19) | \
+	((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
+	((NAME ## _WK_PU_EN & 0x1) << 16) | \
+	((NAME ## _PU_SLW_RT & 0x1) << 13) | \
+	((NAME ## _PU_DRV_STRG & 0x1f) << 8) | \
+	((NAME ## _PD_SLW_RT & 0x1) << 5) | \
+	(NAME ## _PD_DRV_STRG & 0x1f))
+
+#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
diff --git a/arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi
new file mode 100644
index 0000000000..c3d468b01e
--- /dev/null
+++ b/arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/ {
+	compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+	aliases {
+		serial0 = &uart1;
+		ethernet0 = &gmac0;
+		spi0 = &qspi;
+		i2c0 = &i2c1;
+		i2c1 = &i2c0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	/* define i2c label to be used in baseboard dtsi */
+	soc {
+		i2c_encl: i2c@ffc02300 {
+		};
+		i2c_encl_fpga: i2c@ffc02200 {
+		};
+	};
+
+};
+
+&osc1 {
+	clock-frequency = <33330000>;
+};
+
+&l4_main_clk {
+	bootph-all;
+};
+
+&qspi_clk {
+	bootph-all;
+};
+
+&main_sdmmc_clk {
+	bootph-all;
+};
+
+&sdmmc_clk {
+	bootph-all;
+};
+
+&sdmmc_free_clk {
+	bootph-all;
+};
+
+&peri_sdmmc_clk {
+	bootph-all;
+};
+
+&uart1 {
+	bootph-all;
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c_encl {
+	i2c-sda-hold-time-ns = <300>;
+	status = "okay";
+
+	clock-frequency = <100000>;
+
+	atsha204a: atsha204a@64 {
+		status = "okay";
+		compatible = "atmel,atsha204a";
+		reg = <0x64>;
+	};
+};
+
+&i2c_encl_fpga {
+	i2c-sda-hold-time-ns = <300>;
+	status = "disabled";
+};
+
+&mmc {
+	bootph-all;
+	status = "okay";
+	cap-sd-highspeed;
+	broken-cd;
+	bus-width = <4>;
+};
+
+&eccmgr {
+	sdmmca-ecc@ff8c2c00 {
+		compatible = "altr,socfpga-sdmmc-ecc";
+		reg = <0xff8c2c00 0x400>;
+		altr,ecc-parent = <&mmc>;
+		interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+					 <47 IRQ_TYPE_LEVEL_HIGH>,
+					 <16 IRQ_TYPE_LEVEL_HIGH>,
+					 <48 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&qspi {
+	bootph-all;
+	status = "okay";
+
+	flash0: s25fl512s@0 {
+		bootph-all;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25fl512s", "jedec,spi-nor";
+		reg = <0>;
+
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+		spi-max-frequency = <10000000>;
+
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		cdns,page-size = <256>;
+		cdns,block-size = <16>;
+		cdns,tshsl-ns = <200>;
+		cdns,tsd2d-ns = <255>;
+		cdns,tchsh-ns = <20>;
+		cdns,tslch-ns = <20>;
+	};
+};
+
+&watchdog1 {
+	bootph-all;
+	status = "disabled";
+};
+
+&gmac0 {
+	status = "okay";
+	/delete-property/ mac-address;
+	phy-mode = "rgmii";
+	phy-addr = <3>;
+	phy-handle = <&phy3>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		phy3: ethernet-phy@3 {
+			reg = <3>;
+
+			/* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
+			rxc-skew-ps = <1680>;
+			rxd0-skew-ps = <420>;
+			rxd1-skew-ps = <420>;
+			rxd2-skew-ps = <420>;
+			rxd3-skew-ps = <420>;
+			rxdv-skew-ps = <420>;
+
+			/* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/
+			txc-skew-ps = <1860>;
+			txd0-skew-ps = <0>;
+			txd1-skew-ps = <0>;
+			txd2-skew-ps = <0>;
+			txd3-skew-ps = <0>;
+			txen-skew-ps = <0>;
+		};
+	};
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
diff --git a/arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi
new file mode 100644
index 0000000000..f51dc7c55f
--- /dev/null
+++ b/arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/ {
+	fs_loader0: fs-loader {
+		bootph-all;
+		compatible = "u-boot,fs-loader";
+		sfconfig = <0 0 50000000 3>;
+	};
+};
+
+&fpga_mgr {
+	bootph-all;
+	firmware-loader = <&fs_loader0>;
+	altr,bitstream = "300000";
+};
diff --git a/arch/arm/dts/socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi
new file mode 100644
index 0000000000..052726e318
--- /dev/null
+++ b/arch/arm/dts/socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/ {
+	fs_loader0: fs-loader {
+		bootph-all;
+		compatible = "u-boot,fs-loader";
+		phandlepart = <&mmc 1>;
+	};
+};
+
+&fpga_mgr {
+	bootph-all;
+	firmware-loader = <&fs_loader0>;
+	altr,bitstream = "bitstream.itb";
+};
diff --git a/arch/arm/dts/socfpga_enclustra_mercury_pe1.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_pe1.dtsi
new file mode 100644
index 0000000000..e39474f443
--- /dev/null
+++ b/arch/arm/dts/socfpga_enclustra_mercury_pe1.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/ {
+};
diff --git a/arch/arm/dts/socfpga_enclustra_mercury_pe3.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_pe3.dtsi
new file mode 100644
index 0000000000..85d5050bb1
--- /dev/null
+++ b/arch/arm/dts/socfpga_enclustra_mercury_pe3.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl_fpga {
+	status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_enclustra_mercury_st1.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_st1.dtsi
new file mode 100644
index 0000000000..85d5050bb1
--- /dev/null
+++ b/arch/arm/dts/socfpga_enclustra_mercury_st1.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl_fpga {
+	status = "okay";
+};
-- 
2.25.1

[PATCH 3/9] ARM: socfpga: add Enclustra AA1 SoM support

[Lothar Rubusch]

Introduce initial support for the Enclustra SoMs:

- Mercury AA1

Cover general board files for SD/MMC and QSPI boot modes. Integrate the
boards to kconfig. All build variants will depend on Quartus handoff
files, thus they depend on the particular Quartus design. The approach is
covered in the according documentation part.

Additionally add configuration for SD/MMC boot and QSPI bootmodes. Register
additional targets in kconfig.

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 arch/arm/mach-socfpga/Kconfig                 |   9 +
 board/enclustra/common/Kconfig                |   1 +
 board/enclustra/common/Makefile               |   4 +
 board/enclustra/mercury_aa1/Kconfig           |  15 ++
 board/enclustra/mercury_aa1/MAINTAINERS       |  10 +
 board/enclustra/mercury_aa1/Makefile          |   4 +
 board/enclustra/mercury_aa1/bitstream.its     |  32 +++
 board/enclustra/mercury_aa1/mercury_aa1.c     | 185 ++++++++++++++++++
 .../socfpga_enclustra_mercury_aa1_defconfig   |  78 ++++++++
 include/configs/socfpga_mercury_aa1.h         |  33 ++++
 10 files changed, 371 insertions(+)
 create mode 100644 board/enclustra/common/Kconfig
 create mode 100644 board/enclustra/common/Makefile
 create mode 100644 board/enclustra/mercury_aa1/Kconfig
 create mode 100644 board/enclustra/mercury_aa1/MAINTAINERS
 create mode 100644 board/enclustra/mercury_aa1/Makefile
 create mode 100644 board/enclustra/mercury_aa1/bitstream.its
 create mode 100644 board/enclustra/mercury_aa1/mercury_aa1.c
 create mode 100644 configs/socfpga_enclustra_mercury_aa1_defconfig
 create mode 100644 include/configs/socfpga_mercury_aa1.h

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6b6a162f56..d42e7817be 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -221,6 +221,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
 	bool "Terasic SoCkit (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
+	bool "Enclustra Mercury+ AA1"
+	select TARGET_SOCFPGA_ARRIA10
+
 endchoice
 
 config SYS_BOARD
@@ -244,6 +248,7 @@ config SYS_BOARD
 	default "sr1500" if TARGET_SOCFPGA_SR1500
 	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 	default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+	default "mercury_aa1" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
 
 config SYS_VENDOR
 	default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK
@@ -264,6 +269,7 @@ config SYS_VENDOR
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
 	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "enclustra" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
 
 config SYS_SOC
 	default "socfpga"
@@ -289,5 +295,8 @@ config SYS_CONFIG_NAME
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+	default "socfpga_mercury_aa1" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
+
+source "board/enclustra/common/Kconfig"
 
 endif
diff --git a/board/enclustra/common/Kconfig b/board/enclustra/common/Kconfig
new file mode 100644
index 0000000000..51169bada3
--- /dev/null
+++ b/board/enclustra/common/Kconfig
@@ -0,0 +1 @@
+source "board/enclustra/mercury_aa1/Kconfig"
diff --git a/board/enclustra/common/Makefile b/board/enclustra/common/Makefile
new file mode 100644
index 0000000000..16c8531d74
--- /dev/null
+++ b/board/enclustra/common/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2024 Enclustra GmbH
+
+# Common for several Enclustra modules
diff --git a/board/enclustra/mercury_aa1/Kconfig b/board/enclustra/mercury_aa1/Kconfig
new file mode 100644
index 0000000000..40c7cb2687
--- /dev/null
+++ b/board/enclustra/mercury_aa1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "mercury_aa1"
+
+config SYS_VENDOR
+	default "enclustra"
+
+config SYS_CONFIG_NAME
+	default "socfpga_mercury_aa1"
+
+endif
diff --git a/board/enclustra/mercury_aa1/MAINTAINERS b/board/enclustra/mercury_aa1/MAINTAINERS
new file mode 100644
index 0000000000..11b7058d61
--- /dev/null
+++ b/board/enclustra/mercury_aa1/MAINTAINERS
@@ -0,0 +1,10 @@
+Enclustra Mercury+ AA1
+M:	Lothar Rubusch <l.rubusch@gmail.com>
+S:	Maintained
+F:	board/enclustra/mercury_aa1/
+F:	board/enclustra/common/
+F:	include/configs/socfpga_mercury_aa1.h
+F:	configs/socfpga_enclustra_mercury_aa1_defconfig
+F:	arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi
+F:	arch/arm/dts/socfpga_enclustra_mercury_aa1_emmc_boot.dtsi
+F:	arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi
diff --git a/board/enclustra/mercury_aa1/Makefile b/board/enclustra/mercury_aa1/Makefile
new file mode 100644
index 0000000000..d830170dea
--- /dev/null
+++ b/board/enclustra/mercury_aa1/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2024 Enclustra GmbH
+
+obj-y += mercury_aa1.o
diff --git a/board/enclustra/mercury_aa1/bitstream.its b/board/enclustra/mercury_aa1/bitstream.its
new file mode 100644
index 0000000000..d16e4598de
--- /dev/null
+++ b/board/enclustra/mercury_aa1/bitstream.its
@@ -0,0 +1,32 @@
+/dts-v1/;
+
+/ {
+	description = "FIT image with FPGA bistream";
+	#address-cells = <1>;
+
+	images {
+		fpga-periph-1 {
+			description = "FPGA peripheral bitstream";
+			data = /incbin/("bitstream.periph.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+
+		fpga-core-1 {
+			description = "FPGA core bitstream";
+			data = /incbin/("bitstream.core.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+		config-1 {
+			description = "Boot with FPGA early IO release config";
+			fpga = "fpga-periph-1", "fpga-core-1";
+		};
+	};
+};
diff --git a/board/enclustra/mercury_aa1/mercury_aa1.c b/board/enclustra/mercury_aa1/mercury_aa1.c
new file mode 100644
index 0000000000..7de9b287d9
--- /dev/null
+++ b/board/enclustra/mercury_aa1/mercury_aa1.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Enclustra GmbH
+ * <info@enclustra.com>
+ */
+
+#include <command.h>
+#include <env.h>
+#include <init.h>
+#include <dm/uclass.h>
+#include <asm-generic/gpio.h>
+#include <asm/io.h>
+
+/* Pin muxing */
+#if !defined(CONFIG_SPL_BUILD)
+
+#define ALTERA_NONE 0
+#define ALTERA_MMC 1
+#define ALTERA_QSPI 2
+#define ALTERA_EMMC 3
+#define MMC_CLK_DIV 0x9
+#define QSPI_CLK_DIV 0x384
+#define ALTERA_PINMUX_OFFS 0xffd07200
+#define ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE 0xFFD04078
+
+static int altera_current_storage = ALTERA_NONE;
+
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+
+static void set_mux_mmc(void)
+{
+	u32 pinmux_arr[] = {0x0c, 0x8,  // IO4 connected to SDMMC
+			0x10, 0x8,	// IO5
+			0x14, 0x8,	// IO6
+			0x18, 0x8,	// IO7
+			0x1c, 0x8,	// IO8
+			0x20, 0x8,	// IO9
+			0x24, 0xf,	// IO10 connected to GPIO
+			0x28, 0xf,	// IO11
+			0x2c, 0xf,	// IO12
+			0x30, 0xf,	// IO13
+			0x34, 0xf,	// IO14
+			0x38, 0xf};	// IO15
+	u32 len, i, offset, value;
+
+	len = sizeof(pinmux_arr) / sizeof(u32);
+	for (i = 0; i < len; i += 2) {
+		offset = pinmux_arr[i];
+		value = pinmux_arr[i + 1];
+		writel(value, ALTERA_PINMUX_OFFS + offset);
+	}
+}
+
+static void set_mux_emmc(void)
+{
+	u32 pinmux_arr[] = {0x0c, 0x8,  // IO4
+		0x10, 0x8,	// IO5
+		0x14, 0x8,	// IO6
+		0x18, 0x8,	// IO7
+		0x1c, 0x8,	// IO8
+		0x20, 0x8,	// IO9
+		0x24, 0xf,	// IO10
+		0x28, 0xf,	// IO11
+		0x2c, 0x8,	// IO12
+		0x30, 0x8,	// IO13
+		0x34, 0x8,	// IO14
+		0x38, 0x8};	// IO15
+	u32 len, i, offset, value;
+
+	len = sizeof(pinmux_arr) / sizeof(u32);
+	for (i = 0; i < len; i += 2) {
+		offset = pinmux_arr[i];
+		value = pinmux_arr[i + 1];
+		writel(value, ALTERA_PINMUX_OFFS + offset);
+	}
+}
+
+static void set_mux_qspi(void)
+{
+	u32 pinmux_arr[] = {0x0c, 0x4,  // IO4 connected to QSPI
+		0x10, 0x4,	// IO5
+		0x14, 0x4,	// IO6
+		0x18, 0x4,	// IO7
+		0x1c, 0x4,	// IO8
+		0x20, 0x4,	// IO9
+		0x24, 0xf,	// IO10
+		0x28, 0xf,	// IO11
+		0x2c, 0xf,	// IO12
+		0x30, 0xf,	// IO13
+		0x34, 0xf,	// IO14
+		0x38, 0xf};	// IO15
+	u32 len, i, offset, value;
+
+	len = sizeof(pinmux_arr) / sizeof(u32);
+	for (i = 0; i < len; i += 2) {
+		offset = pinmux_arr[i];
+		value = pinmux_arr[i + 1];
+		writel(value, ALTERA_PINMUX_OFFS + offset);
+	}
+}
+
+void altera_set_storage(int store)
+{
+	unsigned int gpio_flash_sel;
+	unsigned int gpio_flash_oe;
+
+	if (store == altera_current_storage)
+		return;
+
+	if (gpio_lookup_name("portb5", NULL, NULL, &gpio_flash_oe)) {
+		printf("ERROR: GPIO not found\n");
+		return;
+	}
+
+	if (gpio_request(gpio_flash_oe, "flash_oe")) {
+		printf("ERROR: GPIO request failed\n");
+		return;
+	}
+
+	if (gpio_lookup_name("portc6", NULL, NULL, &gpio_flash_sel)) {
+		printf("ERROR: GPIO not found\n");
+		return;
+	}
+
+	if (gpio_request(gpio_flash_sel, "flash_sel")) {
+		printf("ERROR: GPIO request failed\n");
+		return;
+	}
+
+	switch (store) {
+	case ALTERA_MMC:
+		set_mux_mmc();
+		gpio_direction_output(gpio_flash_sel, 0);
+		gpio_direction_output(gpio_flash_oe, 0);
+		altera_current_storage = ALTERA_MMC;
+		writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
+		break;
+	case ALTERA_EMMC:
+		set_mux_emmc();
+		gpio_direction_output(gpio_flash_sel, 1);
+		gpio_direction_output(gpio_flash_oe, 1);
+		altera_current_storage = ALTERA_EMMC;
+		writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
+		break;
+	case ALTERA_QSPI:
+		set_mux_qspi();
+		gpio_direction_output(gpio_flash_sel, 1);
+		gpio_direction_output(gpio_flash_oe, 0);
+		altera_current_storage = ALTERA_QSPI;
+		writel(QSPI_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
+		break;
+	default:
+		altera_current_storage = ALTERA_NONE;
+		break;
+	}
+
+	gpio_free(gpio_flash_sel);
+	gpio_free(gpio_flash_oe);
+}
+
+int altera_set_storage_cmd(struct cmd_tbl *cmdtp, int flag,
+			   int argc, char * const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	if (!strcmp(argv[1], "MMC"))
+		altera_set_storage(ALTERA_MMC);
+	else if (!strcmp(argv[1], "QSPI"))
+		altera_set_storage(ALTERA_QSPI);
+	else if (!strcmp(argv[1], "EMMC"))
+		altera_set_storage(ALTERA_EMMC);
+	else
+		return CMD_RET_USAGE;
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(altera_set_storage, 2, 0, altera_set_storage_cmd,
+	   "Set non volatile memory access",
+	   "<MMC|QSPI|EMMC> - Set access for the selected memory device");
+
+#endif
diff --git a/configs/socfpga_enclustra_mercury_aa1_defconfig b/configs/socfpga_enclustra_mercury_aa1_defconfig
new file mode 100644
index 0000000000..b475bd916d
--- /dev/null
+++ b/configs/socfpga_enclustra_mercury_aa1_defconfig
@@ -0,0 +1,78 @@
+CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000
+CONFIG_SF_DEFAULT_SPEED=10000000
+CONFIG_ENV_SIZE=0x80000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="enclustra-aa1"
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0xffe2b000
+CONFIG_TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1=y
+CONFIG_IDENT_STRING="socfpga_arria10"
+CONFIG_SPL_FS_FAT=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_DEFAULT_FDT_FILE="system.dtb"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CLOCKS=y
+CONFIG_SPL_PAD_TO=0x40000
+CONFIG_SPL_NO_BSS_LIMIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x15000
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
diff --git a/include/configs/socfpga_mercury_aa1.h b/include/configs/socfpga_mercury_aa1.h
new file mode 100644
index 0000000000..a5b63336e8
--- /dev/null
+++ b/include/configs/socfpga_mercury_aa1.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 Enclustra GmbH
+ * <info@enclustra.com>
+ */
+
+#ifndef __CONFIG_SOCFGPA_MERCURY_AA1_H__
+#define __CONFIG_SOCFGPA_MERCURY_AA1_H__
+
+#include <asm/arch/base_addr_a10.h>
+
+/*
+ * U-Boot general configurations
+ */
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE		0x80000000
+
+/*
+ * Serial / UART configurations
+ */
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFGPA_MERCURY_AA1_H__ */
-- 
2.25.1

[PATCH 4/9] ARM: socfpga: add Enclustra AA1 extra env settings

[Lothar Rubusch]

Add command files for boot scripts and initial boot environment.

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 include/configs/socfpga_mercury_aa1.h | 35 +++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/include/configs/socfpga_mercury_aa1.h b/include/configs/socfpga_mercury_aa1.h
index a5b63336e8..4b047e11a7 100644
--- a/include/configs/socfpga_mercury_aa1.h
+++ b/include/configs/socfpga_mercury_aa1.h
@@ -21,6 +21,41 @@
  */
 #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
 
+/* U-Boot environment */
+#define CFG_EXTRA_ENV_SETTINGS						\
+	"bitstream_size=0xD00000\0"					\
+	"bootargs=earlycon console=ttyS0,115200 rw rootwait root=/dev/mmcblk0p3\0" \
+	"bootargs_qspi=earlycon console=ttyS0,115200 rw root=/dev/ram0\0" \
+	"bootm_size=0x0a000000\0"					\
+	"env_size=0x80000\0"						\
+	"fdt_addr_r=0x10000000\0"					\
+	"fdtfile=system.dtb\0"						\
+	"fdtload=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${bootdir}/${fdtfile}; load ${devtype} ${devnum}:${distro_bootpart} ${fdto_addr_r} ${bootdir}/${fdtofile}; fdt addr $fdt_addr_r; fdt resize 8192; fdt apply $fdto_addr_r\0" \
+	"fdtload_qspi=sf probe; sf read ${fdt_addr_r} ${qspi_offset_addr_devicetree} ${fdt_size}; sf read ${fdto_addr_r} ${qspi_offset_addr_dtoverlay} ${fdto_size}; fdt addr ${fdt_addr_r}; fdt resize 8192; fdt apply ${fdto_addr_r}\0" \
+	"fdto_addr_r=0x100c0000\0"					\
+	"fdtofile=socfpga_enclustra_mercury_XXX_overlay.dtbo\0"		\
+	"fdto_size=0x40000\0"						\
+	"fdt_size=0x40000\0"						\
+	"kernel_addr_r=0x11000000\0"					\
+	"kernel_size=0x1000000\0"					\
+	"qspiboot=source ${scriptaddr}\0"				\
+	"qspiload=setenv bootargs ${bootargs_qspi}; sf probe; sf read ${scriptaddr} ${qspi_offset_addr_boot_script} ${scriptsize}\0" \
+	"qspi_offset_addr_bitstream=0x300000\0"				\
+	"qspi_offset_addr_boot_script=0x200000\0"			\
+	"qspi_offset_addr_devicetree=0x280000\0"			\
+	"qspi_offset_addr_dtoverlay=0x2c0000\0"				\
+	"qspi_offset_addr_kernel=0x1000000\0"				\
+	"qspi_offset_addr_rootfs=0x2000000\0"				\
+	"qspi_offset_addr_spl=0x0\0"					\
+	"qspi_offset_addr_uboot=0x100000\0"				\
+	"qspi_offset_addr_uboot_env=0x180000\0"				\
+	"rootfs_addr_r=0x12000000\0"					\
+	"rootfs_size=0x2000000\0"					\
+	"scriptaddr=0x10800000\0"					\
+	"scriptsize=0x80000\0"						\
+	"spl_size=0x100000\0"						\
+	"uboot_size=0x80000\0"
+
 /*
  * L4 OSC1 Timer 0
  */
-- 
2.25.1

[PATCH 5/9] ARM: socfpga: add Enclustra AA1 demo env files

[Lothar Rubusch]

Provide additional uboot.env text environment files meant as a generic
demo. The default environment uses a uboot.env. The default environment
works somehow. This environment provides better support but only shows
one possible approach used in the Enclustra reference design setups.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 board/enclustra/mercury_aa1/mercury_aa1.env | 65 +++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 board/enclustra/mercury_aa1/mercury_aa1.env

diff --git a/board/enclustra/mercury_aa1/mercury_aa1.env b/board/enclustra/mercury_aa1/mercury_aa1.env
new file mode 100644
index 0000000000..07b4a95a75
--- /dev/null
+++ b/board/enclustra/mercury_aa1/mercury_aa1.env
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Enclustra GmbH
+ * <info@enclustra.com>
+ *
+ * This is an example configuration file for uboot.env generation.
+ *
+ * Given ENV_FAT_FILE defaults to "uboot.env" and ENV_SIZE defaults to 0x80000
+ * (see configuration options). Then adjust the configuration to your needs and
+ * build the a binary .env file as follows
+ * $ ./tools/mkenvimage -s 0x80000 -o uboot.env ./board/enclustra/mercury_aa1/mercury_aa1.env
+ *
+ * NB: Without providing this binary uboot.env the board is supposed to come up
+ * with the generic environment based on the architecture. This can be helpful
+ * when upgrading and/or recuding environments.
+ */
+bitstream_size=0xD00000
+bootargs=earlycon console=ttyS0,115200 rw rootwait root=/dev/mmcblk0p3
+bootargs_qspi=earlycon console=ttyS0,115200 rw root=/dev/ram0
+bootm_size=0x0a000000
+devnum=0
+devtype=mmc
+distro_bootpart=1
+env_size=0x80000
+fdt_addr_r=0x10000000
+fdtfile=system.dtb
+fdtload=
+	load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${bootdir}/${fdtfile};
+	load ${devtype} ${devnum}:${distro_bootpart} ${fdto_addr_r} ${bootdir}/${fdtofile};
+	fdt addr $fdt_addr_r;
+	fdt resize 8192;
+	fdt apply $fdto_addr_r
+fdtload_qspi=
+	sf probe;
+	sf read ${fdt_addr_r} ${qspi_offset_addr_devicetree} ${fdt_size};
+	sf read ${fdto_addr_r} ${qspi_offset_addr_dtoverlay} ${fdto_size};
+	fdt addr ${fdt_addr_r};
+	fdt resize 8192;
+	fdt apply ${fdto_addr_r}
+fdto_addr_r=0x100c0000
+fdtofile=socfpga_enclustra_mercury_sdmmc_overlay.dtbo
+fdto_size=0x40000
+fdt_size=0x40000
+kernel_addr_r=0x11000000
+kernel_size=0x1000000
+qspiboot=source ${scriptaddr}
+qspiload=
+	setenv bootargs ${bootargs_qspi};
+	sf probe;
+	sf read ${scriptaddr} ${qspi_offset_addr_boot_script} ${scriptsize}
+qspi_offset_addr_bitstream=0x300000
+qspi_offset_addr_boot_script=0x200000
+qspi_offset_addr_devicetree=0x280000
+qspi_offset_addr_dtoverlay=0x2c0000
+qspi_offset_addr_kernel=0x1000000
+qspi_offset_addr_rootfs=0x2000000
+qspi_offset_addr_spl=0x0
+qspi_offset_addr_uboot=0x100000
+qspi_offset_addr_uboot_env=0x180000
+rootfs_addr_r=0x12000000
+rootfs_size=0x2000000
+scriptaddr=0x10800000
+scriptsize=0x80000
+spl_size=0x100000
+uboot_size=0x80000
-- 
2.25.1

[PATCH 6/9] ARM: socfpga: add Enclustra AA1 boot scripts

[Lothar Rubusch]

Add support to boot Enclustra SoMs from MMC, SD or QSPI flash.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 board/enclustra/bootscripts/qspi-aa1.cmd | 12 ++++++++++++
 board/enclustra/bootscripts/sd-aa1.cmd   | 10 ++++++++++
 2 files changed, 22 insertions(+)
 create mode 100644 board/enclustra/bootscripts/qspi-aa1.cmd
 create mode 100644 board/enclustra/bootscripts/sd-aa1.cmd

diff --git a/board/enclustra/bootscripts/qspi-aa1.cmd b/board/enclustra/bootscripts/qspi-aa1.cmd
new file mode 100644
index 0000000000..42d02cfce1
--- /dev/null
+++ b/board/enclustra/bootscripts/qspi-aa1.cmd
@@ -0,0 +1,12 @@
+# This is an example input file for boot.scr generation.
+# Generate boot.scr
+# ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d board/enclustra/bootscripts/qspi-aa1.cmd boot.scr
+#
+# NB: The needed variables need to be set in the environment.
+bridge enable
+sf probe
+sf read $kernel_addr_r $qspi_offset_addr_kernel $kernel_size
+sf read $fdt_addr_r $qspi_offset_addr_devicetree $fdt_size
+sf read $rootfs_addr_r $qspi_offset_addr_rootfs $rootfs_size
+run fdtload_qspi
+bootm $kernel_addr_r $rootfs_addr_r $fdt_addr_r
diff --git a/board/enclustra/bootscripts/sd-aa1.cmd b/board/enclustra/bootscripts/sd-aa1.cmd
new file mode 100644
index 0000000000..4beefc7e13
--- /dev/null
+++ b/board/enclustra/bootscripts/sd-aa1.cmd
@@ -0,0 +1,10 @@
+# This is an example input file for boot.scr generation.
+# Generate boot.scr
+# ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "U-boot mmc start script" -d board/enclustra/bootscripts/sd-aa1.cmd boot.scr
+#
+# NB: The needed variables need to be set in the environment.
+bridge enable
+fatload mmc $devnum:$distro_bootpart $kernel_addr_r Image
+fatload mmc $devnum:$distro_bootpart $fdt_addr_r $fdtfile
+run fdtload
+bootm $kernel_addr_r - $fdt_addr_r
-- 
2.25.1

[PATCH 7/9] ARM: socfpga: AA1: support MAC from secure eeprom

[Lothar Rubusch]

Several Enclustra devices store MAC address in a secure eeprom device. In
most cases this is the atsha204a (alternatively DS28). The atsha204a device
is preconfigured accordingly. Reading then is based on u-boot's atsha204a
driver. Add such support for Enclustra's AA1 SoMs.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 board/enclustra/common/Kconfig                | 23 +++++
 board/enclustra/common/Makefile               |  3 +
 board/enclustra/common/enclustra_mac.h        | 48 +++++++++
 board/enclustra/common/mac_atsha204.c         | 97 +++++++++++++++++++
 board/enclustra/common/mac_common.c           | 54 +++++++++++
 board/enclustra/common/mac_ds28.c             | 88 +++++++++++++++++
 board/enclustra/mercury_aa1/mercury_aa1.c     |  7 ++
 .../socfpga_enclustra_mercury_aa1_defconfig   |  1 +
 drivers/misc/Kconfig                          |  2 +-
 9 files changed, 322 insertions(+), 1 deletion(-)
 create mode 100644 board/enclustra/common/enclustra_mac.h
 create mode 100644 board/enclustra/common/mac_atsha204.c
 create mode 100644 board/enclustra/common/mac_common.c
 create mode 100644 board/enclustra/common/mac_ds28.c

diff --git a/board/enclustra/common/Kconfig b/board/enclustra/common/Kconfig
index 51169bada3..51991f7882 100644
--- a/board/enclustra/common/Kconfig
+++ b/board/enclustra/common/Kconfig
@@ -1 +1,24 @@
+config ENCLUSTRA_EEPROM_MAC
+	bool "Enclustra MAC address"
+	select ATSHA204A
+	default y if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
+	help
+	  Reads the MAC address out of the EEPROM and configures the MAC
+	  addresses in the environment.
+
+choice
+	prompt "Enclustra EEPROM device"
+	depends on ENCLUSTRA_EEPROM_MAC
+	default ENCLUSTRA_EEPROM_MAC_ATSHA204 if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
+	help
+	  Specify the device where the MAC is stored.
+
+config ENCLUSTRA_EEPROM_MAC_ATSHA204
+	bool "MAC stored in 'ATSHA204'"
+
+config ENCLUSTRA_EEPROM_MAC_DS28
+	bool "MAC stored in 'DS28'"
+
+endchoice
+
 source "board/enclustra/mercury_aa1/Kconfig"
diff --git a/board/enclustra/common/Makefile b/board/enclustra/common/Makefile
index 16c8531d74..c83743abe7 100644
--- a/board/enclustra/common/Makefile
+++ b/board/enclustra/common/Makefile
@@ -2,3 +2,6 @@
 # Copyright (c) 2024 Enclustra GmbH
 
 # Common for several Enclustra modules
+obj-$(CONFIG_ENCLUSTRA_EEPROM_MAC) += mac_common.o
+obj-$(CONFIG_ENCLUSTRA_EEPROM_MAC_ATSHA204) += mac_atsha204.o
+obj-$(CONFIG_ENCLUSTRA_EEPROM_MAC_DS28) += mac_ds28.o
diff --git a/board/enclustra/common/enclustra_mac.h b/board/enclustra/common/enclustra_mac.h
new file mode 100644
index 0000000000..9631e9d458
--- /dev/null
+++ b/board/enclustra/common/enclustra_mac.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2024 Enclustra GmbH, <info@enclustra.com>
+ */
+
+#ifndef ENCLUSTRA_MAC
+# define ENCLUSTRA_MAC               0xF7B020
+#endif
+
+/*
+ * enclustra_mac_is_in_env - Check if MAC address is already set
+ *
+ * @env: name of the environment variable
+ * Return: true if MAC is set, false otherwise
+ */
+bool enclustra_mac_is_in_env(const char *env);
+
+/*
+ * enclustra_get_mac_is_enabled - Test if ethernet MAC is enabled in DT
+ *
+ * @alias: alias for ethernet MAC device tree node
+ * Return: 0 if OK, other value on error
+ */
+int enclustra_get_mac_is_enabled(const char *alias);
+
+/*
+ * enclustra_get_mac_from_eeprom - Get MAC address from eeprom and write it to enetaddr
+ *
+ * @enetaddr: buffer where address is to be stored
+ * @alias: alias for EEPROM device tree node
+ * Return: 0 if OK, other value on error
+ */
+int enclustra_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias);
+
+/*
+ * enclustra_get_mac1_from_mac - Get MAC1 address from MAC and write it to enetaddr
+ *
+ * @enetaddr: buffer where MAC is passed, MAC will be modified to MAC1
+ * Return: 0 if OK, else error value
+ */
+int enclustra_get_mac1_from_mac(unsigned char *enetaddr);
+
+/*
+ * enclustra_setup_mac_address - Try to get MAC address from various locations and write it to env
+ *
+ * Return: 0 if OK, other value on error
+ */
+int enclustra_setup_mac_address(void);
diff --git a/board/enclustra/common/mac_atsha204.c b/board/enclustra/common/mac_atsha204.c
new file mode 100644
index 0000000000..4bd25505d6
--- /dev/null
+++ b/board/enclustra/common/mac_atsha204.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Enclustra GmbH
+ */
+
+#include <dm.h>
+#include <atsha204a-i2c.h>
+#include <net.h>
+
+#include "enclustra_mac.h"
+
+int enclustra_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
+{
+	struct udevice *dev;
+	u32 hwaddr_h;
+	u8 data[4];
+	int i, j, eeprom_addr, mac_len, ret;
+
+	ret = uclass_get_device_by_name(UCLASS_MISC, alias, &dev);
+	if (ret) {
+		printf("%s: Failed, cannot find EEPROM! ret = %d\n", __func__, ret);
+		return ret;
+	}
+
+	/* Make sure atsha204a is in a defined state (part of protocol) */
+	if (atsha204a_sleep(dev)) {
+		printf("%s(): Failed to bring EEPROM in defined state\n", __func__);
+		return -ENODEV;
+	}
+
+	if (atsha204a_wakeup(dev)) {
+		printf("%s(): Failed to wakeup EEPROM\n", __func__);
+		return -ENODEV;
+	}
+
+	/* Read twice portions of 4 bytes (atsha204 protocol). One from address 4
+	 * the other from address 5 of the OTP zone. Then convert the data to
+	 * the 6 elements of the MAC address.
+	 */
+	eeprom_addr = 4;
+	mac_len = 6;
+	for (i = 0; i < 2; i++) {
+		eeprom_addr += i;
+		if (atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, eeprom_addr, data)) {
+			printf("%s(): Failed to parse ATSHA204A_ZONE_OTP of EEPROM\n",
+			       __func__);
+			return -EFAULT;
+		}
+
+		for (j = 0; j < 4 && j + i * 4 < mac_len; j++)
+			enetaddr[j + i * 4] = data[j];
+	}
+
+	/* Check if the value is a valid mac registered for
+	 * Enclustra  GmbH
+	 */
+	hwaddr_h = enetaddr[0] | enetaddr[1] << 8 | enetaddr[2] << 16;
+	if ((hwaddr_h & 0xFFFFFF) != ENCLUSTRA_MAC) {
+		printf("%s(): Failed, parsed MAC is no Enclustra MAC\n", __func__);
+		return -ENOENT;
+	}
+
+	if (!is_valid_ethaddr(enetaddr)) {
+		printf("%s(): Failed, address read from EEPROM is invalid!\n",
+		       __func__);
+		return -EINVAL;
+	}
+
+	printf("ethaddr set to %02X:%02X:%02X:%02X:%02X:%02X\n",
+	       enetaddr[0], enetaddr[1], enetaddr[2],
+	       enetaddr[3], enetaddr[4], enetaddr[5]);
+
+	return 0;
+}
+
+__weak int enclustra_setup_mac_address(void)
+{
+	unsigned char enetaddr[6];
+
+	if (enclustra_mac_is_in_env("ethaddr"))
+		return 0;
+
+	if (enclustra_get_mac_is_enabled("ethernet0"))
+		return 0;
+
+	if (enclustra_get_mac_from_eeprom(enetaddr, "atsha204a@64"))
+		return -ENXIO;
+
+	if (eth_env_set_enetaddr("ethaddr", enetaddr))
+		return -ENXIO;
+
+	if (!enclustra_get_mac1_from_mac(enetaddr))
+		return eth_env_set_enetaddr("eth1addr", enetaddr);
+
+	printf("%s(): Failed, unable to set mac address!\n", __func__);
+	return -ENXIO;
+}
diff --git a/board/enclustra/common/mac_common.c b/board/enclustra/common/mac_common.c
new file mode 100644
index 0000000000..cf5dac0e0e
--- /dev/null
+++ b/board/enclustra/common/mac_common.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Enclustra GmbH
+ */
+
+#include <dm.h>
+#include <atsha204a-i2c.h>
+#include <net.h>
+
+#include "enclustra_mac.h"
+
+bool enclustra_mac_is_in_env(const char *env)
+{
+	unsigned char enetaddr[6];
+
+	return eth_env_get_enetaddr(env, enetaddr);
+}
+
+int enclustra_get_mac_is_enabled(const char *alias)
+{
+	ofnode node =   ofnode_path(alias);
+
+	if (!ofnode_valid(node))
+		return -EINVAL;
+
+	if (!ofnode_is_enabled(node))
+		return -EINVAL;
+
+	return 0;
+}
+
+int enclustra_get_mac1_from_mac(unsigned char *enetaddr)
+{
+	u32 hwaddr_h;
+
+	/* Increment MAC addr */
+	hwaddr_h = (enetaddr[3] << 16) | (enetaddr[4] << 8) | enetaddr[5];
+	hwaddr_h = (hwaddr_h + 1) & 0xFFFFFF;
+	enetaddr[3] = (hwaddr_h >> 16) & 0xFF;
+	enetaddr[4] = (hwaddr_h >> 8) & 0xFF;
+	enetaddr[5] = hwaddr_h & 0xFF;
+
+	if (!is_valid_ethaddr(enetaddr)) {
+		printf("%s(): Failed, address computed from enetaddr is invalid!\n",
+		       __func__);
+		return -EINVAL;
+	}
+
+	printf("eth1addr set to %02X:%02X:%02X:%02X:%02X:%02X\n",
+	       enetaddr[0], enetaddr[1], enetaddr[2],
+	       enetaddr[3], enetaddr[4], enetaddr[5]);
+
+	return 0;
+}
diff --git a/board/enclustra/common/mac_ds28.c b/board/enclustra/common/mac_ds28.c
new file mode 100644
index 0000000000..9aed4f1de1
--- /dev/null
+++ b/board/enclustra/common/mac_ds28.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Enclustra GmbH
+ */
+
+#include <linux/compat.h>
+#include <dm.h>
+#include <i2c.h>
+#include <net.h>
+
+#include "enclustra_mac.h"
+
+#define DS28_I2C_ADDR 0x5C
+#define DS28_SYS_I2C_EEPROM_BUS 0
+
+int enclustra_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
+{
+	struct udevice *dev;
+	u32 hwaddr_h;
+	struct dm_i2c_chip *chip;
+	uint chip_addr = DS28_I2C_ADDR;
+	int alen = 1;
+	int ret;
+
+	if (i2c_get_chip_for_busnum(DS28_SYS_I2C_EEPROM_BUS, chip_addr,
+				    alen, &dev))
+		return -ENODEV;
+
+	chip = dev_get_parent_plat(dev);
+	if (chip->offset_len != alen) {
+		debug("I2C chip %x: alen %d does not match offset_len %d\n",
+		      chip_addr, alen, chip->offset_len);
+		return -EADDRNOTAVAIL;
+	}
+
+	ret = dm_i2c_read(dev, 0x10, enetaddr, 6);
+	if (ret) {
+		printf("%s(): Failed reading EEPROM! ret = %d\n", __func__, ret);
+		return ret;
+	}
+
+	/* Check if the value is a valid mac registered for
+	 * Enclustra  GmbH
+	 */
+	hwaddr_h = enetaddr[0] | enetaddr[1] << 8 | enetaddr[2] << 16;
+	if ((hwaddr_h & 0xFFFFFF) != ENCLUSTRA_MAC) {
+		printf("%s(): Failed, parsed MAC is no Enclustra MAC\n", __func__);
+		return -ENOENT;
+	}
+
+	if (!is_valid_ethaddr(enetaddr)) {
+		printf("%s(): Failed, address read from EEPROM is invalid!\n",
+		       __func__);
+		return -EINVAL;
+	}
+
+	printf("ethaddr set to %02X:%02X:%02X:%02X:%02X:%02X\n",
+	       enetaddr[0], enetaddr[1], enetaddr[2],
+	       enetaddr[3], enetaddr[4], enetaddr[5]);
+
+	return 0;
+}
+
+__weak int enclustra_setup_mac_address(void)
+{
+	unsigned char enetaddr[6];
+
+	if (enclustra_mac_is_in_env("ethaddr"))
+		return 0;
+
+	if (enclustra_get_mac_is_enabled("ethernet0"))
+		return 0;
+
+	// NB: DS28 is still not available in official DT, so referencing
+	// here by i2c busnumber and address directly
+	// preparation for DT access here, though
+	if (enclustra_get_mac_from_eeprom(enetaddr, ""))
+		return -ENXIO;
+
+	if (eth_env_set_enetaddr("ethaddr", enetaddr))
+		return -ENXIO;
+
+	if (!enclustra_get_mac1_from_mac(enetaddr))
+		return eth_env_set_enetaddr("eth1addr", enetaddr);
+
+	printf("%s(): Failed, unable to set mac address!\n", __func__);
+	return -ENXIO;
+}
diff --git a/board/enclustra/mercury_aa1/mercury_aa1.c b/board/enclustra/mercury_aa1/mercury_aa1.c
index 7de9b287d9..c53ae128f0 100644
--- a/board/enclustra/mercury_aa1/mercury_aa1.c
+++ b/board/enclustra/mercury_aa1/mercury_aa1.c
@@ -11,6 +11,8 @@
 #include <asm-generic/gpio.h>
 #include <asm/io.h>
 
+#include "../common/enclustra_mac.h"
+
 /* Pin muxing */
 #if !defined(CONFIG_SPL_BUILD)
 
@@ -27,6 +29,11 @@ static int altera_current_storage = ALTERA_NONE;
 
 #endif
 
+int board_late_init(void)
+{
+	return enclustra_setup_mac_address();
+}
+
 #if !defined(CONFIG_SPL_BUILD)
 
 static void set_mux_mmc(void)
diff --git a/configs/socfpga_enclustra_mercury_aa1_defconfig b/configs/socfpga_enclustra_mercury_aa1_defconfig
index b475bd916d..58c718864b 100644
--- a/configs/socfpga_enclustra_mercury_aa1_defconfig
+++ b/configs/socfpga_enclustra_mercury_aa1_defconfig
@@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_LATE_INIT=y
 CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x40000
 CONFIG_SPL_NO_BSS_LIMIT=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6009d55f40..90fa8c9eae 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -73,7 +73,7 @@ config ATSHA204A
 	help
 	   Enable support for I2C connected Atmel's ATSHA204A
 	   CryptoAuthentication module found for example on the Turris Omnia
-	   board.
+	   board and Enclustra SoC FPGA boards.
 
 config GATEWORKS_SC
 	bool "Gateworks System Controller Support"
-- 
2.25.1

[PATCH 8/9] ARM: socfpga: add si5338 clock generator support

[Lothar Rubusch]

The si5338 clock generator is needed on some Enclustra Socfpga SoMs.
Introduce minimal support of this device.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 drivers/clk/Kconfig                          |   1 +
 drivers/clk/Makefile                         |   1 +
 drivers/clk/skyworks/Kconfig                 |  10 +
 drivers/clk/skyworks/Makefile                |   3 +
 drivers/clk/skyworks/Si5338-RevB-Registers.h | 441 +++++++++++++++++++
 drivers/clk/skyworks/si5338_clkgen.c         | 177 ++++++++
 drivers/clk/skyworks/si5338_clkgen.h         |  18 +
 7 files changed, 651 insertions(+)
 create mode 100644 drivers/clk/skyworks/Kconfig
 create mode 100644 drivers/clk/skyworks/Makefile
 create mode 100644 drivers/clk/skyworks/Si5338-RevB-Registers.h
 create mode 100644 drivers/clk/skyworks/si5338_clkgen.c
 create mode 100644 drivers/clk/skyworks/si5338_clkgen.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9acbc47fe8..5d2053623c 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -259,6 +259,7 @@ source "drivers/clk/qcom/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/sunxi/Kconfig"
 source "drivers/clk/sifive/Kconfig"
+source "drivers/clk/skyworks/Kconfig"
 source "drivers/clk/starfive/Kconfig"
 source "drivers/clk/stm32/Kconfig"
 source "drivers/clk/tegra/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 847b9b2911..daa70112ac 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_CLK_QCOM) += qcom/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
 obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
 obj-$(CONFIG_CLK_SIFIVE) += sifive/
+obj-$(CONFIG_CLK_SKYWORKS_SI5338) += skyworks/
 obj-$(CONFIG_CLK_SUNXI) += sunxi/
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
 obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
diff --git a/drivers/clk/skyworks/Kconfig b/drivers/clk/skyworks/Kconfig
new file mode 100644
index 0000000000..dd041f603a
--- /dev/null
+++ b/drivers/clk/skyworks/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_SKYWORKS_SI5338
+	bool "Skyworks SI5338 clock generator"
+	depends on CLK
+	depends on DM_I2C
+	depends on SPL_I2C
+	help
+	  Configure the SI5338 clock generator device. The SI5338 is needed on
+	  some Enclustra Socfpga SoMs.
diff --git a/drivers/clk/skyworks/Makefile b/drivers/clk/skyworks/Makefile
new file mode 100644
index 0000000000..c676b6ef94
--- /dev/null
+++ b/drivers/clk/skyworks/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_CLK_SKYWORKS_SI5338) += si5338_clkgen.o
diff --git a/drivers/clk/skyworks/Si5338-RevB-Registers.h b/drivers/clk/skyworks/Si5338-RevB-Registers.h
new file mode 100644
index 0000000000..e1754cd807
--- /dev/null
+++ b/drivers/clk/skyworks/Si5338-RevB-Registers.h
@@ -0,0 +1,441 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 Enclustra GmbH
+ * <info@enclustra.com>
+ */
+
+#ifndef __SI5338_REVB_REGISTERS_H
+#define __SI5338_REVB_REGISTERS_H
+
+#include "si5338_clkgen.h"
+
+/*
+ * Register map for use with AN428 (JumpStart)
+ * http://www.skyworksinc.com/timing
+ * #BEGIN_HEADER
+ * Date = Friday, June 09, 2023 5:03 PM
+ * File version = 3
+ * Software Name = ClockBuilder Pro
+ * Software version = 4.9.0.0
+ * Software date = 4 24, 2023
+ * Chip = Si533x
+ * Part Number = Si533x
+ * #END_HEADER
+ * Input Frequency (MHz) = 24.000000000
+ * Input Type = CMOS_SSTL_HSTL
+ * P1 = 1
+ * Input Mux = RefClk
+ * FDBK Input Frequency (MHz) = 24.000000000
+ * FDBK Input Type = OFF
+ * P2 = 1
+ * FDBK Mux = NoClk
+ * PFD Input Frequency (MHz) = 24.000000000
+ * VCO Frequency (GHz) = 2.500000
+ * N = 104  1/6  (104.1667)
+ * Internal feedback enabled
+ * Output Clock 0
+ *  Output Frequency (MHz) = 125.000000000
+ *  Mux Selection = IDn
+ *  MultiSynth = 20  (20.0000)
+ *  R = 1
+ * Output Clock 1
+ *  Output is off
+ * Output Clock 2
+ *  Output is off
+ * Output Clock 3
+ *  Output Frequency (MHz) = 100.000000000
+ *  Mux Selection = IDn
+ *  MultiSynth = 25  (25.0000)
+ *  R = 1
+ * Driver 0
+ *  Enabled
+ *  Powered on
+ *  Output voltage = 3.30
+ *  Output type = 3.3V LVDS
+ *  Output state when disabled = Tristate
+ * Driver 1
+ *  Disabled
+ *  Powered off
+ *  Output voltage = 3.30
+ *  Output type = 3.3V LVDS
+ *  Output state when disabled = StopLow
+ * Driver 2
+ *  Disabled
+ *  Powered off
+ *  Output voltage = 3.30
+ *  Output type = 3.3V LVDS
+ *  Output state when disabled = StopLow
+ * Driver 3
+ *  Enabled
+ *  Powered on
+ *  Output voltage = 3.30
+ *  Output type = 3.3V CMOS on A
+ *  Output state when disabled = Tristate
+ * Clock 0 phase inc/dec step size (ns) = 0.000
+ * Clock 1 phase inc/dec step size (ns) = 0.000
+ * Clock 2 phase inc/dec step size (ns) = 0.000
+ * Clock 3 phase inc/dec step size (ns) = 0.000
+ * Phase increment and decrement pin control is off
+ * Frequency increment and decrement pin control is off
+ * Frequency increment and decrement is disabled
+ * Initial phase offset 0 (ns) = 0.000
+ * Initial phase offset 1 (ns) = 0.000
+ * Initial phase offset 2 (ns) = 0.000
+ * Initial phase offset 3 (ns) = 0.000
+ * SSC is disabled
+ */
+
+#define NUM_REGS_MAX 350
+
+struct reg_data const reg_store[NUM_REGS_MAX] = {
+	{  0, 0x00, 0x00},
+	{  1, 0x00, 0x00},
+	{  2, 0x00, 0x00},
+	{  3, 0x00, 0x00},
+	{  4, 0x00, 0x00},
+	{  5, 0x00, 0x00},
+	{  6, 0x08, 0x1D},
+	{  7, 0x00, 0x00},
+	{  8, 0x70, 0x00},
+	{  9, 0x0F, 0x00},
+	{ 10, 0x00, 0x00},
+	{ 11, 0x00, 0x00},
+	{ 12, 0x00, 0x00},
+	{ 13, 0x00, 0x00},
+	{ 14, 0x00, 0x00},
+	{ 15, 0x00, 0x00},
+	{ 16, 0x00, 0x00},
+	{ 17, 0x00, 0x00},
+	{ 18, 0x00, 0x00},
+	{ 19, 0x00, 0x00},
+	{ 20, 0x00, 0x00},
+	{ 21, 0x00, 0x00},
+	{ 22, 0x00, 0x00},
+	{ 23, 0x00, 0x00},
+	{ 24, 0x00, 0x00},
+	{ 25, 0x00, 0x00},
+	{ 26, 0x00, 0x00},
+	{ 27, 0x70, 0x80},
+	{ 28, 0x0B, 0xFF},
+	{ 29, 0x08, 0xFF},
+	{ 30, 0xB0, 0xFF},
+	{ 31, 0xC0, 0xFF},
+	{ 32, 0xE3, 0xFF},
+	{ 33, 0xE3, 0xFF},
+	{ 34, 0xC0, 0xFF},
+	{ 35, 0x00, 0xFF},
+	{ 36, 0x06, 0x1F},
+	{ 37, 0x00, 0x1F},
+	{ 38, 0x00, 0x1F},
+	{ 39, 0x01, 0x1F},
+	{ 40, 0x63, 0xFF},
+	{ 41, 0x0C, 0x7F},
+	{ 42, 0x37, 0x3F},
+	{ 43, 0x00, 0x00},
+	{ 44, 0x00, 0x00},
+	{ 45, 0x00, 0xFF},
+	{ 46, 0x00, 0xFF},
+	{ 47, 0x14, 0x3F},
+	{ 48, 0x3C, 0xFF},
+	{ 49, 0x00, 0xFF},
+	{ 50, 0xC4, 0xFF},
+	{ 51, 0x07, 0xFF},
+	{ 52, 0x10, 0xFF},
+	{ 53, 0x00, 0xFF},
+	{ 54, 0x08, 0xFF},
+	{ 55, 0x00, 0xFF},
+	{ 56, 0x00, 0xFF},
+	{ 57, 0x00, 0xFF},
+	{ 58, 0x00, 0xFF},
+	{ 59, 0x01, 0xFF},
+	{ 60, 0x00, 0xFF},
+	{ 61, 0x00, 0xFF},
+	{ 62, 0x00, 0x3F},
+	{ 63, 0x10, 0xFF},
+	{ 64, 0x00, 0xFF},
+	{ 65, 0x00, 0xFF},
+	{ 66, 0x00, 0xFF},
+	{ 67, 0x00, 0xFF},
+	{ 68, 0x00, 0xFF},
+	{ 69, 0x00, 0xFF},
+	{ 70, 0x00, 0xFF},
+	{ 71, 0x00, 0xFF},
+	{ 72, 0x00, 0xFF},
+	{ 73, 0x00, 0x3F},
+	{ 74, 0x10, 0xFF},
+	{ 75, 0x00, 0xFF},
+	{ 76, 0x00, 0xFF},
+	{ 77, 0x00, 0xFF},
+	{ 78, 0x00, 0xFF},
+	{ 79, 0x00, 0xFF},
+	{ 80, 0x00, 0xFF},
+	{ 81, 0x00, 0xFF},
+	{ 82, 0x00, 0xFF},
+	{ 83, 0x00, 0xFF},
+	{ 84, 0x00, 0x3F},
+	{ 85, 0x10, 0xFF},
+	{ 86, 0x80, 0xFF},
+	{ 87, 0x0A, 0xFF},
+	{ 88, 0x00, 0xFF},
+	{ 89, 0x00, 0xFF},
+	{ 90, 0x00, 0xFF},
+	{ 91, 0x00, 0xFF},
+	{ 92, 0x01, 0xFF},
+	{ 93, 0x00, 0xFF},
+	{ 94, 0x00, 0xFF},
+	{ 95, 0x00, 0x3F},
+	{ 96, 0x10, 0x00},
+	{ 97, 0x15, 0xFF},
+	{ 98, 0x32, 0xFF},
+	{ 99, 0x08, 0xFF},
+	{100, 0x00, 0xFF},
+	{101, 0x00, 0xFF},
+	{102, 0x00, 0xFF},
+	{103, 0x06, 0xFF},
+	{104, 0x00, 0xFF},
+	{105, 0x00, 0xFF},
+	{106, 0x80, 0xBF},
+	{107, 0x00, 0xFF},
+	{108, 0x00, 0xFF},
+	{109, 0x00, 0xFF},
+	{110, 0x00, 0xFF},
+	{111, 0x00, 0xFF},
+	{112, 0x00, 0xFF},
+	{113, 0x00, 0xFF},
+	{114, 0x40, 0xFF},
+	{115, 0x00, 0xFF},
+	{116, 0x80, 0xFF},
+	{117, 0x00, 0xFF},
+	{118, 0x40, 0xFF},
+	{119, 0x00, 0xFF},
+	{120, 0x00, 0xFF},
+	{121, 0x00, 0xFF},
+	{122, 0x00, 0xFF},
+	{123, 0x00, 0xFF},
+	{124, 0x00, 0xFF},
+	{125, 0x00, 0xFF},
+	{126, 0x00, 0xFF},
+	{127, 0x00, 0xFF},
+	{128, 0x00, 0xFF},
+	{129, 0x00, 0x0F},
+	{130, 0x00, 0x0F},
+	{131, 0x00, 0xFF},
+	{132, 0x00, 0xFF},
+	{133, 0x00, 0xFF},
+	{134, 0x00, 0xFF},
+	{135, 0x00, 0xFF},
+	{136, 0x00, 0xFF},
+	{137, 0x00, 0xFF},
+	{138, 0x00, 0xFF},
+	{139, 0x00, 0xFF},
+	{140, 0x00, 0xFF},
+	{141, 0x00, 0xFF},
+	{142, 0x00, 0xFF},
+	{143, 0x00, 0xFF},
+	{144, 0x00, 0xFF},
+	{145, 0x00, 0x00},
+	{146, 0xFF, 0x00},
+	{147, 0x00, 0x00},
+	{148, 0x00, 0x00},
+	{149, 0x00, 0x00},
+	{150, 0x00, 0x00},
+	{151, 0x00, 0x00},
+	{152, 0x00, 0xFF},
+	{153, 0x00, 0xFF},
+	{154, 0x00, 0xFF},
+	{155, 0x00, 0xFF},
+	{156, 0x00, 0xFF},
+	{157, 0x00, 0xFF},
+	{158, 0x00, 0x0F},
+	{159, 0x00, 0x0F},
+	{160, 0x00, 0xFF},
+	{161, 0x00, 0xFF},
+	{162, 0x00, 0xFF},
+	{163, 0x00, 0xFF},
+	{164, 0x00, 0xFF},
+	{165, 0x00, 0xFF},
+	{166, 0x00, 0xFF},
+	{167, 0x00, 0xFF},
+	{168, 0x00, 0xFF},
+	{169, 0x00, 0xFF},
+	{170, 0x00, 0xFF},
+	{171, 0x00, 0xFF},
+	{172, 0x00, 0xFF},
+	{173, 0x00, 0xFF},
+	{174, 0x00, 0xFF},
+	{175, 0x00, 0xFF},
+	{176, 0x00, 0xFF},
+	{177, 0x00, 0xFF},
+	{178, 0x00, 0xFF},
+	{179, 0x00, 0xFF},
+	{180, 0x00, 0xFF},
+	{181, 0x00, 0x0F},
+	{182, 0x00, 0xFF},
+	{183, 0x00, 0xFF},
+	{184, 0x00, 0xFF},
+	{185, 0x00, 0xFF},
+	{186, 0x00, 0xFF},
+	{187, 0x00, 0xFF},
+	{188, 0x00, 0xFF},
+	{189, 0x00, 0xFF},
+	{190, 0x00, 0xFF},
+	{191, 0x00, 0xFF},
+	{192, 0x00, 0xFF},
+	{193, 0x00, 0xFF},
+	{194, 0x00, 0xFF},
+	{195, 0x00, 0xFF},
+	{196, 0x00, 0xFF},
+	{197, 0x00, 0xFF},
+	{198, 0x00, 0xFF},
+	{199, 0x00, 0xFF},
+	{200, 0x00, 0xFF},
+	{201, 0x00, 0xFF},
+	{202, 0x00, 0xFF},
+	{203, 0x00, 0x0F},
+	{204, 0x00, 0xFF},
+	{205, 0x00, 0xFF},
+	{206, 0x00, 0xFF},
+	{207, 0x00, 0xFF},
+	{208, 0x00, 0xFF},
+	{209, 0x00, 0xFF},
+	{210, 0x00, 0xFF},
+	{211, 0x00, 0xFF},
+	{212, 0x00, 0xFF},
+	{213, 0x00, 0xFF},
+	{214, 0x00, 0xFF},
+	{215, 0x00, 0xFF},
+	{216, 0x00, 0xFF},
+	{217, 0x00, 0xFF},
+	{218, 0x00, 0x00},
+	{219, 0x00, 0x00},
+	{220, 0x00, 0x00},
+	{221, 0x0D, 0x00},
+	{222, 0x00, 0x00},
+	{223, 0x00, 0x00},
+	{224, 0xF4, 0x00},
+	{225, 0xF0, 0x00},
+	{226, 0x00, 0x00},
+	{227, 0x00, 0x00},
+	{228, 0x00, 0x00},
+	{229, 0x00, 0x00},
+	{231, 0x00, 0x00},
+	{232, 0x00, 0x00},
+	{233, 0x00, 0x00},
+	{234, 0x00, 0x00},
+	{235, 0x00, 0x00},
+	{236, 0x00, 0x00},
+	{237, 0x00, 0x00},
+	{238, 0x14, 0x00},
+	{239, 0x00, 0x00},
+	{240, 0x00, 0x00},
+	{242, 0x02, 0x02},
+	{243, 0xF0, 0x00},
+	{244, 0x00, 0x00},
+	{245, 0x00, 0x00},
+	{247, 0x00, 0x00},
+	{248, 0x00, 0x00},
+	{249, 0xA8, 0x00},
+	{250, 0x00, 0x00},
+	{251, 0x84, 0x00},
+	{252, 0x00, 0x00},
+	{253, 0x00, 0x00},
+	{254, 0x00, 0x00},
+	{255,    1, 0xFF}, // set page bit to 1
+	{  0, 0x00, 0x00},
+	{  1, 0x00, 0x00},
+	{  2, 0x00, 0x00},
+	{  3, 0x00, 0x00},
+	{  4, 0x00, 0x00},
+	{  5, 0x00, 0x00},
+	{  6, 0x00, 0x00},
+	{  7, 0x00, 0x00},
+	{  8, 0x00, 0x00},
+	{  9, 0x00, 0x00},
+	{ 10, 0x00, 0x00},
+	{ 11, 0x00, 0x00},
+	{ 12, 0x00, 0x00},
+	{ 13, 0x00, 0x00},
+	{ 14, 0x00, 0x00},
+	{ 15, 0x00, 0x00},
+	{ 16, 0x00, 0x00},
+	{ 17, 0x01, 0x00},
+	{ 18, 0x00, 0x00},
+	{ 19, 0x00, 0x00},
+	{ 20, 0x90, 0x00},
+	{ 21, 0x31, 0x00},
+	{ 22, 0x00, 0x00},
+	{ 23, 0x00, 0x00},
+	{ 24, 0x01, 0x00},
+	{ 25, 0x00, 0x00},
+	{ 26, 0x00, 0x00},
+	{ 27, 0x00, 0x00},
+	{ 28, 0x00, 0x00},
+	{ 29, 0x00, 0x00},
+	{ 30, 0x00, 0x00},
+	{ 31, 0x00, 0xFF},
+	{ 32, 0x00, 0xFF},
+	{ 33, 0x01, 0xFF},
+	{ 34, 0x00, 0xFF},
+	{ 35, 0x00, 0xFF},
+	{ 36, 0x90, 0xFF},
+	{ 37, 0x31, 0xFF},
+	{ 38, 0x00, 0xFF},
+	{ 39, 0x00, 0xFF},
+	{ 40, 0x01, 0xFF},
+	{ 41, 0x00, 0xFF},
+	{ 42, 0x00, 0xFF},
+	{ 43, 0x00, 0x0F},
+	{ 44, 0x00, 0x00},
+	{ 45, 0x00, 0x00},
+	{ 46, 0x00, 0x00},
+	{ 47, 0x00, 0xFF},
+	{ 48, 0x00, 0xFF},
+	{ 49, 0x01, 0xFF},
+	{ 50, 0x00, 0xFF},
+	{ 51, 0x00, 0xFF},
+	{ 52, 0x90, 0xFF},
+	{ 53, 0x31, 0xFF},
+	{ 54, 0x00, 0xFF},
+	{ 55, 0x00, 0xFF},
+	{ 56, 0x01, 0xFF},
+	{ 57, 0x00, 0xFF},
+	{ 58, 0x00, 0xFF},
+	{ 59, 0x00, 0x0F},
+	{ 60, 0x00, 0x00},
+	{ 61, 0x00, 0x00},
+	{ 62, 0x00, 0x00},
+	{ 63, 0x00, 0xFF},
+	{ 64, 0x00, 0xFF},
+	{ 65, 0x01, 0xFF},
+	{ 66, 0x00, 0xFF},
+	{ 67, 0x00, 0xFF},
+	{ 68, 0x90, 0xFF},
+	{ 69, 0x31, 0xFF},
+	{ 70, 0x00, 0xFF},
+	{ 71, 0x00, 0xFF},
+	{ 72, 0x01, 0xFF},
+	{ 73, 0x00, 0xFF},
+	{ 74, 0x00, 0xFF},
+	{ 75, 0x00, 0x0F},
+	{ 76, 0x00, 0x00},
+	{ 77, 0x00, 0x00},
+	{ 78, 0x00, 0x00},
+	{ 79, 0x00, 0xFF},
+	{ 80, 0x00, 0xFF},
+	{ 81, 0x00, 0xFF},
+	{ 82, 0x00, 0xFF},
+	{ 83, 0x00, 0xFF},
+	{ 84, 0x90, 0xFF},
+	{ 85, 0x31, 0xFF},
+	{ 86, 0x00, 0xFF},
+	{ 87, 0x00, 0xFF},
+	{ 88, 0x01, 0xFF},
+	{ 89, 0x00, 0xFF},
+	{ 90, 0x00, 0xFF},
+	{ 91, 0x00, 0x0F},
+	{ 92, 0x00, 0x00},
+	{ 93, 0x00, 0x00},
+	{ 94, 0x00, 0x00},
+	{255,    0, 0xFF} }; // set page bit to 0
+
+#endif /* __SI5338_REVB_REGISTERS_H */
diff --git a/drivers/clk/skyworks/si5338_clkgen.c b/drivers/clk/skyworks/si5338_clkgen.c
new file mode 100644
index 0000000000..903dd05d5d
--- /dev/null
+++ b/drivers/clk/skyworks/si5338_clkgen.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Enclustra GmbH
+ *
+ * SI5338 - A I2C programmable any-frequency, any-output quad clock generator.
+ */
+
+#include <linux/compat.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include "si5338_clkgen.h"
+
+#include "Si5338-RevB-Registers.h"
+
+int i2c_write_simple(struct udevice *dev, u8 addr, u8 data)
+{
+	unsigned char buf[1];
+
+	buf[0] = data;
+	if (dm_i2c_write(dev, addr, buf, 1) != 0) {
+		printf("SI5338 I2C write failed: %02x, %02x\n", addr, data);
+		return -1;
+	}
+	return 0;
+}
+
+int i2c_write_masked(struct udevice *dev, u8 addr, u8 data, u8 mask)
+{
+	unsigned char buf[1];
+
+	if (mask == 0x00)
+		return 0;
+
+	if (mask == 0xff)
+		return i2c_write_simple(dev, addr, data);
+
+	if (dm_i2c_read(dev, addr, buf, 1) != 0) {
+		printf("SI5338 I2C read failed\n");
+		return -1;
+	}
+	buf[0] &= ~mask;
+	buf[0] |= data & mask;
+	if (dm_i2c_write(dev, addr, buf, 1) != 0) {
+		printf("SI5338 I2C write failed: %02x, %02x, %02x\n",
+		       addr, data, mask);
+		return -1;
+	}
+	return 0;
+}
+
+int si5338_init(void)
+{
+	unsigned char buf[1];
+	struct udevice *dev;
+	int try = 0;
+	int i;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(0, 0x70, 1, &dev);
+	if (ret) {
+		printf("SI5338 I2C init failed\n");
+		return -ENODEV;
+	}
+
+	/* Set page to 0 */
+	if (i2c_write_simple(dev, 255, 0x00))
+		return -EFAULT;
+
+	/* Disable outputs */
+	if (i2c_write_masked(dev, 230, 0x10, 0x10))
+		return -EFAULT;
+
+	/* Pause */
+	if (i2c_write_masked(dev, 241, 0x80, 0x80))
+		return -EFAULT;
+
+	/* Write new configuration */
+	for (i = 0; i < NUM_REGS_MAX; i++) {
+		if (i2c_write_masked(dev, reg_store[i].reg_addr,
+				     reg_store[i].reg_val,
+				     reg_store[i].reg_mask)) {
+			return -EFAULT;
+		}
+	}
+
+	/* Validate input clock status */
+	do {
+		if (dm_i2c_read(dev, 218, buf, 1) != 0) {
+			printf("SI5338 I2C read failed\n");
+			return -EFAULT;
+		}
+	} while ((buf[0] & 0x04) != 0);
+
+	/* Configure PLL for locking */
+	if (i2c_write_masked(dev, 49, 0, 0x80))
+		return -EFAULT;
+
+	/* Initiate locking of PLL */
+	if (i2c_write_simple(dev, 246, 0x02))
+		return -EFAULT;
+
+	/* Wait 25ms (100ms to be on the safe side) */
+	mdelay(100);
+
+	/* Restart */
+	if (i2c_write_masked(dev, 241, 0x65, 0xff))
+		return -EFAULT;
+
+	/* Confirm PLL lock status */
+	do {
+		if (dm_i2c_read(dev, 218, buf, 1) != 0) {
+			printf("SI5338 I2C read failed\n");
+			return -EFAULT;
+		}
+		mdelay(100);
+		try++;
+		if (try > 10) {
+			printf("SI5338 PLL is not locking\n");
+			return -EFAULT;
+		}
+	} while ((buf[0] & 0x15) != 0);
+
+	/* Copy fcal values to active registers */
+	if (dm_i2c_read(dev, 237, buf, 1) != 0) {
+		printf("SI5338 I2C failed\n");
+		return -EFAULT;
+	}
+
+	if (i2c_write_masked(dev, 47, buf[0], 0x03))
+		return -EFAULT;
+
+	if (dm_i2c_read(dev, 236, buf, 1) != 0) {
+		printf("SI5338 I2C failed\n");
+		return -EFAULT;
+	}
+
+	if (i2c_write_masked(dev, 46, buf[0], 0xFF))
+		return -EFAULT;
+
+	if (dm_i2c_read(dev, 235, buf, 1) != 0) {
+		printf("SI5338 I2C failed\n");
+		return -EFAULT;
+	}
+
+	if (i2c_write_simple(dev, 45, buf[0]))
+		return -EFAULT;
+
+	if (i2c_write_masked(dev, 47, 0x14, 0xFC))
+		return -EFAULT;
+
+	/* Set PLL to use FCAL values */
+	if (i2c_write_masked(dev, 49, 0x80, 0x80))
+		return -EFAULT;
+
+	/* Enable outputs */
+	if (i2c_write_simple(dev, 230, 0x00))
+		return -EFAULT;
+
+	printf("SI5338 init successful\n");
+
+	return 0;
+}
+
+static int si5338_clk_probe(struct udevice *dev)
+{
+	return si5338_init();
+}
+
+U_BOOT_DRIVER(si5338_clkgen) = {
+	.name = "si5338_clkgen",
+	.id = UCLASS_CLK,
+	.probe = si5338_clk_probe,
+};
diff --git a/drivers/clk/skyworks/si5338_clkgen.h b/drivers/clk/skyworks/si5338_clkgen.h
new file mode 100644
index 0000000000..98c6ff1960
--- /dev/null
+++ b/drivers/clk/skyworks/si5338_clkgen.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 Enclustra GmbH
+ * <info@enclustra.com>
+ */
+
+#ifndef __SI5338_CLKGEN_H
+#define __SI5338_CLKGEN_H
+
+int si5338_init(void);
+
+struct reg_data {
+	unsigned char reg_addr;
+	unsigned char reg_val;
+	unsigned char reg_mask;
+};
+
+#endif /* __SI5338_CLKGEN_H */
-- 
2.25.1

[PATCH 9/9] ARM: socfpga: make AA1 use si5338 clock gen

[Lothar Rubusch]

Apply usage of the si5338 clock generator in Enclustra's AA1 SoM as it
has such a chip.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 board/enclustra/mercury_aa1/mercury_aa1.c       | 7 +++++++
 configs/socfpga_enclustra_mercury_aa1_defconfig | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/board/enclustra/mercury_aa1/mercury_aa1.c b/board/enclustra/mercury_aa1/mercury_aa1.c
index c53ae128f0..30a2bf6ea7 100644
--- a/board/enclustra/mercury_aa1/mercury_aa1.c
+++ b/board/enclustra/mercury_aa1/mercury_aa1.c
@@ -10,6 +10,7 @@
 #include <dm/uclass.h>
 #include <asm-generic/gpio.h>
 #include <asm/io.h>
+#include <dm.h>
 
 #include "../common/enclustra_mac.h"
 
@@ -31,6 +32,12 @@ static int altera_current_storage = ALTERA_NONE;
 
 int board_late_init(void)
 {
+	struct udevice *si5338;
+
+	if (IS_ENABLED(CONFIG_CLK_SKYWORKS_SI5338))
+		uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(si5338_clkgen),
+					    &si5338);
+
 	return enclustra_setup_mac_address();
 }
 
diff --git a/configs/socfpga_enclustra_mercury_aa1_defconfig b/configs/socfpga_enclustra_mercury_aa1_defconfig
index 58c718864b..a4b48da207 100644
--- a/configs/socfpga_enclustra_mercury_aa1_defconfig
+++ b/configs/socfpga_enclustra_mercury_aa1_defconfig
@@ -38,6 +38,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x15000
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_FPGA=y
+CONFIG_SPL_I2C=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
 CONFIG_CMD_ASKENV=y
@@ -58,6 +59,7 @@ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_SKYWORKS_SI5338=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_MISC=y
-- 
2.25.1

Re: [PATCH 3/9] ARM: socfpga: add Enclustra AA1 SoM support

[Tom Rini]

[-- Attachment #1: Type: text/plain, Size: 6282 bytes --]

On Thu, Sep 12, 2024 at 06:06:43AM +0000, Lothar Rubusch wrote:

> Introduce initial support for the Enclustra SoMs:
> 
> - Mercury AA1
> 
> Cover general board files for SD/MMC and QSPI boot modes. Integrate the
> boards to kconfig. All build variants will depend on Quartus handoff
> files, thus they depend on the particular Quartus design. The approach is
> covered in the according documentation part.
> 
> Additionally add configuration for SD/MMC boot and QSPI bootmodes. Register
> additional targets in kconfig.
> 
> Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
> Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
[snip]
> diff --git a/board/enclustra/mercury_aa1/mercury_aa1.c b/board/enclustra/mercury_aa1/mercury_aa1.c
> new file mode 100644
> index 0000000000..7de9b287d9
> --- /dev/null
> +++ b/board/enclustra/mercury_aa1/mercury_aa1.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2024 Enclustra GmbH
> + * <info@enclustra.com>
> + */
> +
> +#include <command.h>
> +#include <env.h>
> +#include <init.h>
> +#include <dm/uclass.h>
> +#include <asm-generic/gpio.h>
> +#include <asm/io.h>
> +
> +/* Pin muxing */
> +#if !defined(CONFIG_SPL_BUILD)
> +
> +#define ALTERA_NONE 0
> +#define ALTERA_MMC 1
> +#define ALTERA_QSPI 2
> +#define ALTERA_EMMC 3
> +#define MMC_CLK_DIV 0x9
> +#define QSPI_CLK_DIV 0x384
> +#define ALTERA_PINMUX_OFFS 0xffd07200
> +#define ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE 0xFFD04078
> +
> +static int altera_current_storage = ALTERA_NONE;
> +
> +#endif
> +
> +#if !defined(CONFIG_SPL_BUILD)
> +
> +static void set_mux_mmc(void)
> +{
> +	u32 pinmux_arr[] = {0x0c, 0x8,  // IO4 connected to SDMMC
> +			0x10, 0x8,	// IO5
> +			0x14, 0x8,	// IO6
> +			0x18, 0x8,	// IO7
> +			0x1c, 0x8,	// IO8
> +			0x20, 0x8,	// IO9
> +			0x24, 0xf,	// IO10 connected to GPIO
> +			0x28, 0xf,	// IO11
> +			0x2c, 0xf,	// IO12
> +			0x30, 0xf,	// IO13
> +			0x34, 0xf,	// IO14
> +			0x38, 0xf};	// IO15
> +	u32 len, i, offset, value;
> +
> +	len = sizeof(pinmux_arr) / sizeof(u32);
> +	for (i = 0; i < len; i += 2) {
> +		offset = pinmux_arr[i];
> +		value = pinmux_arr[i + 1];
> +		writel(value, ALTERA_PINMUX_OFFS + offset);
> +	}
> +}
> +
> +static void set_mux_emmc(void)
> +{
> +	u32 pinmux_arr[] = {0x0c, 0x8,  // IO4
> +		0x10, 0x8,	// IO5
> +		0x14, 0x8,	// IO6
> +		0x18, 0x8,	// IO7
> +		0x1c, 0x8,	// IO8
> +		0x20, 0x8,	// IO9
> +		0x24, 0xf,	// IO10
> +		0x28, 0xf,	// IO11
> +		0x2c, 0x8,	// IO12
> +		0x30, 0x8,	// IO13
> +		0x34, 0x8,	// IO14
> +		0x38, 0x8};	// IO15
> +	u32 len, i, offset, value;
> +
> +	len = sizeof(pinmux_arr) / sizeof(u32);
> +	for (i = 0; i < len; i += 2) {
> +		offset = pinmux_arr[i];
> +		value = pinmux_arr[i + 1];
> +		writel(value, ALTERA_PINMUX_OFFS + offset);
> +	}
> +}
> +
> +static void set_mux_qspi(void)
> +{
> +	u32 pinmux_arr[] = {0x0c, 0x4,  // IO4 connected to QSPI
> +		0x10, 0x4,	// IO5
> +		0x14, 0x4,	// IO6
> +		0x18, 0x4,	// IO7
> +		0x1c, 0x4,	// IO8
> +		0x20, 0x4,	// IO9
> +		0x24, 0xf,	// IO10
> +		0x28, 0xf,	// IO11
> +		0x2c, 0xf,	// IO12
> +		0x30, 0xf,	// IO13
> +		0x34, 0xf,	// IO14
> +		0x38, 0xf};	// IO15
> +	u32 len, i, offset, value;
> +
> +	len = sizeof(pinmux_arr) / sizeof(u32);
> +	for (i = 0; i < len; i += 2) {
> +		offset = pinmux_arr[i];
> +		value = pinmux_arr[i + 1];
> +		writel(value, ALTERA_PINMUX_OFFS + offset);
> +	}
> +}
> +
> +void altera_set_storage(int store)

Should be static?

> +{
> +	unsigned int gpio_flash_sel;
> +	unsigned int gpio_flash_oe;
> +
> +	if (store == altera_current_storage)
> +		return;
> +
> +	if (gpio_lookup_name("portb5", NULL, NULL, &gpio_flash_oe)) {
> +		printf("ERROR: GPIO not found\n");
> +		return;
> +	}
> +
> +	if (gpio_request(gpio_flash_oe, "flash_oe")) {
> +		printf("ERROR: GPIO request failed\n");
> +		return;
> +	}
> +
> +	if (gpio_lookup_name("portc6", NULL, NULL, &gpio_flash_sel)) {
> +		printf("ERROR: GPIO not found\n");
> +		return;
> +	}
> +
> +	if (gpio_request(gpio_flash_sel, "flash_sel")) {
> +		printf("ERROR: GPIO request failed\n");
> +		return;
> +	}
> +
> +	switch (store) {
> +	case ALTERA_MMC:
> +		set_mux_mmc();
> +		gpio_direction_output(gpio_flash_sel, 0);
> +		gpio_direction_output(gpio_flash_oe, 0);
> +		altera_current_storage = ALTERA_MMC;
> +		writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
> +		break;
> +	case ALTERA_EMMC:
> +		set_mux_emmc();
> +		gpio_direction_output(gpio_flash_sel, 1);
> +		gpio_direction_output(gpio_flash_oe, 1);
> +		altera_current_storage = ALTERA_EMMC;
> +		writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
> +		break;
> +	case ALTERA_QSPI:
> +		set_mux_qspi();
> +		gpio_direction_output(gpio_flash_sel, 1);
> +		gpio_direction_output(gpio_flash_oe, 0);
> +		altera_current_storage = ALTERA_QSPI;
> +		writel(QSPI_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
> +		break;
> +	default:
> +		altera_current_storage = ALTERA_NONE;
> +		break;
> +	}
> +
> +	gpio_free(gpio_flash_sel);
> +	gpio_free(gpio_flash_oe);
> +}
> +
> +int altera_set_storage_cmd(struct cmd_tbl *cmdtp, int flag,
> +			   int argc, char * const argv[])

Same?

> +{
> +	if (argc != 2)
> +		return CMD_RET_USAGE;
> +
> +	if (!strcmp(argv[1], "MMC"))
> +		altera_set_storage(ALTERA_MMC);
> +	else if (!strcmp(argv[1], "QSPI"))
> +		altera_set_storage(ALTERA_QSPI);
> +	else if (!strcmp(argv[1], "EMMC"))
> +		altera_set_storage(ALTERA_EMMC);
> +	else
> +		return CMD_RET_USAGE;
> +
> +	return CMD_RET_SUCCESS;
> +}
> +
> +U_BOOT_CMD(altera_set_storage, 2, 0, altera_set_storage_cmd,
> +	   "Set non volatile memory access",
> +	   "<MMC|QSPI|EMMC> - Set access for the selected memory device");
> +
> +#endif

The entire file seems to be for just adding the cmd. Perhaps rename this
file to reflect that and have the Makefile only even build this when
CONFIG_SPL_BUILD is not set. And then yes, the later patch will need to
be refactored slightly.

Also, the MAINTAINERS entry doesn't cover the documentation (which I'm
glad to see being added at the start!) nor the clock driver.

-- 
Tom

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]

Re: [PATCH 1/9] doc: board: enclustra: add Enclustra Intel AA1 SoM

[Marek Vasut]

On 9/12/24 8:06 AM, Lothar Rubusch wrote:
[...]

> +Mercury AA1 Module (Arria1 10)
> +==============================
> +
> +- SoM: https://www.enclustra.com/en/products/system-on-chip-modules/mercury-aa1/
> +- Carrier board Mercury+ ST1: https://www.enclustra.com/en/products/base-boards/mercury-st1/
> +- Carrier board Mercury+ PE1: https://www.enclustra.com/en/products/base-boards/mercury-pe1-200-300-400/
> +- Carrier board Mercury+ PE3: https://www.enclustra.com/en/products/base-boards/mercury-pe3/
> +
> +There are slightly different variants of the AA1 SoM, going by the identifier.
> +
> +- Me-aa1-270-2i2-d11e-nfx3
> +- Me-aa1-270-3e4-d11e-nfx3
> +- Me-aa1-480-2i3-d12e-nfx3
> +
> +The u-boot setup is specific to a quartus design. Generate handoff files from
> +the design. Pass them to a python script to produce a handoff.h file. This is
> +needed as input for building the device-tree for u-boot. Eventually, building
> +the final u-boot depends on the particular Quartus design, the particular
> +carrier board, the selected boot media and boot mode.
> +
> +Enclustra provides reference design examples which can be built with yocto
> +using their meta-layer.
> +
> +- Reference Design AA1 on ST1: https://github.com/enclustra/Mercury_AA1_ST1_Reference_Design
> +- Reference Design AA1 on PE1: https://github.com/enclustra/Mercury_AA1_PE1_Reference_Design
> +- Reference Design AA1 on PE3: https://github.com/enclustra/Mercury_AA1_PE3_Reference_Design
> +- Yocto meta-layer: https://github.com/enclustra/meta-enclustra-socfpga

OpenEmbedded .

> +Quick Start
> +-----------
> +
> +- Setup and build a Quartus design project
> +- Obtain the hps.xml file from the Quartus design project
> +- Generate the handoff.h file for u-boot
> +- Adjust the device-tree file according to your setup
> +- Build u-boot
> +- Flash u-boot
> +
> +Build U-Boot
> +------------
> +
> +The Quartus design produces a design specific ``hps.xml``, an ``emif.xml`` and
> +a corresponding ``id`` file contained in a folder ``handoff``.

s@folder@directory@ on unix systems.

[...]

> +.. code-block:: bash
> +
> +    $ sudo fdisk /dev/sda
> +        n,p,1,2048,+20M
> +        t,1,c
> +        n,p,2,409600,+1M
> +        t,2,a2
> +        n,p,3,425984,<REST>
> +        t,3,83
> +        w

Have a look at 'sfdisk' tool, scriptable fdisk , that is preferable .

[...]

> +Boot Media
> +----------
> +
> +Alternative boot media are possible as officially documented by Enclustra.
> +
> +* Micro-SD card
> +* eMMC
> +* QSPI
> +
> +NB: eMMC and QSPI can be flashed from off the u-boot shell. Usually after

What does 'NB:' stand for ?

> +flashing, the coorect boot mode needs to be set by a BSEL switch. Approaches
> +are described consistently in the offical Enclustra documentation according to

"official", typo, run the docs through e.g. aspell to catch those typos.

[...]

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Marek Vasut]

On 9/12/24 8:06 AM, Lothar Rubusch wrote:
> Introduce device-tree files for Enclustra Intel AA1 SoMs and related
> support.
> 
> - Mercury AA1
> 
> The setup depends on a selected boot mode. Various fragments for SD/MMC
> and QSPI flash boot are provided.
> 
> In combination, the following Enclustra carrier boards are supported:
> 
> - ST1
> - PE1
> - PE3
> 
> Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
> Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> ---
>   arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi    |  14 +
>   arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi    |  14 +
>   arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi    |  15 +
>   arch/arm/dts/Makefile                         |   2 +
>   arch/arm/dts/enclustra-aa1.dts                |  32 ++
>   .../dts/socfpga_arria10_mercury_aa1_handoff.h | 307 ++++++++++++++++++
>   .../dts/socfpga_enclustra_mercury_aa1.dtsi    | 179 ++++++++++
>   ...cfpga_enclustra_mercury_aa1_qspi_boot.dtsi |  18 +
>   ...fpga_enclustra_mercury_aa1_sdmmc_boot.dtsi |  18 +
>   .../dts/socfpga_enclustra_mercury_pe1.dtsi    |   7 +
>   .../dts/socfpga_enclustra_mercury_pe3.dtsi    |   8 +
>   .../dts/socfpga_enclustra_mercury_st1.dtsi    |   8 +
Is there any chance to upstream these DTs to Linux first , and then let 
them all trickle into U-Boot through dts/upstream/ ?

Re: [PATCH 8/9] ARM: socfpga: add si5338 clock generator support

[Marek Vasut]

On 9/12/24 8:06 AM, Lothar Rubusch wrote:
> The si5338 clock generator is needed on some Enclustra Socfpga SoMs.
> Introduce minimal support of this device.
> 
> Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> ---
>   drivers/clk/Kconfig                          |   1 +
>   drivers/clk/Makefile                         |   1 +
>   drivers/clk/skyworks/Kconfig                 |  10 +
>   drivers/clk/skyworks/Makefile                |   3 +
>   drivers/clk/skyworks/Si5338-RevB-Registers.h | 441 +++++++++++++++++++

Is there a matching Linux driver which could be imported instead ?

Re: [PATCH 8/9] ARM: socfpga: add si5338 clock generator support

[Lothar Rubusch]

On Fri, Sep 13, 2024 at 1:12 AM Marek Vasut <marex@denx.de> wrote:
>
> On 9/12/24 8:06 AM, Lothar Rubusch wrote:
> > The si5338 clock generator is needed on some Enclustra Socfpga SoMs.
> > Introduce minimal support of this device.
> >
> > Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> > ---
> >   drivers/clk/Kconfig                          |   1 +
> >   drivers/clk/Makefile                         |   1 +
> >   drivers/clk/skyworks/Kconfig                 |  10 +
> >   drivers/clk/skyworks/Makefile                |   3 +
> >   drivers/clk/skyworks/Si5338-RevB-Registers.h | 441 +++++++++++++++++++
>
> Is there a matching Linux driver which could be imported instead ?

Well, not that I'm aware of. To be honest, I removed the si5338
related patches. I'm unsure about the approach. The idea is to
initialize the clock generator. This is supposed to be done as early
as possible. So, at Enclustra u-boot/spl or similar would be
preferable. In case I'll present this separately.

Re: [PATCH 1/9] doc: board: enclustra: add Enclustra Intel AA1 SoM

[Lothar Rubusch]

On Fri, Sep 13, 2024 at 1:11 AM Marek Vasut <marex@denx.de> wrote:
>
> On 9/12/24 8:06 AM, Lothar Rubusch wrote:
> [...]
>
> > +Mercury AA1 Module (Arria1 10)
> > +==============================
> > +
> > +- SoM: https://www.enclustra.com/en/products/system-on-chip-modules/mercury-aa1/
> > +- Carrier board Mercury+ ST1: https://www.enclustra.com/en/products/base-boards/mercury-st1/
> > +- Carrier board Mercury+ PE1: https://www.enclustra.com/en/products/base-boards/mercury-pe1-200-300-400/
> > +- Carrier board Mercury+ PE3: https://www.enclustra.com/en/products/base-boards/mercury-pe3/
> > +
> > +There are slightly different variants of the AA1 SoM, going by the identifier.
> > +
> > +- Me-aa1-270-2i2-d11e-nfx3
> > +- Me-aa1-270-3e4-d11e-nfx3
> > +- Me-aa1-480-2i3-d12e-nfx3
> > +
> > +The u-boot setup is specific to a quartus design. Generate handoff files from
> > +the design. Pass them to a python script to produce a handoff.h file. This is
> > +needed as input for building the device-tree for u-boot. Eventually, building
> > +the final u-boot depends on the particular Quartus design, the particular
> > +carrier board, the selected boot media and boot mode.
> > +
> > +Enclustra provides reference design examples which can be built with yocto
> > +using their meta-layer.
> > +
> > +- Reference Design AA1 on ST1: https://github.com/enclustra/Mercury_AA1_ST1_Reference_Design
> > +- Reference Design AA1 on PE1: https://github.com/enclustra/Mercury_AA1_PE1_Reference_Design
> > +- Reference Design AA1 on PE3: https://github.com/enclustra/Mercury_AA1_PE3_Reference_Design
> > +- Yocto meta-layer: https://github.com/enclustra/meta-enclustra-socfpga
>
> OpenEmbedded .
>

Ok

> > +Quick Start
> > +-----------
> > +
> > +- Setup and build a Quartus design project
> > +- Obtain the hps.xml file from the Quartus design project
> > +- Generate the handoff.h file for u-boot
> > +- Adjust the device-tree file according to your setup
> > +- Build u-boot
> > +- Flash u-boot
> > +
> > +Build U-Boot
> > +------------
> > +
> > +The Quartus design produces a design specific ``hps.xml``, an ``emif.xml`` and
> > +a corresponding ``id`` file contained in a folder ``handoff``.
>
> s@folder@directory@ on unix systems.
>

Ok

> [...]
>
> > +.. code-block:: bash
> > +
> > +    $ sudo fdisk /dev/sda
> > +        n,p,1,2048,+20M
> > +        t,1,c
> > +        n,p,2,409600,+1M
> > +        t,2,a2
> > +        n,p,3,425984,<REST>
> > +        t,3,83
> > +        w
>
> Have a look at 'sfdisk' tool, scriptable fdisk , that is preferable .
>

Ok, ich changed it using sfdisk

> [...]
>
> > +Boot Media
> > +----------
> > +
> > +Alternative boot media are possible as officially documented by Enclustra.
> > +
> > +* Micro-SD card
> > +* eMMC
> > +* QSPI
> > +
> > +NB: eMMC and QSPI can be flashed from off the u-boot shell. Usually after
>
> What does 'NB:' stand for ?
>

I'll change this for "Note:"

> > +flashing, the coorect boot mode needs to be set by a BSEL switch. Approaches
> > +are described consistently in the offical Enclustra documentation according to
>
> "official", typo, run the docs through e.g. aspell to catch those typos.
>

Thank you for the review and the hints. I'll apply the changes in the
next version of this set.

> [...]

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Lothar Rubusch]

On Fri, Sep 13, 2024 at 1:11 AM Marek Vasut <marex@denx.de> wrote:
>
> On 9/12/24 8:06 AM, Lothar Rubusch wrote:
> > Introduce device-tree files for Enclustra Intel AA1 SoMs and related
> > support.
> >
> > - Mercury AA1
> >
> > The setup depends on a selected boot mode. Various fragments for SD/MMC
> > and QSPI flash boot are provided.
> >
> > In combination, the following Enclustra carrier boards are supported:
> >
> > - ST1
> > - PE1
> > - PE3
> >
> > Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
> > Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> > ---
> >   arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi    |  14 +
> >   arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi    |  14 +
> >   arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi    |  15 +
> >   arch/arm/dts/Makefile                         |   2 +
> >   arch/arm/dts/enclustra-aa1.dts                |  32 ++
> >   .../dts/socfpga_arria10_mercury_aa1_handoff.h | 307 ++++++++++++++++++
> >   .../dts/socfpga_enclustra_mercury_aa1.dtsi    | 179 ++++++++++
> >   ...cfpga_enclustra_mercury_aa1_qspi_boot.dtsi |  18 +
> >   ...fpga_enclustra_mercury_aa1_sdmmc_boot.dtsi |  18 +
> >   .../dts/socfpga_enclustra_mercury_pe1.dtsi    |   7 +
> >   .../dts/socfpga_enclustra_mercury_pe3.dtsi    |   8 +
> >   .../dts/socfpga_enclustra_mercury_st1.dtsi    |   8 +
> Is there any chance to upstream these DTs to Linux first , and then let
> them all trickle into U-Boot through dts/upstream/ ?

This is the tricky one. In principle, as it is supposed to be build on
our side this is not the case. For the kernel, we prefer to work with
DT overlays (.dtbo) where on the u-boot side we only need some basic
functionality and not everything declared. So, currently there are
differences.

Another point here for me to understand would be the following. If I
upstream some DT files to  the kernel it might take time until they go
to anything released there. So, upstreaming u-boot would wait on that
kernel release, right? In such case, I really prefer to upstream the
DT files as is to u-boot first. Then / In parallel try  to upstream
the files to the kernel. And update the u-boot DT set to point to the
kernel DT files when they are released. Could this be an approach?

Anyway, it might be that next week, I might discuss that directly in
person to get a better idea what could be a way for me with those
u-boot files. I'm coming back to this topic then. If you find some
time, please let me know what you think about it.

Re: [PATCH 3/9] ARM: socfpga: add Enclustra AA1 SoM support

[Lothar Rubusch]

On Thu, Sep 12, 2024 at 7:45 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Thu, Sep 12, 2024 at 06:06:43AM +0000, Lothar Rubusch wrote:
>
> > Introduce initial support for the Enclustra SoMs:
> >
> > - Mercury AA1
> >
> > Cover general board files for SD/MMC and QSPI boot modes. Integrate the
> > boards to kconfig. All build variants will depend on Quartus handoff
> > files, thus they depend on the particular Quartus design. The approach is
> > covered in the according documentation part.
> >
> > Additionally add configuration for SD/MMC boot and QSPI bootmodes. Register
> > additional targets in kconfig.
> >
> > Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
> > Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> [snip]
> > diff --git a/board/enclustra/mercury_aa1/mercury_aa1.c b/board/enclustra/mercury_aa1/mercury_aa1.c
> > new file mode 100644
> > index 0000000000..7de9b287d9
> > --- /dev/null
> > +++ b/board/enclustra/mercury_aa1/mercury_aa1.c
> > @@ -0,0 +1,185 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2024 Enclustra GmbH
> > + * <info@enclustra.com>
> > + */
> > +
> > +#include <command.h>
> > +#include <env.h>
> > +#include <init.h>
> > +#include <dm/uclass.h>
> > +#include <asm-generic/gpio.h>
> > +#include <asm/io.h>
> > +
> > +/* Pin muxing */
> > +#if !defined(CONFIG_SPL_BUILD)
> > +
> > +#define ALTERA_NONE 0
> > +#define ALTERA_MMC 1
> > +#define ALTERA_QSPI 2
> > +#define ALTERA_EMMC 3
> > +#define MMC_CLK_DIV 0x9
> > +#define QSPI_CLK_DIV 0x384
> > +#define ALTERA_PINMUX_OFFS 0xffd07200
> > +#define ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE 0xFFD04078
> > +
> > +static int altera_current_storage = ALTERA_NONE;
> > +
> > +#endif
> > +
> > +#if !defined(CONFIG_SPL_BUILD)
> > +
> > +static void set_mux_mmc(void)
> > +{
> > +     u32 pinmux_arr[] = {0x0c, 0x8,  // IO4 connected to SDMMC
> > +                     0x10, 0x8,      // IO5
> > +                     0x14, 0x8,      // IO6
> > +                     0x18, 0x8,      // IO7
> > +                     0x1c, 0x8,      // IO8
> > +                     0x20, 0x8,      // IO9
> > +                     0x24, 0xf,      // IO10 connected to GPIO
> > +                     0x28, 0xf,      // IO11
> > +                     0x2c, 0xf,      // IO12
> > +                     0x30, 0xf,      // IO13
> > +                     0x34, 0xf,      // IO14
> > +                     0x38, 0xf};     // IO15
> > +     u32 len, i, offset, value;
> > +
> > +     len = sizeof(pinmux_arr) / sizeof(u32);
> > +     for (i = 0; i < len; i += 2) {
> > +             offset = pinmux_arr[i];
> > +             value = pinmux_arr[i + 1];
> > +             writel(value, ALTERA_PINMUX_OFFS + offset);
> > +     }
> > +}
> > +
> > +static void set_mux_emmc(void)
> > +{
> > +     u32 pinmux_arr[] = {0x0c, 0x8,  // IO4
> > +             0x10, 0x8,      // IO5
> > +             0x14, 0x8,      // IO6
> > +             0x18, 0x8,      // IO7
> > +             0x1c, 0x8,      // IO8
> > +             0x20, 0x8,      // IO9
> > +             0x24, 0xf,      // IO10
> > +             0x28, 0xf,      // IO11
> > +             0x2c, 0x8,      // IO12
> > +             0x30, 0x8,      // IO13
> > +             0x34, 0x8,      // IO14
> > +             0x38, 0x8};     // IO15
> > +     u32 len, i, offset, value;
> > +
> > +     len = sizeof(pinmux_arr) / sizeof(u32);
> > +     for (i = 0; i < len; i += 2) {
> > +             offset = pinmux_arr[i];
> > +             value = pinmux_arr[i + 1];
> > +             writel(value, ALTERA_PINMUX_OFFS + offset);
> > +     }
> > +}
> > +
> > +static void set_mux_qspi(void)
> > +{
> > +     u32 pinmux_arr[] = {0x0c, 0x4,  // IO4 connected to QSPI
> > +             0x10, 0x4,      // IO5
> > +             0x14, 0x4,      // IO6
> > +             0x18, 0x4,      // IO7
> > +             0x1c, 0x4,      // IO8
> > +             0x20, 0x4,      // IO9
> > +             0x24, 0xf,      // IO10
> > +             0x28, 0xf,      // IO11
> > +             0x2c, 0xf,      // IO12
> > +             0x30, 0xf,      // IO13
> > +             0x34, 0xf,      // IO14
> > +             0x38, 0xf};     // IO15
> > +     u32 len, i, offset, value;
> > +
> > +     len = sizeof(pinmux_arr) / sizeof(u32);
> > +     for (i = 0; i < len; i += 2) {
> > +             offset = pinmux_arr[i];
> > +             value = pinmux_arr[i + 1];
> > +             writel(value, ALTERA_PINMUX_OFFS + offset);
> > +     }
> > +}
> > +
> > +void altera_set_storage(int store)
>
> Should be static?
>
> > +{
> > +     unsigned int gpio_flash_sel;
> > +     unsigned int gpio_flash_oe;
> > +
> > +     if (store == altera_current_storage)
> > +             return;
> > +
> > +     if (gpio_lookup_name("portb5", NULL, NULL, &gpio_flash_oe)) {
> > +             printf("ERROR: GPIO not found\n");
> > +             return;
> > +     }
> > +
> > +     if (gpio_request(gpio_flash_oe, "flash_oe")) {
> > +             printf("ERROR: GPIO request failed\n");
> > +             return;
> > +     }
> > +
> > +     if (gpio_lookup_name("portc6", NULL, NULL, &gpio_flash_sel)) {
> > +             printf("ERROR: GPIO not found\n");
> > +             return;
> > +     }
> > +
> > +     if (gpio_request(gpio_flash_sel, "flash_sel")) {
> > +             printf("ERROR: GPIO request failed\n");
> > +             return;
> > +     }
> > +
> > +     switch (store) {
> > +     case ALTERA_MMC:
> > +             set_mux_mmc();
> > +             gpio_direction_output(gpio_flash_sel, 0);
> > +             gpio_direction_output(gpio_flash_oe, 0);
> > +             altera_current_storage = ALTERA_MMC;
> > +             writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
> > +             break;
> > +     case ALTERA_EMMC:
> > +             set_mux_emmc();
> > +             gpio_direction_output(gpio_flash_sel, 1);
> > +             gpio_direction_output(gpio_flash_oe, 1);
> > +             altera_current_storage = ALTERA_EMMC;
> > +             writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
> > +             break;
> > +     case ALTERA_QSPI:
> > +             set_mux_qspi();
> > +             gpio_direction_output(gpio_flash_sel, 1);
> > +             gpio_direction_output(gpio_flash_oe, 0);
> > +             altera_current_storage = ALTERA_QSPI;
> > +             writel(QSPI_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
> > +             break;
> > +     default:
> > +             altera_current_storage = ALTERA_NONE;
> > +             break;
> > +     }
> > +
> > +     gpio_free(gpio_flash_sel);
> > +     gpio_free(gpio_flash_oe);
> > +}
> > +
> > +int altera_set_storage_cmd(struct cmd_tbl *cmdtp, int flag,
> > +                        int argc, char * const argv[])
>
> Same?
>
> > +{
> > +     if (argc != 2)
> > +             return CMD_RET_USAGE;
> > +
> > +     if (!strcmp(argv[1], "MMC"))
> > +             altera_set_storage(ALTERA_MMC);
> > +     else if (!strcmp(argv[1], "QSPI"))
> > +             altera_set_storage(ALTERA_QSPI);
> > +     else if (!strcmp(argv[1], "EMMC"))
> > +             altera_set_storage(ALTERA_EMMC);
> > +     else
> > +             return CMD_RET_USAGE;
> > +
> > +     return CMD_RET_SUCCESS;
> > +}
> > +
> > +U_BOOT_CMD(altera_set_storage, 2, 0, altera_set_storage_cmd,
> > +        "Set non volatile memory access",
> > +        "<MMC|QSPI|EMMC> - Set access for the selected memory device");
> > +
> > +#endif
>
(...)
> The entire file seems to be for just adding the cmd. Perhaps rename this
> file to reflect that and have the Makefile only even build this when
> CONFIG_SPL_BUILD is not set.

Agree. I applied the above changes/fixed the above mentioned issues.
It looks cleaner now. I prepare this in the next version of
this patch set. Thank you for the hint. I would name it as
aa1_set_storage_cmd() is this ok?

(...)
> Also, the MAINTAINERS entry doesn't cover the documentation (which I'm
> glad to see being added at the start!) nor the clock driver.

Added.

Re: [PATCH 3/9] ARM: socfpga: add Enclustra AA1 SoM support

[Tom Rini]

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On Sat, Sep 14, 2024 at 10:03:02PM +0200, Lothar Rubusch wrote:
> On Thu, Sep 12, 2024 at 7:45 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Thu, Sep 12, 2024 at 06:06:43AM +0000, Lothar Rubusch wrote:
> >
> > > Introduce initial support for the Enclustra SoMs:
> > >
> > > - Mercury AA1
> > >
> > > Cover general board files for SD/MMC and QSPI boot modes. Integrate the
> > > boards to kconfig. All build variants will depend on Quartus handoff
> > > files, thus they depend on the particular Quartus design. The approach is
> > > covered in the according documentation part.
> > >
> > > Additionally add configuration for SD/MMC boot and QSPI bootmodes. Register
> > > additional targets in kconfig.
> > >
> > > Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
> > > Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> > [snip]
[snip]
> > > +U_BOOT_CMD(altera_set_storage, 2, 0, altera_set_storage_cmd,
> > > +        "Set non volatile memory access",
> > > +        "<MMC|QSPI|EMMC> - Set access for the selected memory device");
> > > +
> > > +#endif
> >
> > The entire file seems to be for just adding the cmd. Perhaps rename this
> > file to reflect that and have the Makefile only even build this when
> > CONFIG_SPL_BUILD is not set.
> 
> Agree. It looks cleaner now. I prepare this in the next version of
> this patch set. Thank you for the hint. I would name it as
> aa1_set_storage_cmd() is this ok?

Yes, the name sounds fine. Thanks!

-- 
Tom

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Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Lothar Rubusch]

First of all a huge thank you for the time you spend in reviewing the
patches so far. This is highly appreciate!!


On Fri, Sep 13, 2024 at 1:11 AM Marek Vasut <marex@denx.de> wrote:
[...]
> Is there any chance to upstream these DTs to Linux first , and then let
> them all trickle into U-Boot through dts/upstream/ ?

Preparing the DTS patches for Linux kernel, I noticed I will need the
handoff setup for u-boot. AFAIK there is currently no single handoff.h
or handoff.dtsi file in the kernel repo.

Shall I add the files to my DTS patches and ask for upstreaming of the
handoff files into the kernel?

Example:
In specific for u-boot I need a .dts setup like this. Those files are
currently not in the kernel:
    #include "socfpga_arria10_mercury_aa1_handoff.h"
    #include "socfpga_arria10-handoff.dtsi"
    #include "socfpga_arria10_handoff_u-boot.dtsi"
    ...

Since this seems to be common for all socfpga setups (arria10 and
cyclone5), I guess the situation is already known by a common
approach. How to deal with this situation in u-boot dts/upstream?

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Marek Vasut]

On 9/26/24 12:49 AM, Lothar Rubusch wrote:

Hi,

> First of all a huge thank you for the time you spend in reviewing the
> patches so far. This is highly appreciate!!
> 
> 
> On Fri, Sep 13, 2024 at 1:11 AM Marek Vasut <marex@denx.de> wrote:
> [...]
>> Is there any chance to upstream these DTs to Linux first , and then let
>> them all trickle into U-Boot through dts/upstream/ ?
> 
> Preparing the DTS patches for Linux kernel, I noticed I will need the
> handoff setup for u-boot. AFAIK there is currently no single handoff.h
> or handoff.dtsi file in the kernel repo.
> 
> Shall I add the files to my DTS patches and ask for upstreaming of the
> handoff files into the kernel?

Are the handoff files really used by Linux for anything , or do they 
contain various clock/pinmux/DRAM settings only used by U-Boot ? If the 
later, place them into U-Boot and include them from -u-boot.dtsi file.

> Example:
> In specific for u-boot I need a .dts setup like this. Those files are
> currently not in the kernel:
>      #include "socfpga_arria10_mercury_aa1_handoff.h"
>      #include "socfpga_arria10-handoff.dtsi"
>      #include "socfpga_arria10_handoff_u-boot.dtsi"
>      ...
> 
> Since this seems to be common for all socfpga setups (arria10 and
> cyclone5), I guess the situation is already known by a common
> approach. How to deal with this situation in u-boot dts/upstream?

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Lothar Rubusch]

On Thu, Sep 26, 2024 at 3:36 AM Marek Vasut <marex@denx.de> wrote:
>
> On 9/26/24 12:49 AM, Lothar Rubusch wrote:
>
> Hi,
[...]
> > Shall I add the files to my DTS patches and ask for upstreaming of the
> > handoff files into the kernel?
>
> Are the handoff files really used by Linux for anything , or do they
> contain various clock/pinmux/DRAM settings only used by U-Boot ? If the
> later, place them into U-Boot and include them from -u-boot.dtsi file.

Similar to the other socfpga targets, the handoff files are just
relevant to u-boot. So, I'll keep them in arch/arm/dts.

My particular situation then is as follows. The .dts file just
includes several .dtsi files. I place this .dts file into
arch/arm/dts. The first includes contain the "handoff setup". Then I
include adjustments (.dtsi fragments) to the selected base-board and
boot-mode. Both  can vary that's why I really would prefer to allow
for a Kconfig option on that, in contrary to provide a set of .dts
files for all possible combinations.

Example:
$ cat ./arch/arm/dts/socfpga_arria10_mercury_aa1_pe1_sdmmc-u-boot.dts
/dts-v1/;
/* will be taken from /arch/arm/dts */
#include "socfpga_arria10_mercury_aa1_handoff.h"
#include "socfpga_arria10-handoff.dtsi"
#include "socfpga_arria10_handoff_u-boot.dtsi"

/* will be taken from /dts/upstream */
#include "../../../dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi"
#include "../../../dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
#include "../../../dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi"

Ideally, now I like to have the first part as default device tree.
DEFAULT_DEVICE_TREE=socfpga_arria10_mercury_aa1_pe1_sdmmc-u-boot.dts
When doing so, I noticed I cannot enable CONFIG_OF_UPSTREAM anymore,
the files in arch/arm/dts won't be found anymore.
Then I have the issue how to access the generic .dtsi files used for
boot-mode or base board. These files are identical to the kernel DT
why I would prefer to use them from dts/upstream. Including them like
../../../../../... works, but... I think there must be a better way.
Ideally I like to setup some Kconfig choice for base board selection
and one for boot-mode.

1.) In the documentation control.rst I read that the u-boot.dts is
combined of several elements. Is there a way to take this base .dts,
then add a base board .dtsi by Kconfig option, and similar a
boot-mode?

2.) Is there a way to enable CONFIG_OF_UPSTREAM and use explicit DTS
from arch/arm/dts for the u-boot?

3.) What would be the best possibility to have a u-boot.dts with
handoff setup in arch/arm/dts and append .dtsi files from the general
dts/upstream - in case are there other boards are doing something
similar?

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Marek Vasut]

On 9/27/24 12:53 AM, Lothar Rubusch wrote:
> On Thu, Sep 26, 2024 at 3:36 AM Marek Vasut <marex@denx.de> wrote:
>>
>> On 9/26/24 12:49 AM, Lothar Rubusch wrote:
>>
>> Hi,
> [...]
>>> Shall I add the files to my DTS patches and ask for upstreaming of the
>>> handoff files into the kernel?
>>
>> Are the handoff files really used by Linux for anything , or do they
>> contain various clock/pinmux/DRAM settings only used by U-Boot ? If the
>> later, place them into U-Boot and include them from -u-boot.dtsi file.
> 
> Similar to the other socfpga targets, the handoff files are just
> relevant to u-boot. So, I'll keep them in arch/arm/dts.

Right

> My particular situation then is as follows. The .dts file just
> includes several .dtsi files. I place this .dts file into
> arch/arm/dts. The first includes contain the "handoff setup". Then I
> include adjustments (.dtsi fragments) to the selected base-board and
> boot-mode. Both  can vary that's why I really would prefer to allow
> for a Kconfig option on that, in contrary to provide a set of .dts
> files for all possible combinations.
> 
> Example:
> $ cat ./arch/arm/dts/socfpga_arria10_mercury_aa1_pe1_sdmmc-u-boot.dts

Upstream DT named this way into Linux:

socfpga_arria10_mercury_aa1_pe1_sdmmc.dts

And then in U-Boot, implement the extras which include whatever you 
need, name the file:

socfpga_arria10_mercury_aa1_pe1_sdmmc-u-boot.dtsi

The U-Boot build system will combine the two DTs, the build system 
should automatically append matching -u-boot.dtsi content to any .dts file.

I am not sure if this also works if the .dts file is in dts/upstream/* 
while the -u-boot.dtsi is in arch/*/dts/ , but there is now definitely a 
use case for such a setup, it is probably a matter of tweaking the 
Makefiles .

> /dts-v1/;
> /* will be taken from /arch/arm/dts */
> #include "socfpga_arria10_mercury_aa1_handoff.h"
> #include "socfpga_arria10-handoff.dtsi"
> #include "socfpga_arria10_handoff_u-boot.dtsi"
> 
> /* will be taken from /dts/upstream */
> #include "../../../dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi"
> #include "../../../dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
> #include "../../../dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi"
> 
> Ideally, now I like to have the first part as default device tree.
> DEFAULT_DEVICE_TREE=socfpga_arria10_mercury_aa1_pe1_sdmmc-u-boot.dts
> When doing so, I noticed I cannot enable CONFIG_OF_UPSTREAM anymore,
> the files in arch/arm/dts won't be found anymore.
> Then I have the issue how to access the generic .dtsi files used for
> boot-mode or base board. These files are identical to the kernel DT
> why I would prefer to use them from dts/upstream. Including them like
> ../../../../../... works, but... I think there must be a better way.

Look at how the -u-boot.dtsi are automatically added on top of .dts 
files, that might be a start.

> Ideally I like to setup some Kconfig choice for base board selection
> and one for boot-mode.

> 1.) In the documentation control.rst I read that the u-boot.dts is
> combined of several elements. Is there a way to take this base .dts,
> then add a base board .dtsi by Kconfig option, and similar a
> boot-mode?

The -u-boot.dtsi is preprocessed by C preprocessor, just like all the 
other DTs, so you can have a -u-boot.dtsi file which contains C 
preprocessor conditional statements in it to conditionally include other 
.dtsi files:

#if IS_ENABLED(...)
#include ...
#else ...
...
#endif

> 2.) Is there a way to enable CONFIG_OF_UPSTREAM and use explicit DTS
> from arch/arm/dts for the u-boot?

This I do not know.

> 3.) What would be the best possibility to have a u-boot.dts with
> handoff setup in arch/arm/dts and append .dtsi files from the general
> dts/upstream - in case are there other boards are doing something
> similar?

See above, maybe some of it helps.

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Lothar Rubusch]

On Fri, Sep 27, 2024 at 1:19 AM Marek Vasut <marex@denx.de> wrote:
>
> On 9/27/24 12:53 AM, Lothar Rubusch wrote:
> > On Thu, Sep 26, 2024 at 3:36 AM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 9/26/24 12:49 AM, Lothar Rubusch wrote:
> >>
> >> Hi,
> > [...]
> >>> Shall I add the files to my DTS patches and ask for upstreaming of the
> >>> handoff files into the kernel?
> >>
> >> Are the handoff files really used by Linux for anything , or do they
> >> contain various clock/pinmux/DRAM settings only used by U-Boot ? If the
> >> later, place them into U-Boot and include them from -u-boot.dtsi file.
> >
> > Similar to the other socfpga targets, the handoff files are just
> > relevant to u-boot. So, I'll keep them in arch/arm/dts.
>
> Right
>
> > My particular situation then is as follows. The .dts file just
> > includes several .dtsi files. I place this .dts file into
> > arch/arm/dts. The first includes contain the "handoff setup". Then I
> > include adjustments (.dtsi fragments) to the selected base-board and
> > boot-mode. Both  can vary that's why I really would prefer to allow
> > for a Kconfig option on that, in contrary to provide a set of .dts
> > files for all possible combinations.
> >
> > Example:
> > $ cat ./arch/arm/dts/socfpga_arria10_mercury_aa1_pe1_sdmmc-u-boot.dts
>
> Upstream DT named this way into Linux:
>
> socfpga_arria10_mercury_aa1_pe1_sdmmc.dts
>
> And then in U-Boot, implement the extras which include whatever you
> need, name the file:
>
> socfpga_arria10_mercury_aa1_pe1_sdmmc-u-boot.dtsi
>
> The U-Boot build system will combine the two DTs, the build system
> should automatically append matching -u-boot.dtsi content to any .dts file.
>
> I am not sure if this also works if the .dts file is in dts/upstream/*
> while the -u-boot.dtsi is in arch/*/dts/ , but there is now definitely a
> use case for such a setup, it is probably a matter of tweaking the
> Makefiles .
>
> > /dts-v1/;
> > /* will be taken from /arch/arm/dts */
> > #include "socfpga_arria10_mercury_aa1_handoff.h"
> > #include "socfpga_arria10-handoff.dtsi"
> > #include "socfpga_arria10_handoff_u-boot.dtsi"
> >
> > /* will be taken from /dts/upstream */
> > #include "../../../dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi"
> > #include "../../../dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
> > #include "../../../dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi"
> >
> > Ideally, now I like to have the first part as default device tree.
> > DEFAULT_DEVICE_TREE=socfpga_arria10_mercury_aa1_pe1_sdmmc-u-boot.dts
> > When doing so, I noticed I cannot enable CONFIG_OF_UPSTREAM anymore,
> > the files in arch/arm/dts won't be found anymore.
> > Then I have the issue how to access the generic .dtsi files used for
> > boot-mode or base board. These files are identical to the kernel DT
> > why I would prefer to use them from dts/upstream. Including them like
> > ../../../../../... works, but... I think there must be a better way.
>
> Look at how the -u-boot.dtsi are automatically added on top of .dts
> files, that might be a start.
>
> > Ideally I like to setup some Kconfig choice for base board selection
> > and one for boot-mode.
>
> > 1.) In the documentation control.rst I read that the u-boot.dts is
> > combined of several elements. Is there a way to take this base .dts,
> > then add a base board .dtsi by Kconfig option, and similar a
> > boot-mode?
>
> The -u-boot.dtsi is preprocessed by C preprocessor, just like all the
> other DTs, so you can have a -u-boot.dtsi file which contains C
> preprocessor conditional statements in it to conditionally include other
> .dtsi files:
>
> #if IS_ENABLED(...)
> #include ...
> #else ...
> ...
> #endif

Going through the include list setup by the Makefile made me find my
mistake. Currently I may use u-boot specific stuff in arch/arm/dts and
include generic .dtsi fragments from dts/upstream. Note: I'm not
setting CONFIG_OF_UPSTREAM since I'm using the regular include list
which already contains dts/upstream/src/arm/intel. Is this ok? Or,
shall I try a different approach, which involves having
CONFIG_OF_UPSTREAM explicitely set in the defconfig?

> > 3.) What would be the best possibility to have a u-boot.dts with
> > handoff setup in arch/arm/dts and append .dtsi files from the general
> > dts/upstream - in case are there other boards are doing something
> > similar?
>
> See above, maybe some of it helps.

Yes. This helped. I can set base-board and boot mode now by Kconfig
option with a generic .dts file. Note, it may still take some time,
since I'd like to test the stuff still a bit on hardware before
submitting something to the list.

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Marek Vasut]

On 9/28/24 12:47 AM, Lothar Rubusch wrote:

[...]

>>> Ideally I like to setup some Kconfig choice for base board selection
>>> and one for boot-mode.
>>
>>> 1.) In the documentation control.rst I read that the u-boot.dts is
>>> combined of several elements. Is there a way to take this base .dts,
>>> then add a base board .dtsi by Kconfig option, and similar a
>>> boot-mode?
>>
>> The -u-boot.dtsi is preprocessed by C preprocessor, just like all the
>> other DTs, so you can have a -u-boot.dtsi file which contains C
>> preprocessor conditional statements in it to conditionally include other
>> .dtsi files:
>>
>> #if IS_ENABLED(...)
>> #include ...
>> #else ...
>> ...
>> #endif
> 
> Going through the include list setup by the Makefile made me find my
> mistake. Currently I may use u-boot specific stuff in arch/arm/dts and
> include generic .dtsi fragments from dts/upstream. Note: I'm not
> setting CONFIG_OF_UPSTREAM since I'm using the regular include list
> which already contains dts/upstream/src/arm/intel. Is this ok? Or,
> shall I try a different approach, which involves having
> CONFIG_OF_UPSTREAM explicitely set in the defconfig?

I'm not quite sure I understand the question. Once this platform DTs 
land in mainline and the DTs get synchronized into U-Boot, you should 
then set CONFIG_OF_UPSTREAM. Until then, you could patch the DTs into 
dts/upstream/ to test the result with OF_UPSTREAM enabled .

>>> 3.) What would be the best possibility to have a u-boot.dts with
>>> handoff setup in arch/arm/dts and append .dtsi files from the general
>>> dts/upstream - in case are there other boards are doing something
>>> similar?
>>
>> See above, maybe some of it helps.
> 
> Yes. This helped. I can set base-board and boot mode now by Kconfig
> option with a generic .dts file. Note, it may still take some time,
> since I'd like to test the stuff still a bit on hardware before
> submitting something to the list.

Sure

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Lothar Rubusch]

On Sun, Sep 29, 2024 at 6:55 PM Marek Vasut <marex@denx.de> wrote:
>
> On 9/28/24 12:47 AM, Lothar Rubusch wrote:
>
> [...]
>
> >>> Ideally I like to setup some Kconfig choice for base board selection
> >>> and one for boot-mode.
> >>
> >>> 1.) In the documentation control.rst I read that the u-boot.dts is
> >>> combined of several elements. Is there a way to take this base .dts,
> >>> then add a base board .dtsi by Kconfig option, and similar a
> >>> boot-mode?
> >>
> >> The -u-boot.dtsi is preprocessed by C preprocessor, just like all the
> >> other DTs, so you can have a -u-boot.dtsi file which contains C
> >> preprocessor conditional statements in it to conditionally include other
> >> .dtsi files:
> >>
> >> #if IS_ENABLED(...)
> >> #include ...
> >> #else ...
> >> ...
> >> #endif
> >
> > Going through the include list setup by the Makefile made me find my
> > mistake. Currently I may use u-boot specific stuff in arch/arm/dts and
> > include generic .dtsi fragments from dts/upstream. Note: I'm not
> > setting CONFIG_OF_UPSTREAM since I'm using the regular include list
> > which already contains dts/upstream/src/arm/intel. Is this ok? Or,
> > shall I try a different approach, which involves having
> > CONFIG_OF_UPSTREAM explicitely set in the defconfig?
>
> I'm not quite sure I understand the question. Once this platform DTs
> land in mainline and the DTs get synchronized into U-Boot, you should
> then set CONFIG_OF_UPSTREAM. Until then, you could patch the DTs into
> dts/upstream/ to test the result with OF_UPSTREAM enabled .
>

Ah, sorry. I did not explain well. Currently I patch the DTs which
should go to kernel/mainline into my local u-boot:
dts/upstream/src/arm/intel/socfpga/ as a preparation for my test
builds.

For U-boot I will need to build a devicetree file from archarm/dts. I
cannot rely just on the upstream fragments for u-boot. Imagine
settings like initial fpga bitstream loading, handoff file setup for
initialization, etc. In parts I may use .dtsi files from dts/upstream,
though, but most of the u-boot particular devicetree setup will reside
in arch/arm/dts, I guess (you may see later in the patches).

I noticed when setting the option CONFIG_OF_UPSTREAM in `make
menuconfig`, it prepends `dts/upstream/` to the included paths of the
devicetree files. The resulting path for the .dts was then
dts/upstream/arch/arm/dts/ and could not be found anymore. When I
don't activate CONFIG_OF_UPSTREAM, dts/upstream is in the Makefile's
include list anyway so that I easily can include from both locations.

In conclusion, currently I'm calling a .dts for building the u-boot DT
from arch/arm/dts. The file includes upstream stuff as .dtsi fragment
from dts/upstream and handoff from local. CONFIG_OF_UPSTREAM does not
seem to be necessary in this case.

This approach currently works for me. If you strongly disagree, I may
invest more time to find a way (or why there is currently no way) with
CONFIG_OF_UPSTREAM.

This was my question about. Anyway you may wait on v3 to understand
better in source what I'm doing, or if I'm just messing around.

> >>> 3.) What would be the best possibility to have a u-boot.dts with
> >>> handoff setup in arch/arm/dts and append .dtsi files from the general
> >>> dts/upstream - in case are there other boards are doing something
> >>> similar?
> >>
> >> See above, maybe some of it helps.
> >
> > Yes. This helped. I can set base-board and boot mode now by Kconfig
> > option with a generic .dts file. Note, it may still take some time,
> > since I'd like to test the stuff still a bit on hardware before
> > submitting something to the list.
>
> Sure

I still found some bugs. When it's working (again), I'll let you guys know..

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Marek Vasut]

On 9/29/24 9:19 PM, Lothar Rubusch wrote:
> On Sun, Sep 29, 2024 at 6:55 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 9/28/24 12:47 AM, Lothar Rubusch wrote:
>>
>> [...]
>>
>>>>> Ideally I like to setup some Kconfig choice for base board selection
>>>>> and one for boot-mode.
>>>>
>>>>> 1.) In the documentation control.rst I read that the u-boot.dts is
>>>>> combined of several elements. Is there a way to take this base .dts,
>>>>> then add a base board .dtsi by Kconfig option, and similar a
>>>>> boot-mode?
>>>>
>>>> The -u-boot.dtsi is preprocessed by C preprocessor, just like all the
>>>> other DTs, so you can have a -u-boot.dtsi file which contains C
>>>> preprocessor conditional statements in it to conditionally include other
>>>> .dtsi files:
>>>>
>>>> #if IS_ENABLED(...)
>>>> #include ...
>>>> #else ...
>>>> ...
>>>> #endif
>>>
>>> Going through the include list setup by the Makefile made me find my
>>> mistake. Currently I may use u-boot specific stuff in arch/arm/dts and
>>> include generic .dtsi fragments from dts/upstream. Note: I'm not
>>> setting CONFIG_OF_UPSTREAM since I'm using the regular include list
>>> which already contains dts/upstream/src/arm/intel. Is this ok? Or,
>>> shall I try a different approach, which involves having
>>> CONFIG_OF_UPSTREAM explicitely set in the defconfig?
>>
>> I'm not quite sure I understand the question. Once this platform DTs
>> land in mainline and the DTs get synchronized into U-Boot, you should
>> then set CONFIG_OF_UPSTREAM. Until then, you could patch the DTs into
>> dts/upstream/ to test the result with OF_UPSTREAM enabled .
>>
> 
> Ah, sorry. I did not explain well. Currently I patch the DTs which
> should go to kernel/mainline into my local u-boot:
> dts/upstream/src/arm/intel/socfpga/ as a preparation for my test
> builds.

OK

> For U-boot I will need to build a devicetree file from archarm/dts. I
> cannot rely just on the upstream fragments for u-boot. Imagine
> settings like initial fpga bitstream loading, handoff file setup for
> initialization, etc. In parts I may use .dtsi files from dts/upstream,
> though, but most of the u-boot particular devicetree setup will reside
> in arch/arm/dts, I guess (you may see later in the patches).

You should be able to use dts/upstream/src/arm/intel/socfpga/ with 
-u-boot.dtsi from arch/arm/dts/ for this purpose, right ?

> I noticed when setting the option CONFIG_OF_UPSTREAM in `make
> menuconfig`, it prepends `dts/upstream/` to the included paths of the
> devicetree files. The resulting path for the .dts was then
> dts/upstream/arch/arm/dts/ and could not be found anymore. When I
> don't activate CONFIG_OF_UPSTREAM, dts/upstream is in the Makefile's
> include list anyway so that I easily can include from both locations.

+CC Sumit

> In conclusion, currently I'm calling a .dts for building the u-boot DT
> from arch/arm/dts. The file includes upstream stuff as .dtsi fragment
> from dts/upstream and handoff from local. CONFIG_OF_UPSTREAM does not
> seem to be necessary in this case.
> 
> This approach currently works for me. If you strongly disagree, I may
> invest more time to find a way (or why there is currently no way) with
> CONFIG_OF_UPSTREAM.
> 
> This was my question about. Anyway you may wait on v3 to understand
> better in source what I'm doing, or if I'm just messing around.
I'll wait for V3, sure, good luck.

Sorry for the delayed reply.

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Sumit Garg]

On Sat, 5 Oct 2024 at 07:14, Marek Vasut <marex@denx.de> wrote:
>
> On 9/29/24 9:19 PM, Lothar Rubusch wrote:
> > On Sun, Sep 29, 2024 at 6:55 PM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 9/28/24 12:47 AM, Lothar Rubusch wrote:
> >>
> >> [...]
> >>
> >>>>> Ideally I like to setup some Kconfig choice for base board selection
> >>>>> and one for boot-mode.
> >>>>
> >>>>> 1.) In the documentation control.rst I read that the u-boot.dts is
> >>>>> combined of several elements. Is there a way to take this base .dts,
> >>>>> then add a base board .dtsi by Kconfig option, and similar a
> >>>>> boot-mode?
> >>>>
> >>>> The -u-boot.dtsi is preprocessed by C preprocessor, just like all the
> >>>> other DTs, so you can have a -u-boot.dtsi file which contains C
> >>>> preprocessor conditional statements in it to conditionally include other
> >>>> .dtsi files:
> >>>>
> >>>> #if IS_ENABLED(...)
> >>>> #include ...
> >>>> #else ...
> >>>> ...
> >>>> #endif
> >>>
> >>> Going through the include list setup by the Makefile made me find my
> >>> mistake. Currently I may use u-boot specific stuff in arch/arm/dts and
> >>> include generic .dtsi fragments from dts/upstream. Note: I'm not
> >>> setting CONFIG_OF_UPSTREAM since I'm using the regular include list
> >>> which already contains dts/upstream/src/arm/intel. Is this ok? Or,
> >>> shall I try a different approach, which involves having
> >>> CONFIG_OF_UPSTREAM explicitely set in the defconfig?
> >>
> >> I'm not quite sure I understand the question. Once this platform DTs
> >> land in mainline and the DTs get synchronized into U-Boot, you should
> >> then set CONFIG_OF_UPSTREAM. Until then, you could patch the DTs into
> >> dts/upstream/ to test the result with OF_UPSTREAM enabled .
> >>
> >
> > Ah, sorry. I did not explain well. Currently I patch the DTs which
> > should go to kernel/mainline into my local u-boot:
> > dts/upstream/src/arm/intel/socfpga/ as a preparation for my test
> > builds.
>
> OK
>
> > For U-boot I will need to build a devicetree file from archarm/dts. I
> > cannot rely just on the upstream fragments for u-boot. Imagine
> > settings like initial fpga bitstream loading, handoff file setup for
> > initialization, etc. In parts I may use .dtsi files from dts/upstream,
> > though, but most of the u-boot particular devicetree setup will reside
> > in arch/arm/dts, I guess (you may see later in the patches).
>
> You should be able to use dts/upstream/src/arm/intel/socfpga/ with
> -u-boot.dtsi from arch/arm/dts/ for this purpose, right ?

Yeah that's a possibility. But are there any plans on pushing
currently U-Boot specific DT bits to upstream DT (Linux kernel
source)?

>
> > I noticed when setting the option CONFIG_OF_UPSTREAM in `make
> > menuconfig`, it prepends `dts/upstream/` to the included paths of the
> > devicetree files. The resulting path for the .dts was then
> > dts/upstream/arch/arm/dts/ and could not be found anymore. When I
> > don't activate CONFIG_OF_UPSTREAM, dts/upstream is in the Makefile's
> > include list anyway so that I easily can include from both locations.
>
> +CC Sumit
>

Yeah that's true it's done on purpose to allow reuse of DT sources
includes (.dtsi or header files) even when CONFIG_OF_UPSTREAM isn't
enabled.

-Sumit

> > In conclusion, currently I'm calling a .dts for building the u-boot DT
> > from arch/arm/dts. The file includes upstream stuff as .dtsi fragment
> > from dts/upstream and handoff from local. CONFIG_OF_UPSTREAM does not
> > seem to be necessary in this case.
> >
> > This approach currently works for me. If you strongly disagree, I may
> > invest more time to find a way (or why there is currently no way) with
> > CONFIG_OF_UPSTREAM.
> >
> > This was my question about. Anyway you may wait on v3 to understand
> > better in source what I'm doing, or if I'm just messing around.
> I'll wait for V3, sure, good luck.
>
> Sorry for the delayed reply.

Re: [PATCH 2/9] ARM: dts: socfpga: add Enclustra Intel AA1

[Lothar Rubusch]

Dear U-boot community!

On Mon, Oct 7, 2024 at 12:21 PM Sumit Garg <sumit.garg@linaro.org> wrote:
>
> On Sat, 5 Oct 2024 at 07:14, Marek Vasut <marex@denx.de> wrote:
> >
> > On 9/29/24 9:19 PM, Lothar Rubusch wrote:
> > > On Sun, Sep 29, 2024 at 6:55 PM Marek Vasut <marex@denx.de> wrote:
> > >>
> > >> On 9/28/24 12:47 AM, Lothar Rubusch wrote:
> > >>
> > >>>> [...]
> > > For U-boot I will need to build a devicetree file from archarm/dts. I
> > > cannot rely just on the upstream fragments for u-boot. Imagine
> > > settings like initial fpga bitstream loading, handoff file setup for
> > > initialization, etc. In parts I may use .dtsi files from dts/upstream,
> > > though, but most of the u-boot particular devicetree setup will reside
> > > in arch/arm/dts, I guess (you may see later in the patches).
> >
> > You should be able to use dts/upstream/src/arm/intel/socfpga/ with
> > -u-boot.dtsi from arch/arm/dts/ for this purpose, right ?
>
> Yeah that's a possibility. But are there any plans on pushing
> currently U-Boot specific DT bits to upstream DT (Linux kernel
> source)?
>

Hum, I have certain requirements when working with Arria10 Socfpga
SoMs. Here, I need..
- to do the handoff initialization from DTS (only in u-boot)
- to setup a fpga loader for the bitstream in the DTS (only in u-boot/spl)
- to adjust the boot media, needed for u-boot to know from where to
load the fpga.itb
- and to mux the boot-mode in the DT, e.g. QSPI off when booting from
MMC, and vice versa

So, time has passed a bit. I don't need different memory declarations.
I don't need DTBOs, but I'm applying the  #if IS_ENABLED(CONFIG_..)
approach, just great! This reduces complexity by far and I can load
the major part from dts/upstream. For the rest I noticed the Google
Chameleon HW takes a somehow similar approach and I tried to align my
DTS setup to use common base for the handoff and early init approach,
which reduces the need to add additional files.

Nevertheless, I have to not enable CONFIG_OF_UPSTREAM, since I need to
keep the .dts file to reside in arch/arm/dts then taking some of the
.dtsi files from dts/upstream. This works and I'll present my solution
very soon.

> >
> > > I noticed when setting the option CONFIG_OF_UPSTREAM in `make
> > > menuconfig`, it prepends `dts/upstream/` to the included paths of the
> > > devicetree files. The resulting path for the .dts was then
> > > dts/upstream/arch/arm/dts/ and could not be found anymore. When I
> > > don't activate CONFIG_OF_UPSTREAM, dts/upstream is in the Makefile's
> > > include list anyway so that I easily can include from both locations.
> >
> > +CC Sumit
> >
>
> Yeah that's true it's done on purpose to allow reuse of DT sources
> includes (.dtsi or header files) even when CONFIG_OF_UPSTREAM isn't
> enabled.
>

As I said to me this comes in very handy.

So, as an update, I started upstreaming of my DTS parts to the kernel,
at least Marek should be in CC, here.

To the u-boot v3 patch set I prepared further brush ups. I changed
over to  using standard boot env, and currently pretend removing all
of the manually provided env. I tried to get further rid of deprecated
things and after a major rework of the DT approach now I have mainly
one blocking issue.

I'm not sure, perhaps I'll send you the patches together with the
question: The altera_set_storage  command in  the u-boot env was
working with the old GPIO API and without using the DM. So, I defined
a small U_BOOT_DRIVER(). I don't want to have DT binding for that
device, but rather coming up, when I call
uclass_get_device_by_driver(). Nevertheless, this function now does
not give me a valid device back.
IMHO I don't even need an extra bind() or probe(), anyway I tried
with/without explicit bind(), with probe(), I tried even to do a
crafted binding in the DT with the of_match table. But seems I'm
missing something essential. I saw other drivers could use GPIOs
relatively simple. Do you know an example where I could have a look
at?

Then I would use this device and simply implement the
altera_set_storage functionaly by the modern GPIO API on the device.
I'm a bit unsure what I'm doing wrong here. Perhaps I may show the
patches with this issue?

Best regards,
L