From: dinesh.maniyam@intel.com
To: u-boot@lists.denx.de
Cc: Marek <marex@denx.de>, Simon <simon.k.r.goldschmidt@gmail.com>,
Tom Rini <trini@konsulko.com>,
Dario Binacchi <dario.binacchi@amarulasolutions.com>,
Michael Trimarchi <michael@amarulasolutions.com>,
Johan Jonker <jbx6244@gmail.com>,
Michal Simek <michal.simek@amd.com>,
Arseniy Krasnov <avkrasnov@salutedevices.com>,
Alexander Dahl <ada@thorsis.com>,
William Zhang <william.zhang@broadcom.com>,
Igor Prusov <ivprusov@salutedevices.com>,
Tien Fong <tien.fong.chee@intel.com>,
Kok Kiang <kok.kiang.hea@intel.com>,
Dinesh <dinesh.maniyam@intel.com>,
Boon Khai <boon.khai.ng@intel.com>,
Alif <alif.zakuan.yuslaimi@intel.com>,
Teik Heng <teik.heng.chong@intel.com>,
Hazim <muhammad.hazim.izzat.zamri@intel.com>,
Tingting Meng <tingting.meng@intel.com>,
Jit Loon Lim <jit.loon.lim@intel.com>,
Sieu Mun Tang <sieu.mun.tang@intel.com>
Subject: [PATCH 15/19] drivers: mtd: nand: base: Add support for Hardware ECC for check bad block
Date: Thu, 19 Sep 2024 11:55:08 +0800 [thread overview]
Message-ID: <20240919035512.13854-16-dinesh.maniyam@intel.com> (raw)
In-Reply-To: <20240919035512.13854-1-dinesh.maniyam@intel.com>
From: Dinesh Maniyam <dinesh.maniyam@intel.com>
This patch is to leverage linux code to support hardware ECC interface
in verify nand bad block.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
---
drivers/mtd/nand/raw/nand_base.c | 71 +++++++++++++++++++++-----------
include/linux/mtd/rawnand.h | 13 ++++++
2 files changed, 60 insertions(+), 24 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 4401bdcdb9..9b1b2d1f85 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -9,6 +9,8 @@
* Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
* 2002-2006 Thomas Gleixner (tglx@linutronix.de)
*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
* Credits:
* David Woodhouse for adding multichip support
*
@@ -306,6 +308,35 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
}
+/*
+ * nand_bbm_get_next_page - Get the next page for bad block markers
+ * @chip: The NAND chip
+ * @page: First page to start checking for bad block marker usage
+ *
+ * Returns an integer that corresponds to the page offset within a block, for
+ * a page that is used to store bad block markers. If no more pages are
+ * available, -EINVAL is returned.
+ */
+int nand_bbm_get_next_page(struct nand_chip *chip, int page)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int last_page = ((mtd->erasesize - mtd->writesize) >>
+ chip->page_shift) & chip->pagemask;
+ unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE
+ | NAND_BBM_LASTPAGE;
+
+ if (page == 0 && !(chip->options & bbm_flags))
+ return 0;
+ if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
+ return 0;
+ if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
+ return 1;
+ if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
+ return last_page;
+
+ return -EINVAL;
+}
+
/**
* nand_block_bad - [DEFAULT] Read bad block marker from the chip
* @mtd: MTD device structure
@@ -315,40 +346,32 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
*/
static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
{
- int page, res = 0, i = 0;
struct nand_chip *chip = mtd_to_nand(mtd);
- u16 bad;
+ int first_page, page_offset;
+ int res;
+ u8 bad;
- if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
- ofs += mtd->erasesize - mtd->writesize;
+ first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+ page_offset = nand_bbm_get_next_page(chip, 0);
- page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+ while (page_offset >= 0) {
+ res = chip->ecc.read_oob(mtd, chip, first_page + page_offset);
+ if (res < 0)
+ return res;
- do {
- if (chip->options & NAND_BUSWIDTH_16) {
- chip->cmdfunc(mtd, NAND_CMD_READOOB,
- chip->badblockpos & 0xFE, page);
- bad = cpu_to_le16(chip->read_word(mtd));
- if (chip->badblockpos & 0x1)
- bad >>= 8;
- else
- bad &= 0xFF;
- } else {
- chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
- page);
- bad = chip->read_byte(mtd);
- }
+ bad = chip->oob_poi[chip->badblockpos];
if (likely(chip->badblockbits == 8))
res = bad != 0xFF;
else
res = hweight8(bad) < chip->badblockbits;
- ofs += mtd->writesize;
- page = (int)(ofs >> chip->page_shift) & chip->pagemask;
- i++;
- } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
+ if (res)
+ return res;
- return res;
+ page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
+ }
+
+ return 0;
}
/**
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 537c62424a..49444e9353 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -4,6 +4,8 @@
* Steven J. Hill <sjhill@realitydiluted.com>
* Thomas Gleixner <tglx@linutronix.de>
*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
* Info:
* Contains standard defines and IDs for NAND flash devices
*
@@ -131,6 +133,17 @@ void nand_wait_ready(struct mtd_info *mtd);
#define NAND_DATA_IFACE_CHECK_ONLY -1
+/*
+ * There are different places where the manufacturer stores the factory bad
+ * block markers.
+ *
+ * Position within the block: Each of these pages needs to be checked for a
+ * bad block marking pattern.
+ */
+#define NAND_BBM_FIRSTPAGE BIT(24)
+#define NAND_BBM_SECONDPAGE BIT(25)
+#define NAND_BBM_LASTPAGE BIT(26)
+
/*
* Constants for ECC_MODES
*/
--
2.26.2
next prev parent reply other threads:[~2024-09-19 3:58 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-19 3:54 [PATCH 00/19] Add Cadence NAND Driver support dinesh.maniyam
2024-09-19 3:54 ` [PATCH 01/19] dt: nand: add cadence nand dt-bindings dinesh.maniyam
2024-09-19 3:54 ` [PATCH 02/19] arm: dts: agilex5: Enabled cdns-nand dts setting dinesh.maniyam
2024-09-19 3:54 ` [PATCH 03/19] include: asm: Add support to read/write 64-bit dinesh.maniyam
2024-09-19 3:54 ` [PATCH 04/19] drivers: mtd: nand: Add driver for Cadence Nand dinesh.maniyam
2024-09-19 3:54 ` [PATCH 05/19] drivers: mtd: nand: cadence: Add support for read status command dinesh.maniyam
2024-09-19 3:54 ` [PATCH 06/19] drivers: mtd: nand: cadence: Add support for readid command dinesh.maniyam
2024-09-19 3:55 ` [PATCH 07/19] drivers: mtd: nand: cadence: Add support for NAND_CMD_PARAM dinesh.maniyam
2024-09-19 3:55 ` [PATCH 08/19] drivers: mtd: nand: cadence: Support NAND_CMD_RESET dinesh.maniyam
2024-09-19 3:55 ` [PATCH 09/19] drivers: mtd: nand: cadence: Support cmd SET_FEATURES & GET_FEATURES dinesh.maniyam
2024-09-19 3:55 ` [PATCH 10/19] drivers: mtd: nand: cadence: Flush dma descriptor dinesh.maniyam
2024-09-19 3:55 ` [PATCH 11/19] drivers: mtd: nand: cadence: Poll for desc complete status dinesh.maniyam
2024-09-19 3:55 ` [PATCH 12/19] drivers: mtd: nand: cadence: Use bounce buffer dinesh.maniyam
2024-09-19 3:55 ` [PATCH 13/19] drivers: nand: Enabled Kconfig and Makefile for cdns-nand dinesh.maniyam
2024-09-19 3:55 ` [PATCH 14/19] configs: nand2_defconfig: Enable configs for nand boot dinesh.maniyam
2024-10-05 15:16 ` Michael Nazzareno Trimarchi
2024-10-05 15:20 ` Tom Rini
2024-10-07 2:23 ` Maniyam, Dinesh
2024-10-07 17:01 ` Michael Nazzareno Trimarchi
2024-10-08 9:43 ` Maniyam, Dinesh
2024-09-19 3:55 ` dinesh.maniyam [this message]
2024-09-19 3:55 ` [PATCH 16/19] drivers: mtd: nand: spl: Add support for nand SPL load image dinesh.maniyam
2024-10-05 15:22 ` Michael Nazzareno Trimarchi
2024-10-07 2:27 ` Maniyam, Dinesh
2024-09-19 3:55 ` [PATCH 17/19] drivers: mtd: nand: Enabled Kconfig and Makefile for Cadence-SPL dinesh.maniyam
2024-09-19 3:55 ` [PATCH 18/19] drivers: mtd: nand: Kconfig: Remove SYS_NAND_BLOCK_SIZE dependency dinesh.maniyam
2024-09-19 3:55 ` [PATCH 19/19] drivers: mtd: nand: Kconfig: Enabled self-init for cdns-nand SPL dinesh.maniyam
2024-09-19 6:05 ` [PATCH 00/19] Add Cadence NAND Driver support Alexander Dahl
2024-10-07 2:16 ` Maniyam, Dinesh
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