[PATCH 05/26] clk: imx8mm: Mark IMX8MM_SYS_PLL2 and IMX8MM_SYS_PLL3 as enabled

Dario Binacchi
2024-09-13T09:57:55Z

From: Michael Trimarchi <michael@amarulasolutions.com>

Both clock are enabled by the bootloader and we need to increase their
reference count to avoid disable during reparent operation.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---

drivers/clk/imx/clk-imx8mm.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 432348a15cad..0e71ceefe96c 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -176,6 +176,8 @@ static const char * const imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200
static int imx8mm_clk_probe(struct udevice *dev)
{
void __iomem *base;
+ struct clk *clk;
+ int ret;

base = (void *)ANATOP_BASE_ADDR;

@@ -458,6 +460,13 @@ static int imx8mm_clk_probe(struct udevice *dev)
clk_dm(IMX8MM_CLK_QSPI_ROOT,
imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
#endif
+ ret = clk_get_by_id(IMX8MM_SYS_PLL2, &clk);
+ if (!ret)
+ clk_enable(clk);
+
+ ret = clk_get_by_id(IMX8MM_SYS_PLL3, &clk);
+ if (!ret)
+ clk_enable(clk);

clk_dm(IMX8MM_CLK_ARM,
imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
--
2.43.0