* [PATCH 0/3] Add support for all variants of the phyCORE-i.MX93 SOM
@ 2024-11-04 10:41 Christoph Stoidner
2024-11-04 10:41 ` [PATCH 1/3] board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings Christoph Stoidner
2024-11-04 10:41 ` [PATCH 2/3] board: phytec: imx93: Add eeprom-based hardware introspection Christoph Stoidner
0 siblings, 2 replies; 9+ messages in thread
From: Christoph Stoidner @ 2024-11-04 10:41 UTC (permalink / raw)
To: u-boot, upstream; +Cc: Christoph Stoidner
The phyCORE-i.MX 93 is available in various variants (e.g. different ram
sizes, eMMC HS400 yes/no). It's eeprom contains information which features
the existing module supports.
Extend the existing board-code to support all the SOM variants. The spl/u-boot
evaluates the eeprom information and enables supported features accordingly.
The resulting spl and u-boot binary is able to boot each phyCORE-i.MX 93 SOM
variant on each carrier board.
Christoph Stoidner (3):
board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings
board: phytec: imx93: Add eeprom-based hardware introspection
board: phytec: imx93: Add phyCORE-i.MX93 support all SOM variants
arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi | 33 +-
arch/arm/mach-imx/imx9/Kconfig | 2 +
arch/arm/mach-imx/imx9/soc.c | 2 +-
board/phytec/common/Kconfig | 8 +
board/phytec/common/Makefile | 1 +
board/phytec/common/imx93_som_detection.c | 88 ++
board/phytec/common/imx93_som_detection.h | 33 +
board/phytec/phycore_imx93/Kconfig | 28 +
board/phytec/phycore_imx93/MAINTAINERS | 6 +-
board/phytec/phycore_imx93/lpddr4_timing.c | 794 ++++++++++++++++--
board/phytec/phycore_imx93/phycore-imx93.c | 52 ++
board/phytec/phycore_imx93/spl.c | 58 ++
configs/imx93-phycore_defconfig | 156 ++++
13 files changed, 1196 insertions(+), 65 deletions(-)
create mode 100644 board/phytec/common/imx93_som_detection.c
create mode 100644 board/phytec/common/imx93_som_detection.h
create mode 100644 configs/imx93-phycore_defconfig
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/3] board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings
2024-11-04 10:41 [PATCH 0/3] Add support for all variants of the phyCORE-i.MX93 SOM Christoph Stoidner
@ 2024-11-04 10:41 ` Christoph Stoidner
2024-11-04 12:16 ` [Upstream] " Teresa Remmet
2024-11-04 12:30 ` Fabio Estevam
2024-11-04 10:41 ` [PATCH 2/3] board: phytec: imx93: Add eeprom-based hardware introspection Christoph Stoidner
1 sibling, 2 replies; 9+ messages in thread
From: Christoph Stoidner @ 2024-11-04 10:41 UTC (permalink / raw)
To: u-boot, upstream; +Cc: Christoph Stoidner, Mathieu Othacehe
The phyCORE-i.MX 93 is available with a 1GB ram chip or a 2GB ram chip.
Add the ram timings for the 2GB chip, in form of a diff compared
to the existing LPDDR4X 1GB timings. With that, the SPL can select the
appropriate timings at startup.
Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
Cc: Mathieu Othacehe <m.othacehe@gmail.com>, Christoph Stoidner <c.stoidner@phytec.de>, Tom Rini <trini@konsulko.com>, Yannic Moog <y.moog@phytec.de>, Primoz Fiser <primoz.fiser@norik.com>, Andrej Picej <andrej.picej@norik.com>, Wadim Egorov <w.egorov@phytec.de>
---
board/phytec/phycore_imx93/lpddr4_timing.c | 794 +++++++++++++++++++--
1 file changed, 733 insertions(+), 61 deletions(-)
diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx93/lpddr4_timing.c
index 2111972a40..b7132ffade 100644
--- a/board/phytec/phycore_imx93/lpddr4_timing.c
+++ b/board/phytec/phycore_imx93/lpddr4_timing.c
@@ -1,24 +1,24 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2023 NXP
- * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Copyright 2024 NXP
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
* Christoph Stoidner <c.stoidner@phytec.de>
*
- * Code generated with DDR Tool v1.0.0.
+ * Code generated with DDR Tool v3.1.0_7.4.
*/
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
+/* Initialize DDRC registers */
static struct dram_cfg_param ddr_ddrc_cfg[] = {
- /** Initialize DDRC registers **/
{0x4e300110, 0x44100001},
{0x4e300000, 0x8000bf},
{0x4e300008, 0x0},
{0x4e300080, 0x80000412},
{0x4e300084, 0x0},
{0x4e300114, 0x1002},
- {0x4e300260, 0x4080},
+ {0x4e300260, 0x80},
{0x4e300f04, 0x80},
{0x4e300800, 0x43b30002},
{0x4e300804, 0x1f1f1f1f},
@@ -31,18 +31,17 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x4e301254, 0x0},
{0x4e301258, 0x0},
{0x4e30125c, 0x0},
-
};
/* dram fsp cfg */
static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{
{
- {0x4e300100, 0x24A0421B},
+ {0x4e300100, 0x24A0321B},
{0x4e300104, 0xF8EE001B},
- {0x4e300108, 0x2F263233},
- {0x4e30010C, 0x0005E18B},
- {0x4e300124, 0x1C770000},
+ {0x4e300108, 0x2F2E3233},
+ {0x4e30010C, 0x0005C18B},
+ {0x4e300124, 0x1C790000},
{0x4e300160, 0x00009102},
{0x4e30016C, 0x35F00000},
{0x4e300170, 0x8B0B0608},
@@ -50,21 +49,73 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{0x4e300254, 0x00FE00FE},
{0x4e300258, 0x00000008},
{0x4e30025C, 0x00000400},
- {0x4e300300, 0x224F2215},
+ {0x4e300300, 0x224F2213},
{0x4e300304, 0x00FE2213},
- {0x4e300308, 0x0A3C0E3C},
+ {0x4e300308, 0x0A380E3D},
},
{
{0x01, 0xE4},
{0x02, 0x36},
- {0x03, 0xF2},
- {0x0b, 0x46},
- {0x0c, 0x11},
- {0x0e, 0x11},
+ {0x03, 0x22},
+ {0x0b, 0x44},
+ {0x0c, 0x1E},
+ {0x0e, 0x12},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x124F2100},
+ {0x4e300104, 0xF877000E},
+ {0x4e300108, 0x1816E4AA},
+ {0x4e30010C, 0x005101E6},
+ {0x4e300124, 0x0E3C0000},
+ {0x4e300160, 0x00009101},
+ {0x4e30016C, 0x30900000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x00000014},
+ {0x4e300254, 0x007B007B},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0xB4},
+ {0x02, 0x1B},
+ {0x03, 0x22},
+ {0x0b, 0x44},
+ {0x0c, 0x1E},
+ {0x0e, 0x12},
{0x16, 0x04},
},
0,
},
+ {
+ {
+ {0x4e300100, 0x00051000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E620A48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009100},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00240024},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x22},
+ {0x0b, 0x44},
+ {0x0c, 0x1E},
+ {0x0e, 0x12},
+ {0x16, 0x04},
+ },
+ 1,
+ },
};
@@ -90,25 +141,65 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x1015f, 0x5ff},
{0x1105f, 0x5ff},
{0x1115f, 0x5ff},
+ {0x11005f, 0x5ff},
+ {0x11015f, 0x5ff},
+ {0x11105f, 0x5ff},
+ {0x11115f, 0x5ff},
+ {0x21005f, 0x5ff},
+ {0x21015f, 0x5ff},
+ {0x21105f, 0x5ff},
+ {0x21115f, 0x5ff},
{0x55, 0x1ff},
{0x1055, 0x1ff},
{0x2055, 0x1ff},
{0x200c5, 0x19},
+ {0x1200c5, 0xb},
+ {0x2200c5, 0x7},
{0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
{0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
{0x20024, 0x1e3},
{0x2003a, 0x2},
{0x2007d, 0x212},
{0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
{0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
{0x1004d, 0x600},
{0x1014d, 0x600},
{0x1104d, 0x600},
{0x1114d, 0x600},
- {0x10049, 0xe00},
- {0x10149, 0xe00},
- {0x11049, 0xe00},
- {0x11149, 0xe00},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0x604},
+ {0x10149, 0x604},
+ {0x11049, 0x604},
+ {0x11149, 0x604},
+ {0x110049, 0x604},
+ {0x110149, 0x604},
+ {0x111049, 0x604},
+ {0x111149, 0x604},
+ {0x210049, 0x604},
+ {0x210149, 0x604},
+ {0x211049, 0x604},
+ {0x211149, 0x604},
{0x43, 0x60},
{0x1043, 0x60},
{0x2043, 0x60},
@@ -117,14 +208,30 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x20050, 0x0},
{0x2009b, 0x2},
{0x20008, 0x3a5},
+ {0x120008, 0x1d3},
+ {0x220008, 0x9c},
{0x20088, 0x9},
- {0x200b2, 0x10c},
+ {0x200b2, 0x104},
{0x10043, 0x5a1},
{0x10143, 0x5a1},
{0x11043, 0x5a1},
{0x11143, 0x5a1},
+ {0x1200b2, 0x104},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x104},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
{0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
{0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
{0x200f0, 0x600},
{0x200f1, 0x0},
{0x200f2, 0x4444},
@@ -133,42 +240,83 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x200f5, 0x0},
{0x200f6, 0x0},
{0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
{0x20025, 0x0},
- {0x2002d, 0x1},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
{0x2002c, 0x0},
{0x20021, 0x0},
{0x200c7, 0x21},
{0x1200c7, 0x21},
{0x200ca, 0x24},
{0x1200ca, 0x24},
-
};
-/* ddr phy trained csr */
+/* PHY trained csr */
static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x1005f, 0x0},
{0x1015f, 0x0},
{0x1105f, 0x0},
{0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
{0x55, 0x0},
{0x1055, 0x0},
{0x2055, 0x0},
{0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
{0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
{0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
{0x20024, 0x0},
{0x2003a, 0x0},
{0x2007d, 0x0},
{0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
{0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
{0x1004d, 0x0},
{0x1014d, 0x0},
{0x1104d, 0x0},
{0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
{0x10049, 0x0},
{0x10149, 0x0},
{0x11049, 0x0},
{0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
{0x43, 0x0},
{0x1043, 0x0},
{0x2043, 0x0},
@@ -177,14 +325,30 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x20050, 0x0},
{0x2009b, 0x0},
{0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
{0x20088, 0x0},
{0x200b2, 0x0},
{0x10043, 0x0},
{0x10143, 0x0},
{0x11043, 0x0},
{0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
{0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
{0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
{0x200f0, 0x0},
{0x200f1, 0x0},
{0x200f2, 0x0},
@@ -193,8 +357,12 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x200f5, 0x0},
{0x200f6, 0x0},
{0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
{0x20025, 0x0},
{0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
{0x2002c, 0x0},
{0xd0000, 0x0},
{0x90000, 0x0},
@@ -682,6 +850,14 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x2000c, 0x0},
{0x2000d, 0x0},
{0x2000e, 0x0},
+ {0x12000b, 0x0},
+ {0x12000c, 0x0},
+ {0x12000d, 0x0},
+ {0x12000e, 0x0},
+ {0x22000b, 0x0},
+ {0x22000c, 0x0},
+ {0x22000d, 0x0},
+ {0x22000e, 0x0},
{0x9000c, 0x0},
{0x9000d, 0x0},
{0x9000e, 0x0},
@@ -692,12 +868,26 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x90013, 0x0},
{0x20010, 0x0},
{0x20011, 0x0},
+ {0x120010, 0x0},
+ {0x120011, 0x0},
{0x40080, 0x0},
{0x40081, 0x0},
{0x40082, 0x0},
{0x40083, 0x0},
{0x40084, 0x0},
{0x40085, 0x0},
+ {0x140080, 0x0},
+ {0x140081, 0x0},
+ {0x140082, 0x0},
+ {0x140083, 0x0},
+ {0x140084, 0x0},
+ {0x140085, 0x0},
+ {0x240080, 0x0},
+ {0x240081, 0x0},
+ {0x240082, 0x0},
+ {0x240083, 0x0},
+ {0x240084, 0x0},
+ {0x240085, 0x0},
{0x400fd, 0x0},
{0x400f1, 0x0},
{0x10011, 0x0},
@@ -866,6 +1056,160 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x90207, 0x0},
{0x90208, 0x0},
{0x20020, 0x0},
+ {0x100080, 0x0},
+ {0x101080, 0x0},
+ {0x102080, 0x0},
+ {0x110020, 0x0},
+ {0x110080, 0x0},
+ {0x110081, 0x0},
+ {0x1100d0, 0x0},
+ {0x1100d1, 0x0},
+ {0x11008c, 0x0},
+ {0x11008d, 0x0},
+ {0x110180, 0x0},
+ {0x110181, 0x0},
+ {0x1101d0, 0x0},
+ {0x1101d1, 0x0},
+ {0x11018c, 0x0},
+ {0x11018d, 0x0},
+ {0x1100c0, 0x0},
+ {0x1100c1, 0x0},
+ {0x1101c0, 0x0},
+ {0x1101c1, 0x0},
+ {0x1102c0, 0x0},
+ {0x1102c1, 0x0},
+ {0x1103c0, 0x0},
+ {0x1103c1, 0x0},
+ {0x1104c0, 0x0},
+ {0x1104c1, 0x0},
+ {0x1105c0, 0x0},
+ {0x1105c1, 0x0},
+ {0x1106c0, 0x0},
+ {0x1106c1, 0x0},
+ {0x1107c0, 0x0},
+ {0x1107c1, 0x0},
+ {0x1108c0, 0x0},
+ {0x1108c1, 0x0},
+ {0x1100ae, 0x0},
+ {0x1100af, 0x0},
+ {0x111020, 0x0},
+ {0x111080, 0x0},
+ {0x111081, 0x0},
+ {0x1110d0, 0x0},
+ {0x1110d1, 0x0},
+ {0x11108c, 0x0},
+ {0x11108d, 0x0},
+ {0x111180, 0x0},
+ {0x111181, 0x0},
+ {0x1111d0, 0x0},
+ {0x1111d1, 0x0},
+ {0x11118c, 0x0},
+ {0x11118d, 0x0},
+ {0x1110c0, 0x0},
+ {0x1110c1, 0x0},
+ {0x1111c0, 0x0},
+ {0x1111c1, 0x0},
+ {0x1112c0, 0x0},
+ {0x1112c1, 0x0},
+ {0x1113c0, 0x0},
+ {0x1113c1, 0x0},
+ {0x1114c0, 0x0},
+ {0x1114c1, 0x0},
+ {0x1115c0, 0x0},
+ {0x1115c1, 0x0},
+ {0x1116c0, 0x0},
+ {0x1116c1, 0x0},
+ {0x1117c0, 0x0},
+ {0x1117c1, 0x0},
+ {0x1118c0, 0x0},
+ {0x1118c1, 0x0},
+ {0x1110ae, 0x0},
+ {0x1110af, 0x0},
+ {0x190201, 0x0},
+ {0x190202, 0x0},
+ {0x190203, 0x0},
+ {0x190205, 0x0},
+ {0x190206, 0x0},
+ {0x190207, 0x0},
+ {0x190208, 0x0},
+ {0x120020, 0x0},
+ {0x200080, 0x0},
+ {0x201080, 0x0},
+ {0x202080, 0x0},
+ {0x210020, 0x0},
+ {0x210080, 0x0},
+ {0x210081, 0x0},
+ {0x2100d0, 0x0},
+ {0x2100d1, 0x0},
+ {0x21008c, 0x0},
+ {0x21008d, 0x0},
+ {0x210180, 0x0},
+ {0x210181, 0x0},
+ {0x2101d0, 0x0},
+ {0x2101d1, 0x0},
+ {0x21018c, 0x0},
+ {0x21018d, 0x0},
+ {0x2100c0, 0x0},
+ {0x2100c1, 0x0},
+ {0x2101c0, 0x0},
+ {0x2101c1, 0x0},
+ {0x2102c0, 0x0},
+ {0x2102c1, 0x0},
+ {0x2103c0, 0x0},
+ {0x2103c1, 0x0},
+ {0x2104c0, 0x0},
+ {0x2104c1, 0x0},
+ {0x2105c0, 0x0},
+ {0x2105c1, 0x0},
+ {0x2106c0, 0x0},
+ {0x2106c1, 0x0},
+ {0x2107c0, 0x0},
+ {0x2107c1, 0x0},
+ {0x2108c0, 0x0},
+ {0x2108c1, 0x0},
+ {0x2100ae, 0x0},
+ {0x2100af, 0x0},
+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
{0x20077, 0x0},
{0x20072, 0x0},
{0x20073, 0x0},
@@ -888,7 +1232,6 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x11640, 0x0},
{0x11740, 0x0},
{0x11840, 0x0},
-
};
/* P0 message block parameter for training firmware */
@@ -896,7 +1239,7 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
{0xd0000, 0x0},
{0x54003, 0xe94},
{0x54004, 0x4},
- {0x54006, 0x15},
+ {0x54006, 0x14},
{0x54008, 0x131f},
{0x54009, 0xc8},
{0x5400b, 0x4},
@@ -904,36 +1247,113 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
{0x5400f, 0x100},
{0x54012, 0x110},
{0x54019, 0x36e4},
- {0x5401a, 0xf2},
- {0x5401b, 0x1146},
- {0x5401c, 0x1108},
+ {0x5401a, 0x22},
+ {0x5401b, 0x1e44},
+ {0x5401c, 0x1208},
{0x5401e, 0x4},
{0x5401f, 0x36e4},
- {0x54020, 0xf2},
- {0x54021, 0x1146},
- {0x54022, 0x1108},
+ {0x54020, 0x22},
+ {0x54021, 0x1e44},
+ {0x54022, 0x1208},
{0x54024, 0x4},
{0x54032, 0xe400},
- {0x54033, 0xf236},
- {0x54034, 0x4600},
- {0x54035, 0x811},
- {0x54036, 0x11},
+ {0x54033, 0x2236},
+ {0x54034, 0x4400},
+ {0x54035, 0x81e},
+ {0x54036, 0x12},
{0x54037, 0x400},
{0x54038, 0xe400},
- {0x54039, 0xf236},
- {0x5403a, 0x4600},
- {0x5403b, 0x811},
- {0x5403c, 0x11},
+ {0x54039, 0x2236},
+ {0x5403a, 0x4400},
+ {0x5403b, 0x81e},
+ {0x5403c, 0x12},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x74a},
+ {0x54004, 0x4},
+ {0x54006, 0x14},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x1bb4},
+ {0x5401a, 0x22},
+ {0x5401b, 0x1e44},
+ {0x5401c, 0x1208},
+ {0x5401e, 0x4},
+ {0x5401f, 0x1bb4},
+ {0x54020, 0x22},
+ {0x54021, 0x1e44},
+ {0x54022, 0x1208},
+ {0x54024, 0x4},
+ {0x54032, 0xb400},
+ {0x54033, 0x221b},
+ {0x54034, 0x4400},
+ {0x54035, 0x81e},
+ {0x54036, 0x12},
+ {0x54037, 0x400},
+ {0x54038, 0xb400},
+ {0x54039, 0x221b},
+ {0x5403a, 0x4400},
+ {0x5403b, 0x81e},
+ {0x5403c, 0x12},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x14},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x22},
+ {0x5401b, 0x1e44},
+ {0x5401c, 0x1200},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x22},
+ {0x54021, 0x1e44},
+ {0x54022, 0x1200},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x2209},
+ {0x54034, 0x4400},
+ {0x54035, 0x1e},
+ {0x54036, 0x12},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x2209},
+ {0x5403a, 0x4400},
+ {0x5403b, 0x1e},
+ {0x5403c, 0x12},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
+
/* P0 2D message block parameter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{0xd0000, 0x0},
{0x54003, 0xe94},
{0x54004, 0x4},
- {0x54006, 0x15},
+ {0x54006, 0x14},
{0x54008, 0x61},
{0x54009, 0xc8},
{0x5400b, 0x4},
@@ -942,26 +1362,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{0x54010, 0x2080},
{0x54012, 0x110},
{0x54019, 0x36e4},
- {0x5401a, 0xf2},
- {0x5401b, 0x1146},
- {0x5401c, 0x1108},
+ {0x5401a, 0x22},
+ {0x5401b, 0x1e44},
+ {0x5401c, 0x1208},
{0x5401e, 0x4},
{0x5401f, 0x36e4},
- {0x54020, 0xf2},
- {0x54021, 0x1146},
- {0x54022, 0x1108},
+ {0x54020, 0x22},
+ {0x54021, 0x1e44},
+ {0x54022, 0x1208},
{0x54024, 0x4},
{0x54032, 0xe400},
- {0x54033, 0xf236},
- {0x54034, 0x4600},
- {0x54035, 0x811},
- {0x54036, 0x11},
+ {0x54033, 0x2236},
+ {0x54034, 0x4400},
+ {0x54035, 0x81e},
+ {0x54036, 0x12},
{0x54037, 0x400},
{0x54038, 0xe400},
- {0x54039, 0xf236},
- {0x5403a, 0x4600},
- {0x5403b, 0x811},
- {0x5403c, 0x11},
+ {0x54039, 0x2236},
+ {0x5403a, 0x4400},
+ {0x5403b, 0x81e},
+ {0x5403c, 0x12},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
@@ -1451,10 +1871,18 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{0x400d7, 0x20b},
{0x2003a, 0x2},
{0x200be, 0x3},
- {0x2000b, 0x75},
+ {0x2000b, 0x41a},
{0x2000c, 0xe9},
{0x2000d, 0x91c},
{0x2000e, 0x2c},
+ {0x12000b, 0x20d},
+ {0x12000c, 0x74},
+ {0x12000d, 0x48e},
+ {0x12000e, 0x2c},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
{0x9000c, 0x0},
{0x9000d, 0x173},
{0x9000e, 0x60},
@@ -1465,12 +1893,26 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{0x90013, 0x6152},
{0x20010, 0x5a},
{0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
{0x40080, 0xe0},
{0x40081, 0x12},
{0x40082, 0xe0},
{0x40083, 0x12},
{0x40084, 0xe0},
{0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
{0x400fd, 0xf},
{0x400f1, 0xe},
{0x10011, 0x1},
@@ -1505,7 +1947,6 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{0x20088, 0x19},
{0xc0080, 0x0},
{0xd0000, 0x1},
-
};
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
@@ -1515,9 +1956,21 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
-
},
-
+ {
+ /* P1 1866mts 1D */
+ .drate = 1866,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
{
/* P0 3733mts 2D */
.drate = 3733,
@@ -1525,7 +1978,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
},
-
};
/* ddr timing config params */
@@ -1540,7 +1992,227 @@ struct dram_timing_info dram_timing = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, },
+ .fsp_table = { 3733, 1866, 625, },
.fsp_cfg = ddr_dram_fsp_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
};
+
+void set_dram_timings_2gb_lpddr4x(void)
+{
+ /* Initialize DDRC registers */
+ dram_timing.ddrc_cfg[1].val = 0x8000ff;
+ dram_timing.ddrc_cfg[3].val = 0x80000512;
+
+ /* dram fsp cfg */
+ dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x24AB321B;
+ dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x2F2EE233;
+ dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x015B015B;
+ dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x015B2213;
+ dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x13;
+
+ dram_timing.fsp_cfg[1].ddrc_cfg[0].val = 0x12552100;
+ dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x1816B4AA;
+ dram_timing.fsp_cfg[1].ddrc_cfg[9].val = 0x00AA00AA;
+ dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x13;
+
+ dram_timing.fsp_cfg[2].ddrc_cfg[0].val = 0x00061000;
+ dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E62FA48;
+ dram_timing.fsp_cfg[2].ddrc_cfg[9].val = 0x00340034;
+ dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x13;
+
+ /* P0 message block parameter for training firmware */
+ dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
+ dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1308;
+ dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
+ dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1308;
+ dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
+ dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x13;
+ dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
+ dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x13;
+
+ /* P1 message block parameter for training firmware */
+ dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1308;
+ dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1308;
+ dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
+ dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x13;
+ dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
+ dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x13;
+
+ /* P2 message block parameter for training firmware */
+ dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1300;
+ dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1300;
+ dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
+ dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x13;
+ dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
+ dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x13;
+
+ /* P0 2D message block parameter for training firmware */
+ dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1308;
+ dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1308;
+ dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
+ dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x13;
+ dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
+ dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x13;
+}
+
+/* Generated with DDR Tool v3.3.0_7.8-d1cdb7d3 */
+void set_dram_timings_1gb_lpddr4x_900mhz(void)
+{
+ /* Initialize DDRC registers */
+ dram_timing.ddrc_cfg[6].val = 0x4080;
+
+ /* dram fsp cfg */
+ dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x124F2100;
+ dram_timing.fsp_cfg[0].ddrc_cfg[1].val = 0xF877000E;
+ dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x181AE4AA;
+ dram_timing.fsp_cfg[0].ddrc_cfg[3].val = 0x005101E6;
+ dram_timing.fsp_cfg[0].ddrc_cfg[4].val = 0x0E3C0000;
+ dram_timing.fsp_cfg[0].ddrc_cfg[5].val = 0x00009101;
+ dram_timing.fsp_cfg[0].ddrc_cfg[6].val = 0x30900000;
+ dram_timing.fsp_cfg[0].ddrc_cfg[7].val = 0x8A0A0508;
+ dram_timing.fsp_cfg[0].ddrc_cfg[8].val = 0x00000014;
+ dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x007B007B;
+ dram_timing.fsp_cfg[0].ddrc_cfg[12].val = 0x1128110B;
+ dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x007B140A;
+ dram_timing.fsp_cfg[0].ddrc_cfg[14].val = 0x0620071E;
+ dram_timing.fsp_cfg[0].mr_cfg[0].val = 0xB4;
+ dram_timing.fsp_cfg[0].mr_cfg[1].val = 0x1B;
+ dram_timing.fsp_cfg[0].mr_cfg[2].val = 0xE2;
+ dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x15;
+
+ dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x181AE4AA;
+ dram_timing.fsp_cfg[1].mr_cfg[2].val = 0xE2;
+ dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x15;
+
+ dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E660A48;
+ dram_timing.fsp_cfg[2].mr_cfg[2].val = 0xE2;
+ dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x15;
+
+ /* PHY Initialize Configuration */
+ dram_timing.ddrphy_cfg[31].val = 0xb;
+ dram_timing.ddrphy_cfg[86].val = 0x1d3;
+ dram_timing.ddrphy_cfg[90].val = 0x10c;
+ dram_timing.ddrphy_cfg[95].val = 0x10c;
+ dram_timing.ddrphy_cfg[100].val = 0x10c;
+ dram_timing.ddrphy_cfg[122].val = 0x1;
+ /**
+ * NOTE:
+ * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 119
+ * (reg=0x1004a, val=0x500) and 120 (reg=0x1104a, val=0x500) are not
+ * present in the ddr_ddrphy_cfg array. However they were present in array
+ * generated with previous DDR Tool v3.1.0_7.4. We simply set both values
+ * to default value of 0x400 (read with dwc_ddrphy_apb_rd()) here to avoid
+ * any negative side-effects.
+ */
+ dram_timing.ddrphy_cfg[119].val = 0x400;
+ dram_timing.ddrphy_cfg[120].val = 0x400;
+
+ /**
+ * NOTE:
+ * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 101
+ * (reg=0x1004a, val=0x0) and 120 (reg=0x1104a, val=0x0) are not present
+ * in the ddr_ddrphy_trained_csr array. However they were present in array
+ * generated with previous DDR Tool v3.1.0_7.4. We simply set both values
+ * to default 0x0 (like all other ddrphy_trained_csr values) here to avoid
+ * any negative side-effects.
+ */
+ /* PHY trained csr */
+ dram_timing.ddrphy_trained_csr[101].val = 0x0;
+ dram_timing.ddrphy_trained_csr[102].val = 0x0;
+
+ /* P0 message block parameter for training firmware */
+ dram_timing.fsp_msg[0].fsp_cfg[1].val = 0x74a;
+ dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x15;
+ dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x1bb4;
+ dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xe2;
+ dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
+ dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1508;
+ dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x1bb4;
+ dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xe2;
+ dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
+ dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1508;
+ dram_timing.fsp_msg[0].fsp_cfg[20].val = 0xb400;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0xe21b;
+ dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
+ dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x15;
+ dram_timing.fsp_msg[0].fsp_cfg[26].val = 0xb400;
+ dram_timing.fsp_msg[0].fsp_cfg[27].val = 0xe21b;
+ dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
+ dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x15;
+
+ /* P1 message block parameter for training firmware */
+ dram_timing.fsp_msg[1].fsp_cfg[4].val = 0x15;
+ dram_timing.fsp_msg[1].fsp_cfg[12].val = 0xe2;
+ dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1508;
+ dram_timing.fsp_msg[1].fsp_cfg[17].val = 0xe2;
+ dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1508;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0xe21b;
+ dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
+ dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x15;
+ dram_timing.fsp_msg[1].fsp_cfg[28].val = 0xe21b;
+ dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
+ dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x15;
+
+ /* P2 message block parameter for training firmware */
+ dram_timing.fsp_msg[2].fsp_cfg[4].val = 0x15;
+ dram_timing.fsp_msg[2].fsp_cfg[12].val = 0xe2;
+ dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1500;
+ dram_timing.fsp_msg[2].fsp_cfg[17].val = 0xe2;
+ dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1500;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0xe209;
+ dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
+ dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x15;
+ dram_timing.fsp_msg[2].fsp_cfg[28].val = 0xe209;
+ dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
+ dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x15;
+
+ /* P0 2D message block parameter for training firmware */
+ dram_timing.fsp_msg[3].fsp_cfg[1].val = 0x74a;
+ dram_timing.fsp_msg[3].fsp_cfg[3].val = 0x15;
+ dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x1bb4;
+ dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xe2;
+ dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1508;
+ dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x1bb4;
+ dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xe2;
+ dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1508;
+ dram_timing.fsp_msg[3].fsp_cfg[21].val = 0xb400;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0xe21b;
+ dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
+ dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x15;
+ dram_timing.fsp_msg[3].fsp_cfg[27].val = 0xb400;
+ dram_timing.fsp_msg[3].fsp_cfg[28].val = 0xe21b;
+ dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
+ dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x15;
+
+ /* DRAM PHY init engine image */
+ dram_timing.ddrphy_pie[483].val = 0x20d;
+ dram_timing.ddrphy_pie[484].val = 0x74;
+ dram_timing.ddrphy_pie[485].val = 0x48e;
+
+ /* P0 3733mts 1D */
+ dram_timing.fsp_msg[0].drate = 1866;
+
+ /* P0 1866mts 2D */
+ dram_timing.fsp_msg[3].drate = 1866;
+
+ /* ddr timing config params */
+ dram_timing.fsp_table[0] = 1866;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] board: phytec: imx93: Add eeprom-based hardware introspection
2024-11-04 10:41 [PATCH 0/3] Add support for all variants of the phyCORE-i.MX93 SOM Christoph Stoidner
2024-11-04 10:41 ` [PATCH 1/3] board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings Christoph Stoidner
@ 2024-11-04 10:41 ` Christoph Stoidner
2024-11-04 13:53 ` [Upstream] " Wadim Egorov
1 sibling, 1 reply; 9+ messages in thread
From: Christoph Stoidner @ 2024-11-04 10:41 UTC (permalink / raw)
To: u-boot, upstream; +Cc: Christoph Stoidner, Mathieu Othacehe
The phyCORE-i.MX 93 is available in various variants. Relevant variant
options for the spl/u-boot are:
- with or without HS400 support for the eMMC
- with 1GB ram chip, or 2GB ram chip
The phyCORE's eeprom contains all information about the existing variant
options. Add evaluation of the eeprom data to the spl/u-boot to
enable/disable HS400 and to select the appropriate ram configuration at
startup.
Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
Cc: Mathieu Othacehe <m.othacehe@gmail.com>, Christoph Stoidner <c.stoidner@phytec.de>, Stefano Babic <sbabic@denx.de>, Fabio Estevam <festevam@gmail.com>, "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>, Tom Rini <trini@konsulko.com>, Yannic Moog <y.moog@phytec.de>, Primoz Fiser <primoz.fiser@norik.com>, Andrej Picej <andrej.picej@norik.com>, Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi | 19 ++++
arch/arm/mach-imx/imx9/Kconfig | 2 +
arch/arm/mach-imx/imx9/soc.c | 2 +-
board/phytec/common/Kconfig | 8 ++
board/phytec/common/Makefile | 1 +
board/phytec/common/imx93_som_detection.c | 88 +++++++++++++++++++
board/phytec/common/imx93_som_detection.h | 33 +++++++
board/phytec/phycore_imx93/Kconfig | 28 ++++++
board/phytec/phycore_imx93/MAINTAINERS | 5 +-
board/phytec/phycore_imx93/phycore-imx93.c | 52 +++++++++++
board/phytec/phycore_imx93/spl.c | 58 ++++++++++++
11 files changed, 294 insertions(+), 2 deletions(-)
create mode 100644 board/phytec/common/imx93_som_detection.c
create mode 100644 board/phytec/common/imx93_som_detection.h
diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
index 6897c91f4d..25c778bb07 100644
--- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
@@ -305,4 +305,23 @@
};
};
};
+
+ eeprom@50 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ vcc-supply = <&buck4>;
+ };
+
+ eepromid@58 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ compatible = "atmel,24c32";
+ pagesize = <32>;
+ reg = <0x58>;
+ size = <32>;
+ vcc-supply = <&buck4>;
+ };
};
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 5c1054138f..2465e31d73 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -45,6 +45,8 @@ config TARGET_PHYCORE_IMX93
bool "phycore_imx93"
select IMX93
select IMX9_LPDDR4X
+ select OF_BOARD_FIXUP
+ select OF_BOARD_SETUP
endchoice
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 7c28fa39e1..237354f507 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -628,7 +628,7 @@ static int low_drive_freq_update(void *blob)
return 0;
}
-#ifdef CONFIG_OF_BOARD_FIXUP
+#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93)
#ifndef CONFIG_XPL_BUILD
int board_fix_fdt(void *fdt)
{
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
index f394ace786..bc5511707a 100644
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -19,6 +19,14 @@ config PHYTEC_IMX8M_SOM_DETECTION
Support of I2C EEPROM based SoM detection. Supported
for PHYTEC i.MX8MM/i.MX8MP boards
+config PHYTEC_IMX93_SOM_DETECTION
+ bool "Support SoM detection for i.MX93 PHYTEC platforms"
+ depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION
+ default y
+ help
+ Support of I2C EEPROM based SoM detection. Supported
+ for PHYTEC i.MX93 based boards
+
config PHYTEC_AM62_SOM_DETECTION
bool "Support SoM detection for AM62x PHYTEC platforms"
depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \
diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile
index cd78f7686f..8126f7356e 100644
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@@ -10,3 +10,4 @@ endif
obj-y += phytec_som_detection.o phytec_som_detection_blocks.o
obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/
obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
+obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o
diff --git a/board/phytec/common/imx93_som_detection.c b/board/phytec/common/imx93_som_detection.c
new file mode 100644
index 0000000000..b7b237768f
--- /dev/null
+++ b/board/phytec/common/imx93_som_detection.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ */
+
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <i2c.h>
+#include <u-boot/crc.h>
+
+#include "imx93_som_detection.h"
+
+extern struct phytec_eeprom_data eeprom_data;
+
+#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION)
+
+/* Check if the SoM is actually one of the following products:
+ * - i.MX93
+ *
+ * Returns 0 in case it's a known SoM. Otherwise, returns 1.
+ */
+u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+{
+ u8 som;
+
+ if (!data)
+ data = &eeprom_data;
+
+ /* Early API revisions are not supported */
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+ return 1;
+
+ som = data->payload.data.data_api2.som_no;
+ debug("%s: som id: %u\n", __func__, som);
+
+ if (som == PHYTEC_IMX93_SOM && is_imx93())
+ return 0;
+
+ pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__);
+ return 1;
+}
+
+/*
+ * Filter PHYTEC i.MX93 SoM options by option index
+ *
+ * Returns:
+ * - option value
+ * - PHYTEC_EEPROM_INVAL when the data is invalid
+ *
+ */
+u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+ enum phytec_imx93_option_index idx)
+{
+ char *opt;
+ u8 opt_id;
+
+ if (!data)
+ data = &eeprom_data;
+
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+ return PHYTEC_EEPROM_INVAL;
+
+ opt = phytec_get_opt(data);
+ if (opt)
+ opt_id = PHYTEC_GET_OPTION(opt[idx]);
+ else
+ opt_id = PHYTEC_EEPROM_INVAL;
+
+ debug("%s: opt[%d] id: %u\n", __func__, idx, opt_id);
+ return opt_id;
+}
+
+#else
+
+inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+{
+ return 1;
+}
+
+inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+ enum phytec_imx93_option_index idx)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */
diff --git a/board/phytec/common/imx93_som_detection.h b/board/phytec/common/imx93_som_detection.h
new file mode 100644
index 0000000000..bb170bafff
--- /dev/null
+++ b/board/phytec/common/imx93_som_detection.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ */
+
+#ifndef _PHYTEC_IMX93_SOM_DETECTION_H
+#define _PHYTEC_IMX93_SOM_DETECTION_H
+
+#include "phytec_som_detection.h"
+
+#define PHYTEC_IMX93_SOM 77
+
+enum phytec_imx93_option_index {
+ PHYTEC_IMX93_OPT_DDR = 0,
+ PHYTEC_IMX93_OPT_EMMC,
+ PHYTEC_IMX93_OPT_CPU,
+ PHYTEC_IMX93_OPT_FREQ,
+ PHYTEC_IMX93_OPT_NPU,
+ PHYTEC_IMX93_OPT_DISP,
+ PHYTEC_IMX93_OPT_ETH,
+ PHYTEC_IMX93_OPT_FEAT,
+ PHYTEC_IMX93_OPT_TEMP,
+ PHYTEC_IMX93_OPT_BOOT,
+ PHYTEC_IMX93_OPT_LED,
+ PHYTEC_IMX93_OPT_EEPROM,
+};
+
+u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+ enum phytec_imx93_option_index idx);
+
+#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */
diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig
index a70104cb79..09f26e89e3 100644
--- a/board/phytec/phycore_imx93/Kconfig
+++ b/board/phytec/phycore_imx93/Kconfig
@@ -10,4 +10,32 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "phycore_imx93"
+config PHYCORE_IMX93_RAM_TYPE_FIX
+ bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting"
+ default false
+ help
+ RAM type and size is being automatically detected with the help
+ of the PHYTEC EEPROM introspection data.
+ Set RAM type to a fix value instead.
+
+choice
+ prompt "phyCORE-i.MX93 RAM type"
+ depends on PHYCORE_IMX93_RAM_TYPE_FIX
+ default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
+
+config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
+ bool "LPDDR4X 1GB RAM"
+ help
+ Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB
+ for phyCORE-i.MX93.
+
+config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB
+ bool "LPDDR4X 2GB RAM"
+ help
+ Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB
+ for phyCORE-i.MX93.
+
+endchoice
+
+source "board/phytec/common/Kconfig"
endif
diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS
index 9e91a29dc3..cea817ffdc 100644
--- a/board/phytec/phycore_imx93/MAINTAINERS
+++ b/board/phytec/phycore_imx93/MAINTAINERS
@@ -1,10 +1,13 @@
phyCORE-i.MX93
-M: Mathieu Othacehe <m.othacehe@gmail.com>
+M: Mathieu Othacehe <m.othacehe@gmail.com>
+R: Christoph Stoidner <c.stoidner@phytec.de>
W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
S: Maintained
F: arch/arm/dts/imx93-phyboard-segin.dts
F: arch/arm/dts/imx93-phycore-som.dtsi
F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
F: board/phytec/phycore_imx93/
+F: board/phytec/common/imx93_som_detection.c
+F: board/phytec/common/imx93_som_detection.h
F: configs/imx93-phyboard-segin_defconfig
F: include/configs/phycore_imx93.h
diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c
index 085c8e195a..bb7938604d 100644
--- a/board/phytec/phycore_imx93/phycore-imx93.c
+++ b/board/phytec/phycore_imx93/phycore-imx93.c
@@ -3,6 +3,7 @@
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Christoph Stoidner <c.stoidner@phytec.de>
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
*/
#include <asm/arch-imx9/ccm_regs.h>
@@ -12,11 +13,21 @@
#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
+#include <fdt_support.h>
+
+#include "../common/imx93_som_detection.h"
DECLARE_GLOBAL_DATA_PTR;
+#define EEPROM_ADDR 0x50
+
int board_init(void)
{
+ int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
+
+ if (ret)
+ printf("%s: EEPROM data init failed\n", __func__);
+
return 0;
}
@@ -40,3 +51,44 @@ int board_late_init(void)
return 0;
}
+
+static void emmc_fixup(void *blob, struct phytec_eeprom_data *data)
+{
+ u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT);
+ int offset;
+
+ if (option == PHYTEC_EEPROM_INVAL)
+ goto err;
+
+ /* Check "IO Voltage 1v8" flag is set */
+ if (option & 0x01) {
+ offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc",
+ 0x42850000);
+ if (offset)
+ fdt_delprop(blob, offset, "no-1-8-v");
+ else
+ goto err;
+ }
+
+ return;
+err:
+ printf("Could not detect eMMC VDD-IO. Fall back to default.\n");
+}
+
+int board_fix_fdt(void *blob)
+{
+ struct phytec_eeprom_data data;
+
+ phytec_eeprom_data_setup(&data, 2, EEPROM_ADDR);
+
+ emmc_fixup(blob, &data);
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ emmc_fixup(blob, NULL);
+
+ return 0;
+}
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 17a8736c73..cf9c94eb45 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -3,6 +3,7 @@
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Christoph Stoidner <c.stoidner@phytec.de>
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
*/
#include <asm/arch/clock.h>
@@ -20,6 +21,8 @@
#include <power/pca9450.h>
#include <spl.h>
+#include "../common/imx93_som_detection.h"
+
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -27,6 +30,13 @@ DECLARE_GLOBAL_DATA_PTR;
* when pca9451a support is added.
*/
#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5)
+#define EEPROM_ADDR 0x50
+
+/*
+ * Prototypes of automatically generated ram config file
+ */
+void set_dram_timings_2gb_lpddr4x(void);
+void set_dram_timings_1gb_lpddr4x_900mhz(void);
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
@@ -44,8 +54,56 @@ void spl_board_init(void)
puts("Normal Boot\n");
}
+enum phytec_imx93_ddr_eeprom_code {
+ INVALID = PHYTEC_EEPROM_INVAL,
+ PHYTEC_IMX93_LPDDR4X_512MB = 0,
+ PHYTEC_IMX93_LPDDR4X_1GB = 1,
+ PHYTEC_IMX93_LPDDR4X_2GB = 2,
+ PHYTEC_IMX93_LPDDR4_512MB = 3,
+ PHYTEC_IMX93_LPDDR4_1GB = 4,
+ PHYTEC_IMX93_LPDDR4_2GB = 5,
+};
+
void spl_dram_init(void)
{
+ int ret;
+ enum phytec_imx93_ddr_eeprom_code ddr_opt = INVALID;
+
+ /* NOTE: In SPL lpi2c3 is mapped to bus 0 */
+ ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
+ if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
+ goto out;
+
+ ret = phytec_imx93_detect(NULL);
+ if (!ret)
+ phytec_print_som_info(NULL);
+
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB))
+ ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB))
+ ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB;
+ } else {
+ ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR);
+ }
+
+ switch (ddr_opt) {
+ case PHYTEC_IMX93_LPDDR4X_1GB:
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
+ set_dram_timings_1gb_lpddr4x_900mhz();
+ break;
+ case PHYTEC_IMX93_LPDDR4X_2GB:
+ set_dram_timings_2gb_lpddr4x();
+ break;
+ default:
+ goto out;
+ }
+ ddr_init(&dram_timing);
+ return;
+out:
+ puts("Could not detect correct RAM type and size. Fall back to default.\n");
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
+ set_dram_timings_1gb_lpddr4x_900mhz();
ddr_init(&dram_timing);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Upstream] [PATCH 1/3] board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings
2024-11-04 10:41 ` [PATCH 1/3] board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings Christoph Stoidner
@ 2024-11-04 12:16 ` Teresa Remmet
2024-11-05 13:47 ` Christoph Stoidner
2024-11-04 12:30 ` Fabio Estevam
1 sibling, 1 reply; 9+ messages in thread
From: Teresa Remmet @ 2024-11-04 12:16 UTC (permalink / raw)
To: PHYTEC Upstream, Christoph Stoidner, u-boot@lists.denx.de
Cc: m.othacehe@gmail.com
Hello Christoph,
Am Montag, dem 04.11.2024 um 11:41 +0100 schrieb Christoph Stoidner:
> The phyCORE-i.MX 93 is available with a 1GB ram chip or a 2GB ram
> chip.
> Add the ram timings for the 2GB chip, in form of a diff compared
> to the existing LPDDR4X 1GB timings. With that, the SPL can select
> the
> appropriate timings at startup.
it looks like you also updated the existing 1GB RAM timings with a
new version of the DDR Tool. You should reflect this in the commit
message, too.
>
> Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
> Cc: Mathieu Othacehe <m.othacehe@gmail.com>, Christoph Stoidner
> <c.stoidner@phytec.de>, Tom Rini <trini@konsulko.com>, Yannic Moog
> <y.moog@phytec.de>, Primoz Fiser <primoz.fiser@norik.com>, Andrej
> Picej <andrej.picej@norik.com>, Wadim Egorov <w.egorov@phytec.de>
You added here quite a lot of people which are actually not in CC of
this patch. You should check that.
And each entry should be in a separate line.
Teresa
> ---
> board/phytec/phycore_imx93/lpddr4_timing.c | 794
> +++++++++++++++++++--
> 1 file changed, 733 insertions(+), 61 deletions(-)
>
> diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c
> b/board/phytec/phycore_imx93/lpddr4_timing.c
> index 2111972a40..b7132ffade 100644
> --- a/board/phytec/phycore_imx93/lpddr4_timing.c
> +++ b/board/phytec/phycore_imx93/lpddr4_timing.c
> @@ -1,24 +1,24 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2023 NXP
> - * Copyright (C) 2023 PHYTEC Messtechnik GmbH
> + * Copyright 2024 NXP
> + * Copyright (C) 2024 PHYTEC Messtechnik GmbH
> * Christoph Stoidner <c.stoidner@phytec.de>
> *
> - * Code generated with DDR Tool v1.0.0.
> + * Code generated with DDR Tool v3.1.0_7.4.
> */
>
> #include <linux/kernel.h>
> #include <asm/arch/ddr.h>
>
> +/* Initialize DDRC registers */
> static struct dram_cfg_param ddr_ddrc_cfg[] = {
> - /** Initialize DDRC registers **/
> {0x4e300110, 0x44100001},
> {0x4e300000, 0x8000bf},
> {0x4e300008, 0x0},
> {0x4e300080, 0x80000412},
> {0x4e300084, 0x0},
> {0x4e300114, 0x1002},
> - {0x4e300260, 0x4080},
> + {0x4e300260, 0x80},
> {0x4e300f04, 0x80},
> {0x4e300800, 0x43b30002},
> {0x4e300804, 0x1f1f1f1f},
> @@ -31,18 +31,17 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
> {0x4e301254, 0x0},
> {0x4e301258, 0x0},
> {0x4e30125c, 0x0},
> -
> };
>
> /* dram fsp cfg */
> static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
> {
> {
> - {0x4e300100, 0x24A0421B},
> + {0x4e300100, 0x24A0321B},
> {0x4e300104, 0xF8EE001B},
> - {0x4e300108, 0x2F263233},
> - {0x4e30010C, 0x0005E18B},
> - {0x4e300124, 0x1C770000},
> + {0x4e300108, 0x2F2E3233},
> + {0x4e30010C, 0x0005C18B},
> + {0x4e300124, 0x1C790000},
> {0x4e300160, 0x00009102},
> {0x4e30016C, 0x35F00000},
> {0x4e300170, 0x8B0B0608},
> @@ -50,21 +49,73 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
> {0x4e300254, 0x00FE00FE},
> {0x4e300258, 0x00000008},
> {0x4e30025C, 0x00000400},
> - {0x4e300300, 0x224F2215},
> + {0x4e300300, 0x224F2213},
> {0x4e300304, 0x00FE2213},
> - {0x4e300308, 0x0A3C0E3C},
> + {0x4e300308, 0x0A380E3D},
> },
> {
> {0x01, 0xE4},
> {0x02, 0x36},
> - {0x03, 0xF2},
> - {0x0b, 0x46},
> - {0x0c, 0x11},
> - {0x0e, 0x11},
> + {0x03, 0x22},
> + {0x0b, 0x44},
> + {0x0c, 0x1E},
> + {0x0e, 0x12},
> + {0x16, 0x04},
> + },
> + 0,
> + },
> + {
> + {
> + {0x4e300100, 0x124F2100},
> + {0x4e300104, 0xF877000E},
> + {0x4e300108, 0x1816E4AA},
> + {0x4e30010C, 0x005101E6},
> + {0x4e300124, 0x0E3C0000},
> + {0x4e300160, 0x00009101},
> + {0x4e30016C, 0x30900000},
> + {0x4e300170, 0x8A0A0508},
> + {0x4e300250, 0x00000014},
> + {0x4e300254, 0x007B007B},
> + {0x4e300258, 0x00000008},
> + {0x4e30025C, 0x00000400},
> + },
> + {
> + {0x01, 0xB4},
> + {0x02, 0x1B},
> + {0x03, 0x22},
> + {0x0b, 0x44},
> + {0x0c, 0x1E},
> + {0x0e, 0x12},
> {0x16, 0x04},
> },
> 0,
> },
> + {
> + {
> + {0x4e300100, 0x00051000},
> + {0x4e300104, 0xF855000A},
> + {0x4e300108, 0x6E620A48},
> + {0x4e30010C, 0x0031010D},
> + {0x4e300124, 0x04C50000},
> + {0x4e300160, 0x00009100},
> + {0x4e30016C, 0x30000000},
> + {0x4e300170, 0x89090408},
> + {0x4e300250, 0x00000007},
> + {0x4e300254, 0x00240024},
> + {0x4e300258, 0x00000008},
> + {0x4e30025C, 0x00000400},
> + },
> + {
> + {0x01, 0x94},
> + {0x02, 0x9},
> + {0x03, 0x22},
> + {0x0b, 0x44},
> + {0x0c, 0x1E},
> + {0x0e, 0x12},
> + {0x16, 0x04},
> + },
> + 1,
> + },
>
> };
>
> @@ -90,25 +141,65 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] =
> {
> {0x1015f, 0x5ff},
> {0x1105f, 0x5ff},
> {0x1115f, 0x5ff},
> + {0x11005f, 0x5ff},
> + {0x11015f, 0x5ff},
> + {0x11105f, 0x5ff},
> + {0x11115f, 0x5ff},
> + {0x21005f, 0x5ff},
> + {0x21015f, 0x5ff},
> + {0x21105f, 0x5ff},
> + {0x21115f, 0x5ff},
> {0x55, 0x1ff},
> {0x1055, 0x1ff},
> {0x2055, 0x1ff},
> {0x200c5, 0x19},
> + {0x1200c5, 0xb},
> + {0x2200c5, 0x7},
> {0x2002e, 0x2},
> + {0x12002e, 0x2},
> + {0x22002e, 0x2},
> {0x90204, 0x0},
> + {0x190204, 0x0},
> + {0x290204, 0x0},
> {0x20024, 0x1e3},
> {0x2003a, 0x2},
> {0x2007d, 0x212},
> {0x2007c, 0x61},
> + {0x120024, 0x1e3},
> + {0x2003a, 0x2},
> + {0x12007d, 0x212},
> + {0x12007c, 0x61},
> + {0x220024, 0x1e3},
> + {0x2003a, 0x2},
> + {0x22007d, 0x212},
> + {0x22007c, 0x61},
> {0x20056, 0x3},
> + {0x120056, 0x3},
> + {0x220056, 0x3},
> {0x1004d, 0x600},
> {0x1014d, 0x600},
> {0x1104d, 0x600},
> {0x1114d, 0x600},
> - {0x10049, 0xe00},
> - {0x10149, 0xe00},
> - {0x11049, 0xe00},
> - {0x11149, 0xe00},
> + {0x11004d, 0x600},
> + {0x11014d, 0x600},
> + {0x11104d, 0x600},
> + {0x11114d, 0x600},
> + {0x21004d, 0x600},
> + {0x21014d, 0x600},
> + {0x21104d, 0x600},
> + {0x21114d, 0x600},
> + {0x10049, 0x604},
> + {0x10149, 0x604},
> + {0x11049, 0x604},
> + {0x11149, 0x604},
> + {0x110049, 0x604},
> + {0x110149, 0x604},
> + {0x111049, 0x604},
> + {0x111149, 0x604},
> + {0x210049, 0x604},
> + {0x210149, 0x604},
> + {0x211049, 0x604},
> + {0x211149, 0x604},
> {0x43, 0x60},
> {0x1043, 0x60},
> {0x2043, 0x60},
> @@ -117,14 +208,30 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] =
> {
> {0x20050, 0x0},
> {0x2009b, 0x2},
> {0x20008, 0x3a5},
> + {0x120008, 0x1d3},
> + {0x220008, 0x9c},
> {0x20088, 0x9},
> - {0x200b2, 0x10c},
> + {0x200b2, 0x104},
> {0x10043, 0x5a1},
> {0x10143, 0x5a1},
> {0x11043, 0x5a1},
> {0x11143, 0x5a1},
> + {0x1200b2, 0x104},
> + {0x110043, 0x5a1},
> + {0x110143, 0x5a1},
> + {0x111043, 0x5a1},
> + {0x111143, 0x5a1},
> + {0x2200b2, 0x104},
> + {0x210043, 0x5a1},
> + {0x210143, 0x5a1},
> + {0x211043, 0x5a1},
> + {0x211143, 0x5a1},
> {0x200fa, 0x2},
> + {0x1200fa, 0x2},
> + {0x2200fa, 0x2},
> {0x20019, 0x1},
> + {0x120019, 0x1},
> + {0x220019, 0x1},
> {0x200f0, 0x600},
> {0x200f1, 0x0},
> {0x200f2, 0x4444},
> @@ -133,42 +240,83 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] =
> {
> {0x200f5, 0x0},
> {0x200f6, 0x0},
> {0x200f7, 0xf000},
> + {0x1004a, 0x500},
> + {0x1104a, 0x500},
> {0x20025, 0x0},
> - {0x2002d, 0x1},
> + {0x2002d, 0x0},
> + {0x12002d, 0x0},
> + {0x22002d, 0x0},
> {0x2002c, 0x0},
> {0x20021, 0x0},
> {0x200c7, 0x21},
> {0x1200c7, 0x21},
> {0x200ca, 0x24},
> {0x1200ca, 0x24},
> -
> };
>
> -/* ddr phy trained csr */
> +/* PHY trained csr */
> static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> {0x1005f, 0x0},
> {0x1015f, 0x0},
> {0x1105f, 0x0},
> {0x1115f, 0x0},
> + {0x11005f, 0x0},
> + {0x11015f, 0x0},
> + {0x11105f, 0x0},
> + {0x11115f, 0x0},
> + {0x21005f, 0x0},
> + {0x21015f, 0x0},
> + {0x21105f, 0x0},
> + {0x21115f, 0x0},
> {0x55, 0x0},
> {0x1055, 0x0},
> {0x2055, 0x0},
> {0x200c5, 0x0},
> + {0x1200c5, 0x0},
> + {0x2200c5, 0x0},
> {0x2002e, 0x0},
> + {0x12002e, 0x0},
> + {0x22002e, 0x0},
> {0x90204, 0x0},
> + {0x190204, 0x0},
> + {0x290204, 0x0},
> {0x20024, 0x0},
> {0x2003a, 0x0},
> {0x2007d, 0x0},
> {0x2007c, 0x0},
> + {0x120024, 0x0},
> + {0x12007d, 0x0},
> + {0x12007c, 0x0},
> + {0x220024, 0x0},
> + {0x22007d, 0x0},
> + {0x22007c, 0x0},
> {0x20056, 0x0},
> + {0x120056, 0x0},
> + {0x220056, 0x0},
> {0x1004d, 0x0},
> {0x1014d, 0x0},
> {0x1104d, 0x0},
> {0x1114d, 0x0},
> + {0x11004d, 0x0},
> + {0x11014d, 0x0},
> + {0x11104d, 0x0},
> + {0x11114d, 0x0},
> + {0x21004d, 0x0},
> + {0x21014d, 0x0},
> + {0x21104d, 0x0},
> + {0x21114d, 0x0},
> {0x10049, 0x0},
> {0x10149, 0x0},
> {0x11049, 0x0},
> {0x11149, 0x0},
> + {0x110049, 0x0},
> + {0x110149, 0x0},
> + {0x111049, 0x0},
> + {0x111149, 0x0},
> + {0x210049, 0x0},
> + {0x210149, 0x0},
> + {0x211049, 0x0},
> + {0x211149, 0x0},
> {0x43, 0x0},
> {0x1043, 0x0},
> {0x2043, 0x0},
> @@ -177,14 +325,30 @@ static struct dram_cfg_param
> ddr_ddrphy_trained_csr[] = {
> {0x20050, 0x0},
> {0x2009b, 0x0},
> {0x20008, 0x0},
> + {0x120008, 0x0},
> + {0x220008, 0x0},
> {0x20088, 0x0},
> {0x200b2, 0x0},
> {0x10043, 0x0},
> {0x10143, 0x0},
> {0x11043, 0x0},
> {0x11143, 0x0},
> + {0x1200b2, 0x0},
> + {0x110043, 0x0},
> + {0x110143, 0x0},
> + {0x111043, 0x0},
> + {0x111143, 0x0},
> + {0x2200b2, 0x0},
> + {0x210043, 0x0},
> + {0x210143, 0x0},
> + {0x211043, 0x0},
> + {0x211143, 0x0},
> {0x200fa, 0x0},
> + {0x1200fa, 0x0},
> + {0x2200fa, 0x0},
> {0x20019, 0x0},
> + {0x120019, 0x0},
> + {0x220019, 0x0},
> {0x200f0, 0x0},
> {0x200f1, 0x0},
> {0x200f2, 0x0},
> @@ -193,8 +357,12 @@ static struct dram_cfg_param
> ddr_ddrphy_trained_csr[] = {
> {0x200f5, 0x0},
> {0x200f6, 0x0},
> {0x200f7, 0x0},
> + {0x1004a, 0x0},
> + {0x1104a, 0x0},
> {0x20025, 0x0},
> {0x2002d, 0x0},
> + {0x12002d, 0x0},
> + {0x22002d, 0x0},
> {0x2002c, 0x0},
> {0xd0000, 0x0},
> {0x90000, 0x0},
> @@ -682,6 +850,14 @@ static struct dram_cfg_param
> ddr_ddrphy_trained_csr[] = {
> {0x2000c, 0x0},
> {0x2000d, 0x0},
> {0x2000e, 0x0},
> + {0x12000b, 0x0},
> + {0x12000c, 0x0},
> + {0x12000d, 0x0},
> + {0x12000e, 0x0},
> + {0x22000b, 0x0},
> + {0x22000c, 0x0},
> + {0x22000d, 0x0},
> + {0x22000e, 0x0},
> {0x9000c, 0x0},
> {0x9000d, 0x0},
> {0x9000e, 0x0},
> @@ -692,12 +868,26 @@ static struct dram_cfg_param
> ddr_ddrphy_trained_csr[] = {
> {0x90013, 0x0},
> {0x20010, 0x0},
> {0x20011, 0x0},
> + {0x120010, 0x0},
> + {0x120011, 0x0},
> {0x40080, 0x0},
> {0x40081, 0x0},
> {0x40082, 0x0},
> {0x40083, 0x0},
> {0x40084, 0x0},
> {0x40085, 0x0},
> + {0x140080, 0x0},
> + {0x140081, 0x0},
> + {0x140082, 0x0},
> + {0x140083, 0x0},
> + {0x140084, 0x0},
> + {0x140085, 0x0},
> + {0x240080, 0x0},
> + {0x240081, 0x0},
> + {0x240082, 0x0},
> + {0x240083, 0x0},
> + {0x240084, 0x0},
> + {0x240085, 0x0},
> {0x400fd, 0x0},
> {0x400f1, 0x0},
> {0x10011, 0x0},
> @@ -866,6 +1056,160 @@ static struct dram_cfg_param
> ddr_ddrphy_trained_csr[] = {
> {0x90207, 0x0},
> {0x90208, 0x0},
> {0x20020, 0x0},
> + {0x100080, 0x0},
> + {0x101080, 0x0},
> + {0x102080, 0x0},
> + {0x110020, 0x0},
> + {0x110080, 0x0},
> + {0x110081, 0x0},
> + {0x1100d0, 0x0},
> + {0x1100d1, 0x0},
> + {0x11008c, 0x0},
> + {0x11008d, 0x0},
> + {0x110180, 0x0},
> + {0x110181, 0x0},
> + {0x1101d0, 0x0},
> + {0x1101d1, 0x0},
> + {0x11018c, 0x0},
> + {0x11018d, 0x0},
> + {0x1100c0, 0x0},
> + {0x1100c1, 0x0},
> + {0x1101c0, 0x0},
> + {0x1101c1, 0x0},
> + {0x1102c0, 0x0},
> + {0x1102c1, 0x0},
> + {0x1103c0, 0x0},
> + {0x1103c1, 0x0},
> + {0x1104c0, 0x0},
> + {0x1104c1, 0x0},
> + {0x1105c0, 0x0},
> + {0x1105c1, 0x0},
> + {0x1106c0, 0x0},
> + {0x1106c1, 0x0},
> + {0x1107c0, 0x0},
> + {0x1107c1, 0x0},
> + {0x1108c0, 0x0},
> + {0x1108c1, 0x0},
> + {0x1100ae, 0x0},
> + {0x1100af, 0x0},
> + {0x111020, 0x0},
> + {0x111080, 0x0},
> + {0x111081, 0x0},
> + {0x1110d0, 0x0},
> + {0x1110d1, 0x0},
> + {0x11108c, 0x0},
> + {0x11108d, 0x0},
> + {0x111180, 0x0},
> + {0x111181, 0x0},
> + {0x1111d0, 0x0},
> + {0x1111d1, 0x0},
> + {0x11118c, 0x0},
> + {0x11118d, 0x0},
> + {0x1110c0, 0x0},
> + {0x1110c1, 0x0},
> + {0x1111c0, 0x0},
> + {0x1111c1, 0x0},
> + {0x1112c0, 0x0},
> + {0x1112c1, 0x0},
> + {0x1113c0, 0x0},
> + {0x1113c1, 0x0},
> + {0x1114c0, 0x0},
> + {0x1114c1, 0x0},
> + {0x1115c0, 0x0},
> + {0x1115c1, 0x0},
> + {0x1116c0, 0x0},
> + {0x1116c1, 0x0},
> + {0x1117c0, 0x0},
> + {0x1117c1, 0x0},
> + {0x1118c0, 0x0},
> + {0x1118c1, 0x0},
> + {0x1110ae, 0x0},
> + {0x1110af, 0x0},
> + {0x190201, 0x0},
> + {0x190202, 0x0},
> + {0x190203, 0x0},
> + {0x190205, 0x0},
> + {0x190206, 0x0},
> + {0x190207, 0x0},
> + {0x190208, 0x0},
> + {0x120020, 0x0},
> + {0x200080, 0x0},
> + {0x201080, 0x0},
> + {0x202080, 0x0},
> + {0x210020, 0x0},
> + {0x210080, 0x0},
> + {0x210081, 0x0},
> + {0x2100d0, 0x0},
> + {0x2100d1, 0x0},
> + {0x21008c, 0x0},
> + {0x21008d, 0x0},
> + {0x210180, 0x0},
> + {0x210181, 0x0},
> + {0x2101d0, 0x0},
> + {0x2101d1, 0x0},
> + {0x21018c, 0x0},
> + {0x21018d, 0x0},
> + {0x2100c0, 0x0},
> + {0x2100c1, 0x0},
> + {0x2101c0, 0x0},
> + {0x2101c1, 0x0},
> + {0x2102c0, 0x0},
> + {0x2102c1, 0x0},
> + {0x2103c0, 0x0},
> + {0x2103c1, 0x0},
> + {0x2104c0, 0x0},
> + {0x2104c1, 0x0},
> + {0x2105c0, 0x0},
> + {0x2105c1, 0x0},
> + {0x2106c0, 0x0},
> + {0x2106c1, 0x0},
> + {0x2107c0, 0x0},
> + {0x2107c1, 0x0},
> + {0x2108c0, 0x0},
> + {0x2108c1, 0x0},
> + {0x2100ae, 0x0},
> + {0x2100af, 0x0},
> + {0x211020, 0x0},
> + {0x211080, 0x0},
> + {0x211081, 0x0},
> + {0x2110d0, 0x0},
> + {0x2110d1, 0x0},
> + {0x21108c, 0x0},
> + {0x21108d, 0x0},
> + {0x211180, 0x0},
> + {0x211181, 0x0},
> + {0x2111d0, 0x0},
> + {0x2111d1, 0x0},
> + {0x21118c, 0x0},
> + {0x21118d, 0x0},
> + {0x2110c0, 0x0},
> + {0x2110c1, 0x0},
> + {0x2111c0, 0x0},
> + {0x2111c1, 0x0},
> + {0x2112c0, 0x0},
> + {0x2112c1, 0x0},
> + {0x2113c0, 0x0},
> + {0x2113c1, 0x0},
> + {0x2114c0, 0x0},
> + {0x2114c1, 0x0},
> + {0x2115c0, 0x0},
> + {0x2115c1, 0x0},
> + {0x2116c0, 0x0},
> + {0x2116c1, 0x0},
> + {0x2117c0, 0x0},
> + {0x2117c1, 0x0},
> + {0x2118c0, 0x0},
> + {0x2118c1, 0x0},
> + {0x2110ae, 0x0},
> + {0x2110af, 0x0},
> + {0x290201, 0x0},
> + {0x290202, 0x0},
> + {0x290203, 0x0},
> + {0x290205, 0x0},
> + {0x290206, 0x0},
> + {0x290207, 0x0},
> + {0x290208, 0x0},
> + {0x220020, 0x0},
> {0x20077, 0x0},
> {0x20072, 0x0},
> {0x20073, 0x0},
> @@ -888,7 +1232,6 @@ static struct dram_cfg_param
> ddr_ddrphy_trained_csr[] = {
> {0x11640, 0x0},
> {0x11740, 0x0},
> {0x11840, 0x0},
> -
> };
>
> /* P0 message block parameter for training firmware */
> @@ -896,7 +1239,7 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
> {0xd0000, 0x0},
> {0x54003, 0xe94},
> {0x54004, 0x4},
> - {0x54006, 0x15},
> + {0x54006, 0x14},
> {0x54008, 0x131f},
> {0x54009, 0xc8},
> {0x5400b, 0x4},
> @@ -904,36 +1247,113 @@ static struct dram_cfg_param ddr_fsp0_cfg[] =
> {
> {0x5400f, 0x100},
> {0x54012, 0x110},
> {0x54019, 0x36e4},
> - {0x5401a, 0xf2},
> - {0x5401b, 0x1146},
> - {0x5401c, 0x1108},
> + {0x5401a, 0x22},
> + {0x5401b, 0x1e44},
> + {0x5401c, 0x1208},
> {0x5401e, 0x4},
> {0x5401f, 0x36e4},
> - {0x54020, 0xf2},
> - {0x54021, 0x1146},
> - {0x54022, 0x1108},
> + {0x54020, 0x22},
> + {0x54021, 0x1e44},
> + {0x54022, 0x1208},
> {0x54024, 0x4},
> {0x54032, 0xe400},
> - {0x54033, 0xf236},
> - {0x54034, 0x4600},
> - {0x54035, 0x811},
> - {0x54036, 0x11},
> + {0x54033, 0x2236},
> + {0x54034, 0x4400},
> + {0x54035, 0x81e},
> + {0x54036, 0x12},
> {0x54037, 0x400},
> {0x54038, 0xe400},
> - {0x54039, 0xf236},
> - {0x5403a, 0x4600},
> - {0x5403b, 0x811},
> - {0x5403c, 0x11},
> + {0x54039, 0x2236},
> + {0x5403a, 0x4400},
> + {0x5403b, 0x81e},
> + {0x5403c, 0x12},
> + {0x5403d, 0x400},
> + {0xd0000, 0x1}
> +};
> +
> +/* P1 message block parameter for training firmware */
> +static struct dram_cfg_param ddr_fsp1_cfg[] = {
> + {0xd0000, 0x0},
> + {0x54002, 0x1},
> + {0x54003, 0x74a},
> + {0x54004, 0x4},
> + {0x54006, 0x14},
> + {0x54008, 0x121f},
> + {0x54009, 0xc8},
> + {0x5400b, 0x4},
> + {0x5400d, 0x100},
> + {0x5400f, 0x100},
> + {0x54012, 0x110},
> + {0x54019, 0x1bb4},
> + {0x5401a, 0x22},
> + {0x5401b, 0x1e44},
> + {0x5401c, 0x1208},
> + {0x5401e, 0x4},
> + {0x5401f, 0x1bb4},
> + {0x54020, 0x22},
> + {0x54021, 0x1e44},
> + {0x54022, 0x1208},
> + {0x54024, 0x4},
> + {0x54032, 0xb400},
> + {0x54033, 0x221b},
> + {0x54034, 0x4400},
> + {0x54035, 0x81e},
> + {0x54036, 0x12},
> + {0x54037, 0x400},
> + {0x54038, 0xb400},
> + {0x54039, 0x221b},
> + {0x5403a, 0x4400},
> + {0x5403b, 0x81e},
> + {0x5403c, 0x12},
> + {0x5403d, 0x400},
> + {0xd0000, 0x1}
> +};
> +
> +/* P2 message block parameter for training firmware */
> +static struct dram_cfg_param ddr_fsp2_cfg[] = {
> + {0xd0000, 0x0},
> + {0x54002, 0x102},
> + {0x54003, 0x270},
> + {0x54004, 0x4},
> + {0x54006, 0x14},
> + {0x54008, 0x121f},
> + {0x54009, 0xc8},
> + {0x5400b, 0x4},
> + {0x5400d, 0x100},
> + {0x5400f, 0x100},
> + {0x54012, 0x110},
> + {0x54019, 0x994},
> + {0x5401a, 0x22},
> + {0x5401b, 0x1e44},
> + {0x5401c, 0x1200},
> + {0x5401e, 0x4},
> + {0x5401f, 0x994},
> + {0x54020, 0x22},
> + {0x54021, 0x1e44},
> + {0x54022, 0x1200},
> + {0x54024, 0x4},
> + {0x54032, 0x9400},
> + {0x54033, 0x2209},
> + {0x54034, 0x4400},
> + {0x54035, 0x1e},
> + {0x54036, 0x12},
> + {0x54037, 0x400},
> + {0x54038, 0x9400},
> + {0x54039, 0x2209},
> + {0x5403a, 0x4400},
> + {0x5403b, 0x1e},
> + {0x5403c, 0x12},
> {0x5403d, 0x400},
> {0xd0000, 0x1}
> };
>
> +
> /* P0 2D message block parameter for training firmware */
> static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> {0xd0000, 0x0},
> {0x54003, 0xe94},
> {0x54004, 0x4},
> - {0x54006, 0x15},
> + {0x54006, 0x14},
> {0x54008, 0x61},
> {0x54009, 0xc8},
> {0x5400b, 0x4},
> @@ -942,26 +1362,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[]
> = {
> {0x54010, 0x2080},
> {0x54012, 0x110},
> {0x54019, 0x36e4},
> - {0x5401a, 0xf2},
> - {0x5401b, 0x1146},
> - {0x5401c, 0x1108},
> + {0x5401a, 0x22},
> + {0x5401b, 0x1e44},
> + {0x5401c, 0x1208},
> {0x5401e, 0x4},
> {0x5401f, 0x36e4},
> - {0x54020, 0xf2},
> - {0x54021, 0x1146},
> - {0x54022, 0x1108},
> + {0x54020, 0x22},
> + {0x54021, 0x1e44},
> + {0x54022, 0x1208},
> {0x54024, 0x4},
> {0x54032, 0xe400},
> - {0x54033, 0xf236},
> - {0x54034, 0x4600},
> - {0x54035, 0x811},
> - {0x54036, 0x11},
> + {0x54033, 0x2236},
> + {0x54034, 0x4400},
> + {0x54035, 0x81e},
> + {0x54036, 0x12},
> {0x54037, 0x400},
> {0x54038, 0xe400},
> - {0x54039, 0xf236},
> - {0x5403a, 0x4600},
> - {0x5403b, 0x811},
> - {0x5403c, 0x11},
> + {0x54039, 0x2236},
> + {0x5403a, 0x4400},
> + {0x5403b, 0x81e},
> + {0x5403c, 0x12},
> {0x5403d, 0x400},
> {0xd0000, 0x1}
> };
> @@ -1451,10 +1871,18 @@ static struct dram_cfg_param ddr_phy_pie[] =
> {
> {0x400d7, 0x20b},
> {0x2003a, 0x2},
> {0x200be, 0x3},
> - {0x2000b, 0x75},
> + {0x2000b, 0x41a},
> {0x2000c, 0xe9},
> {0x2000d, 0x91c},
> {0x2000e, 0x2c},
> + {0x12000b, 0x20d},
> + {0x12000c, 0x74},
> + {0x12000d, 0x48e},
> + {0x12000e, 0x2c},
> + {0x22000b, 0xb0},
> + {0x22000c, 0x27},
> + {0x22000d, 0x186},
> + {0x22000e, 0x10},
> {0x9000c, 0x0},
> {0x9000d, 0x173},
> {0x9000e, 0x60},
> @@ -1465,12 +1893,26 @@ static struct dram_cfg_param ddr_phy_pie[] =
> {
> {0x90013, 0x6152},
> {0x20010, 0x5a},
> {0x20011, 0x3},
> + {0x120010, 0x5a},
> + {0x120011, 0x3},
> {0x40080, 0xe0},
> {0x40081, 0x12},
> {0x40082, 0xe0},
> {0x40083, 0x12},
> {0x40084, 0xe0},
> {0x40085, 0x12},
> + {0x140080, 0xe0},
> + {0x140081, 0x12},
> + {0x140082, 0xe0},
> + {0x140083, 0x12},
> + {0x140084, 0xe0},
> + {0x140085, 0x12},
> + {0x240080, 0xe0},
> + {0x240081, 0x12},
> + {0x240082, 0xe0},
> + {0x240083, 0x12},
> + {0x240084, 0xe0},
> + {0x240085, 0x12},
> {0x400fd, 0xf},
> {0x400f1, 0xe},
> {0x10011, 0x1},
> @@ -1505,7 +1947,6 @@ static struct dram_cfg_param ddr_phy_pie[] = {
> {0x20088, 0x19},
> {0xc0080, 0x0},
> {0xd0000, 0x1},
> -
> };
>
> static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> @@ -1515,9 +1956,21 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[]
> = {
> .fw_type = FW_1D_IMAGE,
> .fsp_cfg = ddr_fsp0_cfg,
> .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> -
> },
> -
> + {
> + /* P1 1866mts 1D */
> + .drate = 1866,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp1_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
> + },
> + {
> + /* P2 625mts 1D */
> + .drate = 625,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp2_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
> + },
> {
> /* P0 3733mts 2D */
> .drate = 3733,
> @@ -1525,7 +1978,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] =
> {
> .fsp_cfg = ddr_fsp0_2d_cfg,
> .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> },
> -
> };
>
> /* ddr timing config params */
> @@ -1540,7 +1992,227 @@ struct dram_timing_info dram_timing = {
> .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
> .ddrphy_pie = ddr_phy_pie,
> .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> - .fsp_table = { 3733, },
> + .fsp_table = { 3733, 1866, 625, },
> .fsp_cfg = ddr_dram_fsp_cfg,
> .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
> };
> +
> +void set_dram_timings_2gb_lpddr4x(void)
> +{
> + /* Initialize DDRC registers */
> + dram_timing.ddrc_cfg[1].val = 0x8000ff;
> + dram_timing.ddrc_cfg[3].val = 0x80000512;
> +
> + /* dram fsp cfg */
> + dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x24AB321B;
> + dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x2F2EE233;
> + dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x015B015B;
> + dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x015B2213;
> + dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
> + dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x13;
> +
> + dram_timing.fsp_cfg[1].ddrc_cfg[0].val = 0x12552100;
> + dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x1816B4AA;
> + dram_timing.fsp_cfg[1].ddrc_cfg[9].val = 0x00AA00AA;
> + dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
> + dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x13;
> +
> + dram_timing.fsp_cfg[2].ddrc_cfg[0].val = 0x00061000;
> + dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E62FA48;
> + dram_timing.fsp_cfg[2].ddrc_cfg[9].val = 0x00340034;
> + dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
> + dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x13;
> +
> + /* P0 message block parameter for training firmware */
> + dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
> + dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1308;
> + dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
> + dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1308;
> + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
> + dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x13;
> + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
> + dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x13;
> +
> + /* P1 message block parameter for training firmware */
> + dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
> + dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1308;
> + dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
> + dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1308;
> + dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
> + dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x13;
> + dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
> + dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x13;
> +
> + /* P2 message block parameter for training firmware */
> + dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
> + dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1300;
> + dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
> + dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1300;
> + dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
> + dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x13;
> + dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
> + dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x13;
> +
> + /* P0 2D message block parameter for training firmware */
> + dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
> + dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1308;
> + dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
> + dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1308;
> + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
> + dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x13;
> + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
> + dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x13;
> +}
> +
> +/* Generated with DDR Tool v3.3.0_7.8-d1cdb7d3 */
> +void set_dram_timings_1gb_lpddr4x_900mhz(void)
> +{
> + /* Initialize DDRC registers */
> + dram_timing.ddrc_cfg[6].val = 0x4080;
> +
> + /* dram fsp cfg */
> + dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x124F2100;
> + dram_timing.fsp_cfg[0].ddrc_cfg[1].val = 0xF877000E;
> + dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x181AE4AA;
> + dram_timing.fsp_cfg[0].ddrc_cfg[3].val = 0x005101E6;
> + dram_timing.fsp_cfg[0].ddrc_cfg[4].val = 0x0E3C0000;
> + dram_timing.fsp_cfg[0].ddrc_cfg[5].val = 0x00009101;
> + dram_timing.fsp_cfg[0].ddrc_cfg[6].val = 0x30900000;
> + dram_timing.fsp_cfg[0].ddrc_cfg[7].val = 0x8A0A0508;
> + dram_timing.fsp_cfg[0].ddrc_cfg[8].val = 0x00000014;
> + dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x007B007B;
> + dram_timing.fsp_cfg[0].ddrc_cfg[12].val = 0x1128110B;
> + dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x007B140A;
> + dram_timing.fsp_cfg[0].ddrc_cfg[14].val = 0x0620071E;
> + dram_timing.fsp_cfg[0].mr_cfg[0].val = 0xB4;
> + dram_timing.fsp_cfg[0].mr_cfg[1].val = 0x1B;
> + dram_timing.fsp_cfg[0].mr_cfg[2].val = 0xE2;
> + dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
> + dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x15;
> +
> + dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x181AE4AA;
> + dram_timing.fsp_cfg[1].mr_cfg[2].val = 0xE2;
> + dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
> + dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x15;
> +
> + dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E660A48;
> + dram_timing.fsp_cfg[2].mr_cfg[2].val = 0xE2;
> + dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
> + dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x15;
> +
> + /* PHY Initialize Configuration */
> + dram_timing.ddrphy_cfg[31].val = 0xb;
> + dram_timing.ddrphy_cfg[86].val = 0x1d3;
> + dram_timing.ddrphy_cfg[90].val = 0x10c;
> + dram_timing.ddrphy_cfg[95].val = 0x10c;
> + dram_timing.ddrphy_cfg[100].val = 0x10c;
> + dram_timing.ddrphy_cfg[122].val = 0x1;
> + /**
> + * NOTE:
> + * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array
> members 119
> + * (reg=0x1004a, val=0x500) and 120 (reg=0x1104a, val=0x500)
> are not
> + * present in the ddr_ddrphy_cfg array. However they were
> present in array
> + * generated with previous DDR Tool v3.1.0_7.4. We simply set
> both values
> + * to default value of 0x400 (read with dwc_ddrphy_apb_rd())
> here to avoid
> + * any negative side-effects.
> + */
> + dram_timing.ddrphy_cfg[119].val = 0x400;
> + dram_timing.ddrphy_cfg[120].val = 0x400;
> +
> + /**
> + * NOTE:
> + * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array
> members 101
> + * (reg=0x1004a, val=0x0) and 120 (reg=0x1104a, val=0x0) are
> not present
> + * in the ddr_ddrphy_trained_csr array. However they were
> present in array
> + * generated with previous DDR Tool v3.1.0_7.4. We simply set
> both values
> + * to default 0x0 (like all other ddrphy_trained_csr values)
> here to avoid
> + * any negative side-effects.
> + */
> + /* PHY trained csr */
> + dram_timing.ddrphy_trained_csr[101].val = 0x0;
> + dram_timing.ddrphy_trained_csr[102].val = 0x0;
> +
> + /* P0 message block parameter for training firmware */
> + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0x74a;
> + dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x15;
> + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x1bb4;
> + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xe2;
> + dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
> + dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1508;
> + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x1bb4;
> + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xe2;
> + dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
> + dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1508;
> + dram_timing.fsp_msg[0].fsp_cfg[20].val = 0xb400;
> + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0xe21b;
> + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
> + dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x15;
> + dram_timing.fsp_msg[0].fsp_cfg[26].val = 0xb400;
> + dram_timing.fsp_msg[0].fsp_cfg[27].val = 0xe21b;
> + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
> + dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x15;
> +
> + /* P1 message block parameter for training firmware */
> + dram_timing.fsp_msg[1].fsp_cfg[4].val = 0x15;
> + dram_timing.fsp_msg[1].fsp_cfg[12].val = 0xe2;
> + dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
> + dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1508;
> + dram_timing.fsp_msg[1].fsp_cfg[17].val = 0xe2;
> + dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
> + dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1508;
> + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0xe21b;
> + dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
> + dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x15;
> + dram_timing.fsp_msg[1].fsp_cfg[28].val = 0xe21b;
> + dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
> + dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x15;
> +
> + /* P2 message block parameter for training firmware */
> + dram_timing.fsp_msg[2].fsp_cfg[4].val = 0x15;
> + dram_timing.fsp_msg[2].fsp_cfg[12].val = 0xe2;
> + dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
> + dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1500;
> + dram_timing.fsp_msg[2].fsp_cfg[17].val = 0xe2;
> + dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
> + dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1500;
> + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0xe209;
> + dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
> + dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x15;
> + dram_timing.fsp_msg[2].fsp_cfg[28].val = 0xe209;
> + dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
> + dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x15;
> +
> + /* P0 2D message block parameter for training firmware */
> + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0x74a;
> + dram_timing.fsp_msg[3].fsp_cfg[3].val = 0x15;
> + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x1bb4;
> + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xe2;
> + dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
> + dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1508;
> + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x1bb4;
> + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xe2;
> + dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
> + dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1508;
> + dram_timing.fsp_msg[3].fsp_cfg[21].val = 0xb400;
> + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0xe21b;
> + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
> + dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x15;
> + dram_timing.fsp_msg[3].fsp_cfg[27].val = 0xb400;
> + dram_timing.fsp_msg[3].fsp_cfg[28].val = 0xe21b;
> + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
> + dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x15;
> +
> + /* DRAM PHY init engine image */
> + dram_timing.ddrphy_pie[483].val = 0x20d;
> + dram_timing.ddrphy_pie[484].val = 0x74;
> + dram_timing.ddrphy_pie[485].val = 0x48e;
> +
> + /* P0 3733mts 1D */
> + dram_timing.fsp_msg[0].drate = 1866;
> +
> + /* P0 1866mts 2D */
> + dram_timing.fsp_msg[3].drate = 1866;
> +
> + /* ddr timing config params */
> + dram_timing.fsp_table[0] = 1866;
> +}
--
PHYTEC Messtechnik GmbH | Barcelona-Allee 1 | 55129 Mainz, Germany
Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber,
Dipl.-Ing. (FH) Markus Lickes | Handelsregister Mainz HRB 4656 |
Finanzamt Mainz | St.Nr. 26/665/00608, DE 149059855
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings
2024-11-04 10:41 ` [PATCH 1/3] board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings Christoph Stoidner
2024-11-04 12:16 ` [Upstream] " Teresa Remmet
@ 2024-11-04 12:30 ` Fabio Estevam
2024-11-05 13:56 ` Christoph Stoidner
1 sibling, 1 reply; 9+ messages in thread
From: Fabio Estevam @ 2024-11-04 12:30 UTC (permalink / raw)
To: Christoph Stoidner; +Cc: u-boot, upstream, Mathieu Othacehe
Hi Christoph,
On Mon, Nov 4, 2024 at 7:52 AM Christoph Stoidner <c.stoidner@phytec.de> wrote:
>
> The phyCORE-i.MX 93 is available with a 1GB ram chip or a 2GB ram chip.
> Add the ram timings for the 2GB chip, in form of a diff compared
> to the existing LPDDR4X 1GB timings. With that, the SPL can select the
> appropriate timings at startup.
>
> Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
> Cc: Mathieu Othacehe <m.othacehe@gmail.com>, Christoph Stoidner <c.stoidner@phytec.de>, Tom Rini <trini@konsulko.com>, Yannic Moog <y.moog@phytec.de>, Primoz Fiser <primoz.fiser@norik.com>, Andrej Picej <andrej.picej@norik.com>, Wadim Egorov <w.egorov@phytec.de>
As Teresa pointed out, the correct way to add Cc is as follows:
Cc: Mathieu Othacehe <m.othacehe@gmail.com>
Cc: Christoph Stoidner <c.stoidner@phytec.de>
... etc
You can even put the Cc list below the --- line so it does not appear
in the commit log.
Please run checkpatch on all the patches too. There is a warning on
this one that is easy to fix:
./scripts/checkpatch.pl
~/Downloads/1-3-board-phytec-phycore-imx93-Add-2GB-LPDDR4X-RAM-timings.patch
CHECK: Please don't use multiple blank lines
#879: FILE: board/phytec/phycore_imx93/lpddr4_timing.c:1350:
+
total: 0 errors, 0 warnings, 1 checks, 1051 lines checked
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Upstream] [PATCH 2/3] board: phytec: imx93: Add eeprom-based hardware introspection
2024-11-04 10:41 ` [PATCH 2/3] board: phytec: imx93: Add eeprom-based hardware introspection Christoph Stoidner
@ 2024-11-04 13:53 ` Wadim Egorov
2024-11-05 13:30 ` Christoph Stoidner
0 siblings, 1 reply; 9+ messages in thread
From: Wadim Egorov @ 2024-11-04 13:53 UTC (permalink / raw)
To: Christoph Stoidner, u-boot, upstream; +Cc: Mathieu Othacehe
Hi Christoph,
Am 04.11.24 um 11:41 schrieb Christoph Stoidner:
> The phyCORE-i.MX 93 is available in various variants. Relevant variant
> options for the spl/u-boot are:
> - with or without HS400 support for the eMMC
> - with 1GB ram chip, or 2GB ram chip
>
> The phyCORE's eeprom contains all information about the existing variant
> options. Add evaluation of the eeprom data to the spl/u-boot to
> enable/disable HS400 and to select the appropriate ram configuration at
> startup.
>
> Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
<snip>
> --- a/board/phytec/phycore_imx93/phycore-imx93.c
> +++ b/board/phytec/phycore_imx93/phycore-imx93.c
> @@ -3,6 +3,7 @@
> * Copyright (C) 2023 PHYTEC Messtechnik GmbH
> * Author: Christoph Stoidner <c.stoidner@phytec.de>
> * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
> + * Copyright (C) 2024 PHYTEC Messtechnik GmbH
> */
>
> #include <asm/arch-imx9/ccm_regs.h>
> @@ -12,11 +13,21 @@
> #include <asm/global_data.h>
> #include <asm/mach-imx/boot_mode.h>
> #include <env.h>
> +#include <fdt_support.h>
> +
> +#include "../common/imx93_som_detection.h"
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +#define EEPROM_ADDR 0x50
> +
> int board_init(void)
> {
> + int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
> +
> + if (ret)
> + printf("%s: EEPROM data init failed\n", __func__);
> +
> return 0;
> }
>
> @@ -40,3 +51,44 @@ int board_late_init(void)
>
> return 0;
> }
> +
> +static void emmc_fixup(void *blob, struct phytec_eeprom_data *data)
> +{
> + u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT);
I am thinking about future SoMs using similar variants.
> + int offset;
> +
> + if (option == PHYTEC_EEPROM_INVAL)
> + goto err;
> +
> + /* Check "IO Voltage 1v8" flag is set */
> + if (option & 0x01) {
If you abstract away the option details into an own function, e.g.
phytec_get_imx93_io_volt(), you could reduce the amount of code in your
board files. Also, if SoMs change the option layouts for a specific
detail (for whatever reason), you would have an abstraction layer to
details with it.
> + offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc",
> + 0x42850000);
> + if (offset)
> + fdt_delprop(blob, offset, "no-1-8-v");
> + else
> + goto err;
> + }
> +
> + return;
> +err:
> + printf("Could not detect eMMC VDD-IO. Fall back to default.\n");
> +}
> +
> +int board_fix_fdt(void *blob)
> +{
> + struct phytec_eeprom_data data;
> +
> + phytec_eeprom_data_setup(&data, 2, EEPROM_ADDR);
> +
> + emmc_fixup(blob, &data);
> +
> + return 0;
> +}
> +
> +int ft_board_setup(void *blob, struct bd_info *bd)
> +{
> + emmc_fixup(blob, NULL);
> +
> + return 0;
> +}
> diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
> index 17a8736c73..cf9c94eb45 100644
> --- a/board/phytec/phycore_imx93/spl.c
> +++ b/board/phytec/phycore_imx93/spl.c
> @@ -3,6 +3,7 @@
> * Copyright (C) 2023 PHYTEC Messtechnik GmbH
> * Author: Christoph Stoidner <c.stoidner@phytec.de>
> * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
> + * Copyright (C) 2024 PHYTEC Messtechnik GmbH
> */
>
> #include <asm/arch/clock.h>
> @@ -20,6 +21,8 @@
> #include <power/pca9450.h>
> #include <spl.h>
>
> +#include "../common/imx93_som_detection.h"
> +
> DECLARE_GLOBAL_DATA_PTR;
>
> /*
> @@ -27,6 +30,13 @@ DECLARE_GLOBAL_DATA_PTR;
> * when pca9451a support is added.
> */
> #define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5)
> +#define EEPROM_ADDR 0x50
> +
> +/*
> + * Prototypes of automatically generated ram config file
> + */
> +void set_dram_timings_2gb_lpddr4x(void);
> +void set_dram_timings_1gb_lpddr4x_900mhz(void);
>
> int spl_board_boot_device(enum boot_device boot_dev_spl)
> {
> @@ -44,8 +54,56 @@ void spl_board_init(void)
> puts("Normal Boot\n");
> }
>
> +enum phytec_imx93_ddr_eeprom_code {
> + INVALID = PHYTEC_EEPROM_INVAL,
> + PHYTEC_IMX93_LPDDR4X_512MB = 0,
> + PHYTEC_IMX93_LPDDR4X_1GB = 1,
> + PHYTEC_IMX93_LPDDR4X_2GB = 2,
> + PHYTEC_IMX93_LPDDR4_512MB = 3,
> + PHYTEC_IMX93_LPDDR4_1GB = 4,
> + PHYTEC_IMX93_LPDDR4_2GB = 5,
> +};
^ IMO this belongs into imx93_som_detection.h file
Regards,
Wadim
> +
> void spl_dram_init(void)
> {
> + int ret;
> + enum phytec_imx93_ddr_eeprom_code ddr_opt = INVALID;
> +
> + /* NOTE: In SPL lpi2c3 is mapped to bus 0 */
> + ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
> + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
> + goto out;
> +
> + ret = phytec_imx93_detect(NULL);
> + if (!ret)
> + phytec_print_som_info(NULL);
> +
> + if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) {
> + if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB))
> + ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB;
> + else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB))
> + ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB;
> + } else {
> + ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR);
> + }
> +
> + switch (ddr_opt) {
> + case PHYTEC_IMX93_LPDDR4X_1GB:
> + if (is_voltage_mode(VOLT_LOW_DRIVE))
> + set_dram_timings_1gb_lpddr4x_900mhz();
> + break;
> + case PHYTEC_IMX93_LPDDR4X_2GB:
> + set_dram_timings_2gb_lpddr4x();
> + break;
> + default:
> + goto out;
> + }
> + ddr_init(&dram_timing);
> + return;
> +out:
> + puts("Could not detect correct RAM type and size. Fall back to default.\n");
> + if (is_voltage_mode(VOLT_LOW_DRIVE))
> + set_dram_timings_1gb_lpddr4x_900mhz();
> ddr_init(&dram_timing);
> }
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Upstream] [PATCH 2/3] board: phytec: imx93: Add eeprom-based hardware introspection
2024-11-04 13:53 ` [Upstream] " Wadim Egorov
@ 2024-11-05 13:30 ` Christoph Stoidner
0 siblings, 0 replies; 9+ messages in thread
From: Christoph Stoidner @ 2024-11-05 13:30 UTC (permalink / raw)
To: PHYTEC Upstream, Wadim Egorov, u-boot@lists.denx.de; +Cc: m.othacehe@gmail.com
Hi Wadmin,
On Mo, 2024-11-04 at 14:53 +0100, Wadim Egorov wrote:
> Hi Christoph,
>
> Am 04.11.24 um 11:41 schrieb Christoph Stoidner:
> > The phyCORE-i.MX 93 is available in various variants. Relevant
> > variant
> > options for the spl/u-boot are:
> > - with or without HS400 support for the eMMC
> > - with 1GB ram chip, or 2GB ram chip
> >
> > The phyCORE's eeprom contains all information about the existing
> > variant
> > options. Add evaluation of the eeprom data to the spl/u-boot to
> > enable/disable HS400 and to select the appropriate ram
> > configuration at
> > startup.
> >
> > Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
>
> <snip>
>
> > --- a/board/phytec/phycore_imx93/phycore-imx93.c
> > +++ b/board/phytec/phycore_imx93/phycore-imx93.c
> > @@ -3,6 +3,7 @@
> > * Copyright (C) 2023 PHYTEC Messtechnik GmbH
> > * Author: Christoph Stoidner <c.stoidner@phytec.de>
> > * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
> > + * Copyright (C) 2024 PHYTEC Messtechnik GmbH
> > */
> >
> > #include <asm/arch-imx9/ccm_regs.h>
> > @@ -12,11 +13,21 @@
> > #include <asm/global_data.h>
> > #include <asm/mach-imx/boot_mode.h>
> > #include <env.h>
> > +#include <fdt_support.h>
> > +
> > +#include "../common/imx93_som_detection.h"
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +#define EEPROM_ADDR 0x50
> > +
> > int board_init(void)
> > {
> > + int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
> > +
> > + if (ret)
> > + printf("%s: EEPROM data init failed\n", __func__);
> > +
> > return 0;
> > }
> >
> > @@ -40,3 +51,44 @@ int board_late_init(void)
> >
> > return 0;
> > }
> > +
> > +static void emmc_fixup(void *blob, struct phytec_eeprom_data
> > *data)
> > +{
> > + u8 option = phytec_imx93_get_opt(data,
> > PHYTEC_IMX93_OPT_FEAT);
>
> I am thinking about future SoMs using similar variants.
>
>
>
> > + int offset;
> > +
> > + if (option == PHYTEC_EEPROM_INVAL)
> > + goto err;
> > +
> > + /* Check "IO Voltage 1v8" flag is set */
> > + if (option & 0x01) {
> If you abstract away the option details into an own function, e.g.
> phytec_get_imx93_io_volt(), you could reduce the amount of code in
> your
> board files. Also, if SoMs change the option layouts for a specific
> detail (for whatever reason), you would have an abstraction layer to
> details with it.
>
Yes, that might make sense. I will send a v2 for it.
> > + offset = fdt_node_offset_by_compat_reg(blob,
> > "fsl,imx93-usdhc",
> > + 0x42850000);
> > + if (offset)
> > + fdt_delprop(blob, offset, "no-1-8-v");
> > + else
> > + goto err;
> > + }
> > +
> > + return;
> > +err:
> > + printf("Could not detect eMMC VDD-IO. Fall back to
> > default.\n");
> > +}
> > +
> > +int board_fix_fdt(void *blob)
> > +{
> > + struct phytec_eeprom_data data;
> > +
> > + phytec_eeprom_data_setup(&data, 2, EEPROM_ADDR);
> > +
> > + emmc_fixup(blob, &data);
> > +
> > + return 0;
> > +}
> > +
> > +int ft_board_setup(void *blob, struct bd_info *bd)
> > +{
> > + emmc_fixup(blob, NULL);
> > +
> > + return 0;
> > +}
> > diff --git a/board/phytec/phycore_imx93/spl.c
> > b/board/phytec/phycore_imx93/spl.c
> > index 17a8736c73..cf9c94eb45 100644
> > --- a/board/phytec/phycore_imx93/spl.c
> > +++ b/board/phytec/phycore_imx93/spl.c
> > @@ -3,6 +3,7 @@
> > * Copyright (C) 2023 PHYTEC Messtechnik GmbH
> > * Author: Christoph Stoidner <c.stoidner@phytec.de>
> > * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
> > + * Copyright (C) 2024 PHYTEC Messtechnik GmbH
> > */
> >
> > #include <asm/arch/clock.h>
> > @@ -20,6 +21,8 @@
> > #include <power/pca9450.h>
> > #include <spl.h>
> >
> > +#include "../common/imx93_som_detection.h"
> > +
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > /*
> > @@ -27,6 +30,13 @@ DECLARE_GLOBAL_DATA_PTR;
> > * when pca9451a support is added.
> > */
> > #define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5)
> > +#define EEPROM_ADDR 0x50
> > +
> > +/*
> > + * Prototypes of automatically generated ram config file
> > + */
> > +void set_dram_timings_2gb_lpddr4x(void);
> > +void set_dram_timings_1gb_lpddr4x_900mhz(void);
> >
> > int spl_board_boot_device(enum boot_device boot_dev_spl)
> > {
> > @@ -44,8 +54,56 @@ void spl_board_init(void)
> > puts("Normal Boot\n");
> > }
> >
> > +enum phytec_imx93_ddr_eeprom_code {
> > + INVALID = PHYTEC_EEPROM_INVAL,
> > + PHYTEC_IMX93_LPDDR4X_512MB = 0,
> > + PHYTEC_IMX93_LPDDR4X_1GB = 1,
> > + PHYTEC_IMX93_LPDDR4X_2GB = 2,
> > + PHYTEC_IMX93_LPDDR4_512MB = 3,
> > + PHYTEC_IMX93_LPDDR4_1GB = 4,
> > + PHYTEC_IMX93_LPDDR4_2GB = 5,
> > +};
> ^ IMO this belongs into imx93_som_detection.h file
That enum is in spl.c, because there is nothing like
phytec_get_imx93_ram_type(), but we use the generic
phytec_imx93_get_opt() instead. So that is very similar to your comment
about phytec_get_imx93_io_volt() above.
I will add a phytec_get_imx93_ram_type() to imx93_som_detection.c
and also move thereby enum phytec_imx93_ddr_eeprom_code to
imx93_som_detection.h .
Thanks,
Christoph
>
> Regards,
> Wadim
> > +
> > void spl_dram_init(void)
> > {
> > + int ret;
> > + enum phytec_imx93_ddr_eeprom_code ddr_opt = INVALID;
> > +
> > + /* NOTE: In SPL lpi2c3 is mapped to bus 0 */
> > + ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
> > + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
> > + goto out;
> > +
> > + ret = phytec_imx93_detect(NULL);
> > + if (!ret)
> > + phytec_print_som_info(NULL);
> > +
> > + if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) {
> > + if
> > (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB))
> > + ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB;
> > + else if
> > (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB))
> > + ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB;
> > + } else {
> > + ddr_opt = phytec_imx93_get_opt(NULL,
> > PHYTEC_IMX93_OPT_DDR);
> > + }
> > +
> > + switch (ddr_opt) {
> > + case PHYTEC_IMX93_LPDDR4X_1GB:
> > + if (is_voltage_mode(VOLT_LOW_DRIVE))
> > + set_dram_timings_1gb_lpddr4x_900mhz();
> > + break;
> > + case PHYTEC_IMX93_LPDDR4X_2GB:
> > + set_dram_timings_2gb_lpddr4x();
> > + break;
> > + default:
> > + goto out;
> > + }
> > + ddr_init(&dram_timing);
> > + return;
> > +out:
> > + puts("Could not detect correct RAM type and size. Fall back
> > to default.\n");
> > + if (is_voltage_mode(VOLT_LOW_DRIVE))
> > + set_dram_timings_1gb_lpddr4x_900mhz();
> > ddr_init(&dram_timing);
> > }
> >
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Upstream] [PATCH 1/3] board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings
2024-11-04 12:16 ` [Upstream] " Teresa Remmet
@ 2024-11-05 13:47 ` Christoph Stoidner
0 siblings, 0 replies; 9+ messages in thread
From: Christoph Stoidner @ 2024-11-05 13:47 UTC (permalink / raw)
To: PHYTEC Upstream, u-boot@lists.denx.de, Teresa Remmet; +Cc: m.othacehe@gmail.com
Hi Teresa,
On Mo, 2024-11-04 at 13:16 +0100, Teresa Remmet wrote:
> Hello Christoph,
>
> Am Montag, dem 04.11.2024 um 11:41 +0100 schrieb Christoph Stoidner:
> > The phyCORE-i.MX 93 is available with a 1GB ram chip or a 2GB ram
> > chip.
> > Add the ram timings for the 2GB chip, in form of a diff compared
> > to the existing LPDDR4X 1GB timings. With that, the SPL can select
> > the
> > appropriate timings at startup.
>
> it looks like you also updated the existing 1GB RAM timings with a
> new version of the DDR Tool. You should reflect this in the commit
> message, too.
True. I will send a v2 for that.
>
> >
> > Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
> > Cc: Mathieu Othacehe <m.othacehe@gmail.com>, Christoph Stoidner
> > <c.stoidner@phytec.de>, Tom Rini <trini@konsulko.com>, Yannic Moog
> > <y.moog@phytec.de>, Primoz Fiser <primoz.fiser@norik.com>, Andrej
> > Picej <andrej.picej@norik.com>, Wadim Egorov <w.egorov@phytec.de>
>
> You added here quite a lot of people which are actually not in CC of
> this patch. You should check that.
> And each entry should be in a separate line.
Thanks for the hint. I will consider it for all my next patches.
Christoph
>
> Teresa
>
> > ---
> > board/phytec/phycore_imx93/lpddr4_timing.c | 794
> > +++++++++++++++++++--
> > 1 file changed, 733 insertions(+), 61 deletions(-)
> >
> > diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c
> > b/board/phytec/phycore_imx93/lpddr4_timing.c
> > index 2111972a40..b7132ffade 100644
> > --- a/board/phytec/phycore_imx93/lpddr4_timing.c
> > +++ b/board/phytec/phycore_imx93/lpddr4_timing.c
> > @@ -1,24 +1,24 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> > - * Copyright 2023 NXP
> > - * Copyright (C) 2023 PHYTEC Messtechnik GmbH
> > + * Copyright 2024 NXP
> > + * Copyright (C) 2024 PHYTEC Messtechnik GmbH
> > * Christoph Stoidner <c.stoidner@phytec.de>
> > *
> > - * Code generated with DDR Tool v1.0.0.
> > + * Code generated with DDR Tool v3.1.0_7.4.
> > */
> >
> > #include <linux/kernel.h>
> > #include <asm/arch/ddr.h>
> >
> > +/* Initialize DDRC registers */
> > static struct dram_cfg_param ddr_ddrc_cfg[] = {
> > - /** Initialize DDRC registers **/
> > {0x4e300110, 0x44100001},
> > {0x4e300000, 0x8000bf},
> > {0x4e300008, 0x0},
> > {0x4e300080, 0x80000412},
> > {0x4e300084, 0x0},
> > {0x4e300114, 0x1002},
> > - {0x4e300260, 0x4080},
> > + {0x4e300260, 0x80},
> > {0x4e300f04, 0x80},
> > {0x4e300800, 0x43b30002},
> > {0x4e300804, 0x1f1f1f1f},
> > @@ -31,18 +31,17 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
> > {0x4e301254, 0x0},
> > {0x4e301258, 0x0},
> > {0x4e30125c, 0x0},
> > -
> > };
> >
> > /* dram fsp cfg */
> > static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
> > {
> > {
> > - {0x4e300100, 0x24A0421B},
> > + {0x4e300100, 0x24A0321B},
> > {0x4e300104, 0xF8EE001B},
> > - {0x4e300108, 0x2F263233},
> > - {0x4e30010C, 0x0005E18B},
> > - {0x4e300124, 0x1C770000},
> > + {0x4e300108, 0x2F2E3233},
> > + {0x4e30010C, 0x0005C18B},
> > + {0x4e300124, 0x1C790000},
> > {0x4e300160, 0x00009102},
> > {0x4e30016C, 0x35F00000},
> > {0x4e300170, 0x8B0B0608},
> > @@ -50,21 +49,73 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] =
> > {
> > {0x4e300254, 0x00FE00FE},
> > {0x4e300258, 0x00000008},
> > {0x4e30025C, 0x00000400},
> > - {0x4e300300, 0x224F2215},
> > + {0x4e300300, 0x224F2213},
> > {0x4e300304, 0x00FE2213},
> > - {0x4e300308, 0x0A3C0E3C},
> > + {0x4e300308, 0x0A380E3D},
> > },
> > {
> > {0x01, 0xE4},
> > {0x02, 0x36},
> > - {0x03, 0xF2},
> > - {0x0b, 0x46},
> > - {0x0c, 0x11},
> > - {0x0e, 0x11},
> > + {0x03, 0x22},
> > + {0x0b, 0x44},
> > + {0x0c, 0x1E},
> > + {0x0e, 0x12},
> > + {0x16, 0x04},
> > + },
> > + 0,
> > + },
> > + {
> > + {
> > + {0x4e300100, 0x124F2100},
> > + {0x4e300104, 0xF877000E},
> > + {0x4e300108, 0x1816E4AA},
> > + {0x4e30010C, 0x005101E6},
> > + {0x4e300124, 0x0E3C0000},
> > + {0x4e300160, 0x00009101},
> > + {0x4e30016C, 0x30900000},
> > + {0x4e300170, 0x8A0A0508},
> > + {0x4e300250, 0x00000014},
> > + {0x4e300254, 0x007B007B},
> > + {0x4e300258, 0x00000008},
> > + {0x4e30025C, 0x00000400},
> > + },
> > + {
> > + {0x01, 0xB4},
> > + {0x02, 0x1B},
> > + {0x03, 0x22},
> > + {0x0b, 0x44},
> > + {0x0c, 0x1E},
> > + {0x0e, 0x12},
> > {0x16, 0x04},
> > },
> > 0,
> > },
> > + {
> > + {
> > + {0x4e300100, 0x00051000},
> > + {0x4e300104, 0xF855000A},
> > + {0x4e300108, 0x6E620A48},
> > + {0x4e30010C, 0x0031010D},
> > + {0x4e300124, 0x04C50000},
> > + {0x4e300160, 0x00009100},
> > + {0x4e30016C, 0x30000000},
> > + {0x4e300170, 0x89090408},
> > + {0x4e300250, 0x00000007},
> > + {0x4e300254, 0x00240024},
> > + {0x4e300258, 0x00000008},
> > + {0x4e30025C, 0x00000400},
> > + },
> > + {
> > + {0x01, 0x94},
> > + {0x02, 0x9},
> > + {0x03, 0x22},
> > + {0x0b, 0x44},
> > + {0x0c, 0x1E},
> > + {0x0e, 0x12},
> > + {0x16, 0x04},
> > + },
> > + 1,
> > + },
> >
> > };
> >
> > @@ -90,25 +141,65 @@ static struct dram_cfg_param ddr_ddrphy_cfg[]
> > =
> > {
> > {0x1015f, 0x5ff},
> > {0x1105f, 0x5ff},
> > {0x1115f, 0x5ff},
> > + {0x11005f, 0x5ff},
> > + {0x11015f, 0x5ff},
> > + {0x11105f, 0x5ff},
> > + {0x11115f, 0x5ff},
> > + {0x21005f, 0x5ff},
> > + {0x21015f, 0x5ff},
> > + {0x21105f, 0x5ff},
> > + {0x21115f, 0x5ff},
> > {0x55, 0x1ff},
> > {0x1055, 0x1ff},
> > {0x2055, 0x1ff},
> > {0x200c5, 0x19},
> > + {0x1200c5, 0xb},
> > + {0x2200c5, 0x7},
> > {0x2002e, 0x2},
> > + {0x12002e, 0x2},
> > + {0x22002e, 0x2},
> > {0x90204, 0x0},
> > + {0x190204, 0x0},
> > + {0x290204, 0x0},
> > {0x20024, 0x1e3},
> > {0x2003a, 0x2},
> > {0x2007d, 0x212},
> > {0x2007c, 0x61},
> > + {0x120024, 0x1e3},
> > + {0x2003a, 0x2},
> > + {0x12007d, 0x212},
> > + {0x12007c, 0x61},
> > + {0x220024, 0x1e3},
> > + {0x2003a, 0x2},
> > + {0x22007d, 0x212},
> > + {0x22007c, 0x61},
> > {0x20056, 0x3},
> > + {0x120056, 0x3},
> > + {0x220056, 0x3},
> > {0x1004d, 0x600},
> > {0x1014d, 0x600},
> > {0x1104d, 0x600},
> > {0x1114d, 0x600},
> > - {0x10049, 0xe00},
> > - {0x10149, 0xe00},
> > - {0x11049, 0xe00},
> > - {0x11149, 0xe00},
> > + {0x11004d, 0x600},
> > + {0x11014d, 0x600},
> > + {0x11104d, 0x600},
> > + {0x11114d, 0x600},
> > + {0x21004d, 0x600},
> > + {0x21014d, 0x600},
> > + {0x21104d, 0x600},
> > + {0x21114d, 0x600},
> > + {0x10049, 0x604},
> > + {0x10149, 0x604},
> > + {0x11049, 0x604},
> > + {0x11149, 0x604},
> > + {0x110049, 0x604},
> > + {0x110149, 0x604},
> > + {0x111049, 0x604},
> > + {0x111149, 0x604},
> > + {0x210049, 0x604},
> > + {0x210149, 0x604},
> > + {0x211049, 0x604},
> > + {0x211149, 0x604},
> > {0x43, 0x60},
> > {0x1043, 0x60},
> > {0x2043, 0x60},
> > @@ -117,14 +208,30 @@ static struct dram_cfg_param ddr_ddrphy_cfg[]
> > =
> > {
> > {0x20050, 0x0},
> > {0x2009b, 0x2},
> > {0x20008, 0x3a5},
> > + {0x120008, 0x1d3},
> > + {0x220008, 0x9c},
> > {0x20088, 0x9},
> > - {0x200b2, 0x10c},
> > + {0x200b2, 0x104},
> > {0x10043, 0x5a1},
> > {0x10143, 0x5a1},
> > {0x11043, 0x5a1},
> > {0x11143, 0x5a1},
> > + {0x1200b2, 0x104},
> > + {0x110043, 0x5a1},
> > + {0x110143, 0x5a1},
> > + {0x111043, 0x5a1},
> > + {0x111143, 0x5a1},
> > + {0x2200b2, 0x104},
> > + {0x210043, 0x5a1},
> > + {0x210143, 0x5a1},
> > + {0x211043, 0x5a1},
> > + {0x211143, 0x5a1},
> > {0x200fa, 0x2},
> > + {0x1200fa, 0x2},
> > + {0x2200fa, 0x2},
> > {0x20019, 0x1},
> > + {0x120019, 0x1},
> > + {0x220019, 0x1},
> > {0x200f0, 0x600},
> > {0x200f1, 0x0},
> > {0x200f2, 0x4444},
> > @@ -133,42 +240,83 @@ static struct dram_cfg_param ddr_ddrphy_cfg[]
> > =
> > {
> > {0x200f5, 0x0},
> > {0x200f6, 0x0},
> > {0x200f7, 0xf000},
> > + {0x1004a, 0x500},
> > + {0x1104a, 0x500},
> > {0x20025, 0x0},
> > - {0x2002d, 0x1},
> > + {0x2002d, 0x0},
> > + {0x12002d, 0x0},
> > + {0x22002d, 0x0},
> > {0x2002c, 0x0},
> > {0x20021, 0x0},
> > {0x200c7, 0x21},
> > {0x1200c7, 0x21},
> > {0x200ca, 0x24},
> > {0x1200ca, 0x24},
> > -
> > };
> >
> > -/* ddr phy trained csr */
> > +/* PHY trained csr */
> > static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> > {0x1005f, 0x0},
> > {0x1015f, 0x0},
> > {0x1105f, 0x0},
> > {0x1115f, 0x0},
> > + {0x11005f, 0x0},
> > + {0x11015f, 0x0},
> > + {0x11105f, 0x0},
> > + {0x11115f, 0x0},
> > + {0x21005f, 0x0},
> > + {0x21015f, 0x0},
> > + {0x21105f, 0x0},
> > + {0x21115f, 0x0},
> > {0x55, 0x0},
> > {0x1055, 0x0},
> > {0x2055, 0x0},
> > {0x200c5, 0x0},
> > + {0x1200c5, 0x0},
> > + {0x2200c5, 0x0},
> > {0x2002e, 0x0},
> > + {0x12002e, 0x0},
> > + {0x22002e, 0x0},
> > {0x90204, 0x0},
> > + {0x190204, 0x0},
> > + {0x290204, 0x0},
> > {0x20024, 0x0},
> > {0x2003a, 0x0},
> > {0x2007d, 0x0},
> > {0x2007c, 0x0},
> > + {0x120024, 0x0},
> > + {0x12007d, 0x0},
> > + {0x12007c, 0x0},
> > + {0x220024, 0x0},
> > + {0x22007d, 0x0},
> > + {0x22007c, 0x0},
> > {0x20056, 0x0},
> > + {0x120056, 0x0},
> > + {0x220056, 0x0},
> > {0x1004d, 0x0},
> > {0x1014d, 0x0},
> > {0x1104d, 0x0},
> > {0x1114d, 0x0},
> > + {0x11004d, 0x0},
> > + {0x11014d, 0x0},
> > + {0x11104d, 0x0},
> > + {0x11114d, 0x0},
> > + {0x21004d, 0x0},
> > + {0x21014d, 0x0},
> > + {0x21104d, 0x0},
> > + {0x21114d, 0x0},
> > {0x10049, 0x0},
> > {0x10149, 0x0},
> > {0x11049, 0x0},
> > {0x11149, 0x0},
> > + {0x110049, 0x0},
> > + {0x110149, 0x0},
> > + {0x111049, 0x0},
> > + {0x111149, 0x0},
> > + {0x210049, 0x0},
> > + {0x210149, 0x0},
> > + {0x211049, 0x0},
> > + {0x211149, 0x0},
> > {0x43, 0x0},
> > {0x1043, 0x0},
> > {0x2043, 0x0},
> > @@ -177,14 +325,30 @@ static struct dram_cfg_param
> > ddr_ddrphy_trained_csr[] = {
> > {0x20050, 0x0},
> > {0x2009b, 0x0},
> > {0x20008, 0x0},
> > + {0x120008, 0x0},
> > + {0x220008, 0x0},
> > {0x20088, 0x0},
> > {0x200b2, 0x0},
> > {0x10043, 0x0},
> > {0x10143, 0x0},
> > {0x11043, 0x0},
> > {0x11143, 0x0},
> > + {0x1200b2, 0x0},
> > + {0x110043, 0x0},
> > + {0x110143, 0x0},
> > + {0x111043, 0x0},
> > + {0x111143, 0x0},
> > + {0x2200b2, 0x0},
> > + {0x210043, 0x0},
> > + {0x210143, 0x0},
> > + {0x211043, 0x0},
> > + {0x211143, 0x0},
> > {0x200fa, 0x0},
> > + {0x1200fa, 0x0},
> > + {0x2200fa, 0x0},
> > {0x20019, 0x0},
> > + {0x120019, 0x0},
> > + {0x220019, 0x0},
> > {0x200f0, 0x0},
> > {0x200f1, 0x0},
> > {0x200f2, 0x0},
> > @@ -193,8 +357,12 @@ static struct dram_cfg_param
> > ddr_ddrphy_trained_csr[] = {
> > {0x200f5, 0x0},
> > {0x200f6, 0x0},
> > {0x200f7, 0x0},
> > + {0x1004a, 0x0},
> > + {0x1104a, 0x0},
> > {0x20025, 0x0},
> > {0x2002d, 0x0},
> > + {0x12002d, 0x0},
> > + {0x22002d, 0x0},
> > {0x2002c, 0x0},
> > {0xd0000, 0x0},
> > {0x90000, 0x0},
> > @@ -682,6 +850,14 @@ static struct dram_cfg_param
> > ddr_ddrphy_trained_csr[] = {
> > {0x2000c, 0x0},
> > {0x2000d, 0x0},
> > {0x2000e, 0x0},
> > + {0x12000b, 0x0},
> > + {0x12000c, 0x0},
> > + {0x12000d, 0x0},
> > + {0x12000e, 0x0},
> > + {0x22000b, 0x0},
> > + {0x22000c, 0x0},
> > + {0x22000d, 0x0},
> > + {0x22000e, 0x0},
> > {0x9000c, 0x0},
> > {0x9000d, 0x0},
> > {0x9000e, 0x0},
> > @@ -692,12 +868,26 @@ static struct dram_cfg_param
> > ddr_ddrphy_trained_csr[] = {
> > {0x90013, 0x0},
> > {0x20010, 0x0},
> > {0x20011, 0x0},
> > + {0x120010, 0x0},
> > + {0x120011, 0x0},
> > {0x40080, 0x0},
> > {0x40081, 0x0},
> > {0x40082, 0x0},
> > {0x40083, 0x0},
> > {0x40084, 0x0},
> > {0x40085, 0x0},
> > + {0x140080, 0x0},
> > + {0x140081, 0x0},
> > + {0x140082, 0x0},
> > + {0x140083, 0x0},
> > + {0x140084, 0x0},
> > + {0x140085, 0x0},
> > + {0x240080, 0x0},
> > + {0x240081, 0x0},
> > + {0x240082, 0x0},
> > + {0x240083, 0x0},
> > + {0x240084, 0x0},
> > + {0x240085, 0x0},
> > {0x400fd, 0x0},
> > {0x400f1, 0x0},
> > {0x10011, 0x0},
> > @@ -866,6 +1056,160 @@ static struct dram_cfg_param
> > ddr_ddrphy_trained_csr[] = {
> > {0x90207, 0x0},
> > {0x90208, 0x0},
> > {0x20020, 0x0},
> > + {0x100080, 0x0},
> > + {0x101080, 0x0},
> > + {0x102080, 0x0},
> > + {0x110020, 0x0},
> > + {0x110080, 0x0},
> > + {0x110081, 0x0},
> > + {0x1100d0, 0x0},
> > + {0x1100d1, 0x0},
> > + {0x11008c, 0x0},
> > + {0x11008d, 0x0},
> > + {0x110180, 0x0},
> > + {0x110181, 0x0},
> > + {0x1101d0, 0x0},
> > + {0x1101d1, 0x0},
> > + {0x11018c, 0x0},
> > + {0x11018d, 0x0},
> > + {0x1100c0, 0x0},
> > + {0x1100c1, 0x0},
> > + {0x1101c0, 0x0},
> > + {0x1101c1, 0x0},
> > + {0x1102c0, 0x0},
> > + {0x1102c1, 0x0},
> > + {0x1103c0, 0x0},
> > + {0x1103c1, 0x0},
> > + {0x1104c0, 0x0},
> > + {0x1104c1, 0x0},
> > + {0x1105c0, 0x0},
> > + {0x1105c1, 0x0},
> > + {0x1106c0, 0x0},
> > + {0x1106c1, 0x0},
> > + {0x1107c0, 0x0},
> > + {0x1107c1, 0x0},
> > + {0x1108c0, 0x0},
> > + {0x1108c1, 0x0},
> > + {0x1100ae, 0x0},
> > + {0x1100af, 0x0},
> > + {0x111020, 0x0},
> > + {0x111080, 0x0},
> > + {0x111081, 0x0},
> > + {0x1110d0, 0x0},
> > + {0x1110d1, 0x0},
> > + {0x11108c, 0x0},
> > + {0x11108d, 0x0},
> > + {0x111180, 0x0},
> > + {0x111181, 0x0},
> > + {0x1111d0, 0x0},
> > + {0x1111d1, 0x0},
> > + {0x11118c, 0x0},
> > + {0x11118d, 0x0},
> > + {0x1110c0, 0x0},
> > + {0x1110c1, 0x0},
> > + {0x1111c0, 0x0},
> > + {0x1111c1, 0x0},
> > + {0x1112c0, 0x0},
> > + {0x1112c1, 0x0},
> > + {0x1113c0, 0x0},
> > + {0x1113c1, 0x0},
> > + {0x1114c0, 0x0},
> > + {0x1114c1, 0x0},
> > + {0x1115c0, 0x0},
> > + {0x1115c1, 0x0},
> > + {0x1116c0, 0x0},
> > + {0x1116c1, 0x0},
> > + {0x1117c0, 0x0},
> > + {0x1117c1, 0x0},
> > + {0x1118c0, 0x0},
> > + {0x1118c1, 0x0},
> > + {0x1110ae, 0x0},
> > + {0x1110af, 0x0},
> > + {0x190201, 0x0},
> > + {0x190202, 0x0},
> > + {0x190203, 0x0},
> > + {0x190205, 0x0},
> > + {0x190206, 0x0},
> > + {0x190207, 0x0},
> > + {0x190208, 0x0},
> > + {0x120020, 0x0},
> > + {0x200080, 0x0},
> > + {0x201080, 0x0},
> > + {0x202080, 0x0},
> > + {0x210020, 0x0},
> > + {0x210080, 0x0},
> > + {0x210081, 0x0},
> > + {0x2100d0, 0x0},
> > + {0x2100d1, 0x0},
> > + {0x21008c, 0x0},
> > + {0x21008d, 0x0},
> > + {0x210180, 0x0},
> > + {0x210181, 0x0},
> > + {0x2101d0, 0x0},
> > + {0x2101d1, 0x0},
> > + {0x21018c, 0x0},
> > + {0x21018d, 0x0},
> > + {0x2100c0, 0x0},
> > + {0x2100c1, 0x0},
> > + {0x2101c0, 0x0},
> > + {0x2101c1, 0x0},
> > + {0x2102c0, 0x0},
> > + {0x2102c1, 0x0},
> > + {0x2103c0, 0x0},
> > + {0x2103c1, 0x0},
> > + {0x2104c0, 0x0},
> > + {0x2104c1, 0x0},
> > + {0x2105c0, 0x0},
> > + {0x2105c1, 0x0},
> > + {0x2106c0, 0x0},
> > + {0x2106c1, 0x0},
> > + {0x2107c0, 0x0},
> > + {0x2107c1, 0x0},
> > + {0x2108c0, 0x0},
> > + {0x2108c1, 0x0},
> > + {0x2100ae, 0x0},
> > + {0x2100af, 0x0},
> > + {0x211020, 0x0},
> > + {0x211080, 0x0},
> > + {0x211081, 0x0},
> > + {0x2110d0, 0x0},
> > + {0x2110d1, 0x0},
> > + {0x21108c, 0x0},
> > + {0x21108d, 0x0},
> > + {0x211180, 0x0},
> > + {0x211181, 0x0},
> > + {0x2111d0, 0x0},
> > + {0x2111d1, 0x0},
> > + {0x21118c, 0x0},
> > + {0x21118d, 0x0},
> > + {0x2110c0, 0x0},
> > + {0x2110c1, 0x0},
> > + {0x2111c0, 0x0},
> > + {0x2111c1, 0x0},
> > + {0x2112c0, 0x0},
> > + {0x2112c1, 0x0},
> > + {0x2113c0, 0x0},
> > + {0x2113c1, 0x0},
> > + {0x2114c0, 0x0},
> > + {0x2114c1, 0x0},
> > + {0x2115c0, 0x0},
> > + {0x2115c1, 0x0},
> > + {0x2116c0, 0x0},
> > + {0x2116c1, 0x0},
> > + {0x2117c0, 0x0},
> > + {0x2117c1, 0x0},
> > + {0x2118c0, 0x0},
> > + {0x2118c1, 0x0},
> > + {0x2110ae, 0x0},
> > + {0x2110af, 0x0},
> > + {0x290201, 0x0},
> > + {0x290202, 0x0},
> > + {0x290203, 0x0},
> > + {0x290205, 0x0},
> > + {0x290206, 0x0},
> > + {0x290207, 0x0},
> > + {0x290208, 0x0},
> > + {0x220020, 0x0},
> > {0x20077, 0x0},
> > {0x20072, 0x0},
> > {0x20073, 0x0},
> > @@ -888,7 +1232,6 @@ static struct dram_cfg_param
> > ddr_ddrphy_trained_csr[] = {
> > {0x11640, 0x0},
> > {0x11740, 0x0},
> > {0x11840, 0x0},
> > -
> > };
> >
> > /* P0 message block parameter for training firmware */
> > @@ -896,7 +1239,7 @@ static struct dram_cfg_param ddr_fsp0_cfg[] =
> > {
> > {0xd0000, 0x0},
> > {0x54003, 0xe94},
> > {0x54004, 0x4},
> > - {0x54006, 0x15},
> > + {0x54006, 0x14},
> > {0x54008, 0x131f},
> > {0x54009, 0xc8},
> > {0x5400b, 0x4},
> > @@ -904,36 +1247,113 @@ static struct dram_cfg_param ddr_fsp0_cfg[]
> > =
> > {
> > {0x5400f, 0x100},
> > {0x54012, 0x110},
> > {0x54019, 0x36e4},
> > - {0x5401a, 0xf2},
> > - {0x5401b, 0x1146},
> > - {0x5401c, 0x1108},
> > + {0x5401a, 0x22},
> > + {0x5401b, 0x1e44},
> > + {0x5401c, 0x1208},
> > {0x5401e, 0x4},
> > {0x5401f, 0x36e4},
> > - {0x54020, 0xf2},
> > - {0x54021, 0x1146},
> > - {0x54022, 0x1108},
> > + {0x54020, 0x22},
> > + {0x54021, 0x1e44},
> > + {0x54022, 0x1208},
> > {0x54024, 0x4},
> > {0x54032, 0xe400},
> > - {0x54033, 0xf236},
> > - {0x54034, 0x4600},
> > - {0x54035, 0x811},
> > - {0x54036, 0x11},
> > + {0x54033, 0x2236},
> > + {0x54034, 0x4400},
> > + {0x54035, 0x81e},
> > + {0x54036, 0x12},
> > {0x54037, 0x400},
> > {0x54038, 0xe400},
> > - {0x54039, 0xf236},
> > - {0x5403a, 0x4600},
> > - {0x5403b, 0x811},
> > - {0x5403c, 0x11},
> > + {0x54039, 0x2236},
> > + {0x5403a, 0x4400},
> > + {0x5403b, 0x81e},
> > + {0x5403c, 0x12},
> > + {0x5403d, 0x400},
> > + {0xd0000, 0x1}
> > +};
> > +
> > +/* P1 message block parameter for training firmware */
> > +static struct dram_cfg_param ddr_fsp1_cfg[] = {
> > + {0xd0000, 0x0},
> > + {0x54002, 0x1},
> > + {0x54003, 0x74a},
> > + {0x54004, 0x4},
> > + {0x54006, 0x14},
> > + {0x54008, 0x121f},
> > + {0x54009, 0xc8},
> > + {0x5400b, 0x4},
> > + {0x5400d, 0x100},
> > + {0x5400f, 0x100},
> > + {0x54012, 0x110},
> > + {0x54019, 0x1bb4},
> > + {0x5401a, 0x22},
> > + {0x5401b, 0x1e44},
> > + {0x5401c, 0x1208},
> > + {0x5401e, 0x4},
> > + {0x5401f, 0x1bb4},
> > + {0x54020, 0x22},
> > + {0x54021, 0x1e44},
> > + {0x54022, 0x1208},
> > + {0x54024, 0x4},
> > + {0x54032, 0xb400},
> > + {0x54033, 0x221b},
> > + {0x54034, 0x4400},
> > + {0x54035, 0x81e},
> > + {0x54036, 0x12},
> > + {0x54037, 0x400},
> > + {0x54038, 0xb400},
> > + {0x54039, 0x221b},
> > + {0x5403a, 0x4400},
> > + {0x5403b, 0x81e},
> > + {0x5403c, 0x12},
> > + {0x5403d, 0x400},
> > + {0xd0000, 0x1}
> > +};
> > +
> > +/* P2 message block parameter for training firmware */
> > +static struct dram_cfg_param ddr_fsp2_cfg[] = {
> > + {0xd0000, 0x0},
> > + {0x54002, 0x102},
> > + {0x54003, 0x270},
> > + {0x54004, 0x4},
> > + {0x54006, 0x14},
> > + {0x54008, 0x121f},
> > + {0x54009, 0xc8},
> > + {0x5400b, 0x4},
> > + {0x5400d, 0x100},
> > + {0x5400f, 0x100},
> > + {0x54012, 0x110},
> > + {0x54019, 0x994},
> > + {0x5401a, 0x22},
> > + {0x5401b, 0x1e44},
> > + {0x5401c, 0x1200},
> > + {0x5401e, 0x4},
> > + {0x5401f, 0x994},
> > + {0x54020, 0x22},
> > + {0x54021, 0x1e44},
> > + {0x54022, 0x1200},
> > + {0x54024, 0x4},
> > + {0x54032, 0x9400},
> > + {0x54033, 0x2209},
> > + {0x54034, 0x4400},
> > + {0x54035, 0x1e},
> > + {0x54036, 0x12},
> > + {0x54037, 0x400},
> > + {0x54038, 0x9400},
> > + {0x54039, 0x2209},
> > + {0x5403a, 0x4400},
> > + {0x5403b, 0x1e},
> > + {0x5403c, 0x12},
> > {0x5403d, 0x400},
> > {0xd0000, 0x1}
> > };
> >
> > +
> > /* P0 2D message block parameter for training firmware */
> > static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> > {0xd0000, 0x0},
> > {0x54003, 0xe94},
> > {0x54004, 0x4},
> > - {0x54006, 0x15},
> > + {0x54006, 0x14},
> > {0x54008, 0x61},
> > {0x54009, 0xc8},
> > {0x5400b, 0x4},
> > @@ -942,26 +1362,26 @@ static struct dram_cfg_param
> > ddr_fsp0_2d_cfg[]
> > = {
> > {0x54010, 0x2080},
> > {0x54012, 0x110},
> > {0x54019, 0x36e4},
> > - {0x5401a, 0xf2},
> > - {0x5401b, 0x1146},
> > - {0x5401c, 0x1108},
> > + {0x5401a, 0x22},
> > + {0x5401b, 0x1e44},
> > + {0x5401c, 0x1208},
> > {0x5401e, 0x4},
> > {0x5401f, 0x36e4},
> > - {0x54020, 0xf2},
> > - {0x54021, 0x1146},
> > - {0x54022, 0x1108},
> > + {0x54020, 0x22},
> > + {0x54021, 0x1e44},
> > + {0x54022, 0x1208},
> > {0x54024, 0x4},
> > {0x54032, 0xe400},
> > - {0x54033, 0xf236},
> > - {0x54034, 0x4600},
> > - {0x54035, 0x811},
> > - {0x54036, 0x11},
> > + {0x54033, 0x2236},
> > + {0x54034, 0x4400},
> > + {0x54035, 0x81e},
> > + {0x54036, 0x12},
> > {0x54037, 0x400},
> > {0x54038, 0xe400},
> > - {0x54039, 0xf236},
> > - {0x5403a, 0x4600},
> > - {0x5403b, 0x811},
> > - {0x5403c, 0x11},
> > + {0x54039, 0x2236},
> > + {0x5403a, 0x4400},
> > + {0x5403b, 0x81e},
> > + {0x5403c, 0x12},
> > {0x5403d, 0x400},
> > {0xd0000, 0x1}
> > };
> > @@ -1451,10 +1871,18 @@ static struct dram_cfg_param ddr_phy_pie[]
> > =
> > {
> > {0x400d7, 0x20b},
> > {0x2003a, 0x2},
> > {0x200be, 0x3},
> > - {0x2000b, 0x75},
> > + {0x2000b, 0x41a},
> > {0x2000c, 0xe9},
> > {0x2000d, 0x91c},
> > {0x2000e, 0x2c},
> > + {0x12000b, 0x20d},
> > + {0x12000c, 0x74},
> > + {0x12000d, 0x48e},
> > + {0x12000e, 0x2c},
> > + {0x22000b, 0xb0},
> > + {0x22000c, 0x27},
> > + {0x22000d, 0x186},
> > + {0x22000e, 0x10},
> > {0x9000c, 0x0},
> > {0x9000d, 0x173},
> > {0x9000e, 0x60},
> > @@ -1465,12 +1893,26 @@ static struct dram_cfg_param ddr_phy_pie[]
> > =
> > {
> > {0x90013, 0x6152},
> > {0x20010, 0x5a},
> > {0x20011, 0x3},
> > + {0x120010, 0x5a},
> > + {0x120011, 0x3},
> > {0x40080, 0xe0},
> > {0x40081, 0x12},
> > {0x40082, 0xe0},
> > {0x40083, 0x12},
> > {0x40084, 0xe0},
> > {0x40085, 0x12},
> > + {0x140080, 0xe0},
> > + {0x140081, 0x12},
> > + {0x140082, 0xe0},
> > + {0x140083, 0x12},
> > + {0x140084, 0xe0},
> > + {0x140085, 0x12},
> > + {0x240080, 0xe0},
> > + {0x240081, 0x12},
> > + {0x240082, 0xe0},
> > + {0x240083, 0x12},
> > + {0x240084, 0xe0},
> > + {0x240085, 0x12},
> > {0x400fd, 0xf},
> > {0x400f1, 0xe},
> > {0x10011, 0x1},
> > @@ -1505,7 +1947,6 @@ static struct dram_cfg_param ddr_phy_pie[] =
> > {
> > {0x20088, 0x19},
> > {0xc0080, 0x0},
> > {0xd0000, 0x1},
> > -
> > };
> >
> > static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> > @@ -1515,9 +1956,21 @@ static struct dram_fsp_msg
> > ddr_dram_fsp_msg[]
> > = {
> > .fw_type = FW_1D_IMAGE,
> > .fsp_cfg = ddr_fsp0_cfg,
> > .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> > -
> > },
> > -
> > + {
> > + /* P1 1866mts 1D */
> > + .drate = 1866,
> > + .fw_type = FW_1D_IMAGE,
> > + .fsp_cfg = ddr_fsp1_cfg,
> > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
> > + },
> > + {
> > + /* P2 625mts 1D */
> > + .drate = 625,
> > + .fw_type = FW_1D_IMAGE,
> > + .fsp_cfg = ddr_fsp2_cfg,
> > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
> > + },
> > {
> > /* P0 3733mts 2D */
> > .drate = 3733,
> > @@ -1525,7 +1978,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[]
> > =
> > {
> > .fsp_cfg = ddr_fsp0_2d_cfg,
> > .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> > },
> > -
> > };
> >
> > /* ddr timing config params */
> > @@ -1540,7 +1992,227 @@ struct dram_timing_info dram_timing = {
> > .ddrphy_trained_csr_num =
> > ARRAY_SIZE(ddr_ddrphy_trained_csr),
> > .ddrphy_pie = ddr_phy_pie,
> > .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> > - .fsp_table = { 3733, },
> > + .fsp_table = { 3733, 1866, 625, },
> > .fsp_cfg = ddr_dram_fsp_cfg,
> > .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
> > };
> > +
> > +void set_dram_timings_2gb_lpddr4x(void)
> > +{
> > + /* Initialize DDRC registers */
> > + dram_timing.ddrc_cfg[1].val = 0x8000ff;
> > + dram_timing.ddrc_cfg[3].val = 0x80000512;
> > +
> > + /* dram fsp cfg */
> > + dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x24AB321B;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x2F2EE233;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x015B015B;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x015B2213;
> > + dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
> > + dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x13;
> > +
> > + dram_timing.fsp_cfg[1].ddrc_cfg[0].val = 0x12552100;
> > + dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x1816B4AA;
> > + dram_timing.fsp_cfg[1].ddrc_cfg[9].val = 0x00AA00AA;
> > + dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
> > + dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x13;
> > +
> > + dram_timing.fsp_cfg[2].ddrc_cfg[0].val = 0x00061000;
> > + dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E62FA48;
> > + dram_timing.fsp_cfg[2].ddrc_cfg[9].val = 0x00340034;
> > + dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
> > + dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x13;
> > +
> > + /* P0 message block parameter for training firmware */
> > + dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
> > + dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1308;
> > + dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
> > + dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1308;
> > + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
> > + dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x13;
> > + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
> > + dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x13;
> > +
> > + /* P1 message block parameter for training firmware */
> > + dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
> > + dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1308;
> > + dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
> > + dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1308;
> > + dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
> > + dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x13;
> > + dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
> > + dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x13;
> > +
> > + /* P2 message block parameter for training firmware */
> > + dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
> > + dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1300;
> > + dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
> > + dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1300;
> > + dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
> > + dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x13;
> > + dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
> > + dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x13;
> > +
> > + /* P0 2D message block parameter for training firmware */
> > + dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
> > + dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1308;
> > + dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
> > + dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1308;
> > + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
> > + dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x13;
> > + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
> > + dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x13;
> > +}
> > +
> > +/* Generated with DDR Tool v3.3.0_7.8-d1cdb7d3 */
> > +void set_dram_timings_1gb_lpddr4x_900mhz(void)
> > +{
> > + /* Initialize DDRC registers */
> > + dram_timing.ddrc_cfg[6].val = 0x4080;
> > +
> > + /* dram fsp cfg */
> > + dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x124F2100;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[1].val = 0xF877000E;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x181AE4AA;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[3].val = 0x005101E6;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[4].val = 0x0E3C0000;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[5].val = 0x00009101;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[6].val = 0x30900000;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[7].val = 0x8A0A0508;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[8].val = 0x00000014;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x007B007B;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[12].val = 0x1128110B;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x007B140A;
> > + dram_timing.fsp_cfg[0].ddrc_cfg[14].val = 0x0620071E;
> > + dram_timing.fsp_cfg[0].mr_cfg[0].val = 0xB4;
> > + dram_timing.fsp_cfg[0].mr_cfg[1].val = 0x1B;
> > + dram_timing.fsp_cfg[0].mr_cfg[2].val = 0xE2;
> > + dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
> > + dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x15;
> > +
> > + dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x181AE4AA;
> > + dram_timing.fsp_cfg[1].mr_cfg[2].val = 0xE2;
> > + dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
> > + dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x15;
> > +
> > + dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E660A48;
> > + dram_timing.fsp_cfg[2].mr_cfg[2].val = 0xE2;
> > + dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
> > + dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x15;
> > +
> > + /* PHY Initialize Configuration */
> > + dram_timing.ddrphy_cfg[31].val = 0xb;
> > + dram_timing.ddrphy_cfg[86].val = 0x1d3;
> > + dram_timing.ddrphy_cfg[90].val = 0x10c;
> > + dram_timing.ddrphy_cfg[95].val = 0x10c;
> > + dram_timing.ddrphy_cfg[100].val = 0x10c;
> > + dram_timing.ddrphy_cfg[122].val = 0x1;
> > + /**
> > + * NOTE:
> > + * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array
> > members 119
> > + * (reg=0x1004a, val=0x500) and 120 (reg=0x1104a,
> > val=0x500)
> > are not
> > + * present in the ddr_ddrphy_cfg array. However they were
> > present in array
> > + * generated with previous DDR Tool v3.1.0_7.4. We simply
> > set
> > both values
> > + * to default value of 0x400 (read with
> > dwc_ddrphy_apb_rd())
> > here to avoid
> > + * any negative side-effects.
> > + */
> > + dram_timing.ddrphy_cfg[119].val = 0x400;
> > + dram_timing.ddrphy_cfg[120].val = 0x400;
> > +
> > + /**
> > + * NOTE:
> > + * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array
> > members 101
> > + * (reg=0x1004a, val=0x0) and 120 (reg=0x1104a, val=0x0)
> > are
> > not present
> > + * in the ddr_ddrphy_trained_csr array. However they were
> > present in array
> > + * generated with previous DDR Tool v3.1.0_7.4. We simply
> > set
> > both values
> > + * to default 0x0 (like all other ddrphy_trained_csr
> > values)
> > here to avoid
> > + * any negative side-effects.
> > + */
> > + /* PHY trained csr */
> > + dram_timing.ddrphy_trained_csr[101].val = 0x0;
> > + dram_timing.ddrphy_trained_csr[102].val = 0x0;
> > +
> > + /* P0 message block parameter for training firmware */
> > + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0x74a;
> > + dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x15;
> > + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x1bb4;
> > + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xe2;
> > + dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
> > + dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1508;
> > + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x1bb4;
> > + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xe2;
> > + dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
> > + dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1508;
> > + dram_timing.fsp_msg[0].fsp_cfg[20].val = 0xb400;
> > + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0xe21b;
> > + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
> > + dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x15;
> > + dram_timing.fsp_msg[0].fsp_cfg[26].val = 0xb400;
> > + dram_timing.fsp_msg[0].fsp_cfg[27].val = 0xe21b;
> > + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
> > + dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x15;
> > +
> > + /* P1 message block parameter for training firmware */
> > + dram_timing.fsp_msg[1].fsp_cfg[4].val = 0x15;
> > + dram_timing.fsp_msg[1].fsp_cfg[12].val = 0xe2;
> > + dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
> > + dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1508;
> > + dram_timing.fsp_msg[1].fsp_cfg[17].val = 0xe2;
> > + dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
> > + dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1508;
> > + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0xe21b;
> > + dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
> > + dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x15;
> > + dram_timing.fsp_msg[1].fsp_cfg[28].val = 0xe21b;
> > + dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
> > + dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x15;
> > +
> > + /* P2 message block parameter for training firmware */
> > + dram_timing.fsp_msg[2].fsp_cfg[4].val = 0x15;
> > + dram_timing.fsp_msg[2].fsp_cfg[12].val = 0xe2;
> > + dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
> > + dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1500;
> > + dram_timing.fsp_msg[2].fsp_cfg[17].val = 0xe2;
> > + dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
> > + dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1500;
> > + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0xe209;
> > + dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
> > + dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x15;
> > + dram_timing.fsp_msg[2].fsp_cfg[28].val = 0xe209;
> > + dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
> > + dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x15;
> > +
> > + /* P0 2D message block parameter for training firmware */
> > + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0x74a;
> > + dram_timing.fsp_msg[3].fsp_cfg[3].val = 0x15;
> > + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x1bb4;
> > + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xe2;
> > + dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
> > + dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1508;
> > + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x1bb4;
> > + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xe2;
> > + dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
> > + dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1508;
> > + dram_timing.fsp_msg[3].fsp_cfg[21].val = 0xb400;
> > + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0xe21b;
> > + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
> > + dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x15;
> > + dram_timing.fsp_msg[3].fsp_cfg[27].val = 0xb400;
> > + dram_timing.fsp_msg[3].fsp_cfg[28].val = 0xe21b;
> > + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
> > + dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x15;
> > +
> > + /* DRAM PHY init engine image */
> > + dram_timing.ddrphy_pie[483].val = 0x20d;
> > + dram_timing.ddrphy_pie[484].val = 0x74;
> > + dram_timing.ddrphy_pie[485].val = 0x48e;
> > +
> > + /* P0 3733mts 1D */
> > + dram_timing.fsp_msg[0].drate = 1866;
> > +
> > + /* P0 1866mts 2D */
> > + dram_timing.fsp_msg[3].drate = 1866;
> > +
> > + /* ddr timing config params */
> > + dram_timing.fsp_table[0] = 1866;
> > +}
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings
2024-11-04 12:30 ` Fabio Estevam
@ 2024-11-05 13:56 ` Christoph Stoidner
0 siblings, 0 replies; 9+ messages in thread
From: Christoph Stoidner @ 2024-11-05 13:56 UTC (permalink / raw)
To: festevam@gmail.com
Cc: PHYTEC Upstream, u-boot@lists.denx.de, m.othacehe@gmail.com
Hi Fabio,
On Mo, 2024-11-04 at 09:30 -0300, Fabio Estevam wrote:
> Hi Christoph,
>
> On Mon, Nov 4, 2024 at 7:52 AM Christoph Stoidner
> <c.stoidner@phytec.de> wrote:
> >
> > The phyCORE-i.MX 93 is available with a 1GB ram chip or a 2GB ram
> > chip.
> > Add the ram timings for the 2GB chip, in form of a diff compared
> > to the existing LPDDR4X 1GB timings. With that, the SPL can select
> > the
> > appropriate timings at startup.
> >
> > Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
> > Cc: Mathieu Othacehe <m.othacehe@gmail.com>, Christoph Stoidner
> > <c.stoidner@phytec.de>, Tom Rini <trini@konsulko.com>, Yannic Moog
> > <y.moog@phytec.de>, Primoz Fiser <primoz.fiser@norik.com>, Andrej
> > Picej <andrej.picej@norik.com>, Wadim Egorov <w.egorov@phytec.de>
>
> As Teresa pointed out, the correct way to add Cc is as follows:
>
> Cc: Mathieu Othacehe <m.othacehe@gmail.com>
> Cc: Christoph Stoidner <c.stoidner@phytec.de>
> ... etc
>
> You can even put the Cc list below the --- line so it does not appear
> in the commit log.
>
Thanks for the hint. I will do so for my next patches.
> Please run checkpatch on all the patches too. There is a warning on
> this one that is easy to fix:
>
> ./scripts/checkpatch.pl
> ~/Downloads/1-3-board-phytec-phycore-imx93-Add-2GB-LPDDR4X-RAM-
> timings.patch
> CHECK: Please don't use multiple blank lines
> #879: FILE: board/phytec/phycore_imx93/lpddr4_timing.c:1350:
>
> +
>
> total: 0 errors, 0 warnings, 1 checks, 1051 lines checked
Actually I saw that warning, but since the file was automatically
generated I decided to not change it. But honestly, we have meanwhile a
few manual changes in that file.
So I will fix it and inlucde it in a v2.
Thanks,
Christoph
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-11-05 13:56 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-11-04 10:41 [PATCH 0/3] Add support for all variants of the phyCORE-i.MX93 SOM Christoph Stoidner
2024-11-04 10:41 ` [PATCH 1/3] board: phytec: phycore-imx93: Add 2GB LPDDR4X RAM timings Christoph Stoidner
2024-11-04 12:16 ` [Upstream] " Teresa Remmet
2024-11-05 13:47 ` Christoph Stoidner
2024-11-04 12:30 ` Fabio Estevam
2024-11-05 13:56 ` Christoph Stoidner
2024-11-04 10:41 ` [PATCH 2/3] board: phytec: imx93: Add eeprom-based hardware introspection Christoph Stoidner
2024-11-04 13:53 ` [Upstream] " Wadim Egorov
2024-11-05 13:30 ` Christoph Stoidner
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