* [PATCH v4 v5 01/10] doc: board: enclustra: add Enclustra Mercury+ AA1
2024-11-19 22:46 [PATCH v4 v5 00/10] add support for Enclustra Mercury AA1 SoMs Lothar Rubusch
@ 2024-11-19 22:46 ` Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 02/10] ARM: socfpga: add Mercury+ AA1 SoM support Lothar Rubusch
` (8 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Lothar Rubusch @ 2024-11-19 22:46 UTC (permalink / raw)
To: u-boot, trini, marex, simon.k.r.goldschmidt, tien.fong.chee,
sumit.garg
Cc: sjg, xypron.glpk, michal.simek, jit.loon.lim, barnas, l.rubusch
Start documentation section for Enclustra. Cover Enclustra Intel SoMs and
related carrier board setups. The section covers the Mercury+ AA1 SoM
(Intel/arria10).
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
doc/board/enclustra/index.rst | 9 ++
doc/board/enclustra/mercury-aa1.rst | 202 ++++++++++++++++++++++++++++
doc/board/index.rst | 1 +
3 files changed, 212 insertions(+)
create mode 100644 doc/board/enclustra/index.rst
create mode 100644 doc/board/enclustra/mercury-aa1.rst
diff --git a/doc/board/enclustra/index.rst b/doc/board/enclustra/index.rst
new file mode 100644
index 0000000000..00727d0861
--- /dev/null
+++ b/doc/board/enclustra/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Enclustra
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ mercury-aa1
diff --git a/doc/board/enclustra/mercury-aa1.rst b/doc/board/enclustra/mercury-aa1.rst
new file mode 100644
index 0000000000..dec7cc3bdd
--- /dev/null
+++ b/doc/board/enclustra/mercury-aa1.rst
@@ -0,0 +1,202 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Lothar Rubusch <l.rubusch@gmail.com>
+
+Mercury AA1 Module (Arria1 10)
+==============================
+
+- SoM: https://www.enclustra.com/en/products/system-on-chip-modules/mercury-aa1/
+- Carrier board Mercury+ ST1: https://www.enclustra.com/en/products/base-boards/mercury-st1/
+- Carrier board Mercury+ PE1: https://www.enclustra.com/en/products/base-boards/mercury-pe1-200-300-400/
+- Carrier board Mercury+ PE3: https://www.enclustra.com/en/products/base-boards/mercury-pe3/
+
+There are slightly different variants of the AA1 SoM, going by the identifier.
+
+- Me-aa1-270-2i2-d11e-nfx3
+- Me-aa1-270-3e4-d11e-nfx3
+- Me-aa1-480-2i3-d12e-nfx3
+
+The u-boot setup is specific to a quartus design. Generate handoff files from
+the design. Pass them to a python script to produce a handoff.h file. This is
+needed as input for building the device-tree for u-boot. Eventually, building
+the final u-boot depends on the particular Quartus design, the particular
+carrier board, the selected boot media and boot mode.
+
+Enclustra provides reference design examples which can be built with
+OpenEmbedded using their meta-layer.
+
+- Reference Design AA1 on ST1: https://github.com/enclustra/Mercury_AA1_ST1_Reference_Design
+- Reference Design AA1 on PE1: https://github.com/enclustra/Mercury_AA1_PE1_Reference_Design
+- Reference Design AA1 on PE3: https://github.com/enclustra/Mercury_AA1_PE3_Reference_Design
+- OpenEmbedded meta-layer: https://github.com/enclustra/meta-enclustra-socfpga
+
+Quick Start
+-----------
+
+- Setup and build a Quartus design project
+- Obtain the hps.xml file from the Quartus design project
+- Generate the handoff.h file for u-boot
+- Adjust the device-tree file according to your setup
+- Build u-boot
+- Flash u-boot
+
+Build U-Boot
+------------
+
+The Quartus design produces a design specific ``hps.xml``, an ``emif.xml`` and
+a corresponding ``id`` file contained in a directory ``handoff``.
+
+Generate the handoff.h file for u-boot, from a provided ``hps.xml`` using the
+script provided in u-boot.
+
+.. code-block:: bash
+
+ $ arch/arm/mach-socfpga/qts-filter-a10.sh <where you saved it>/hps.xml arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
+
+Adjust the device-tree file according to your setup. Follow the comments in the
+file.
+
+.. code-block:: bash
+
+ $ vi ./arch/arm/dts/enclustra-aa1.dts
+
+Build u-boot. Source your favorite toolchain for ARM first.
+
+.. code-block:: bash
+
+ $ make socfpga_enclustra_mercury_aa1_defconfig
+ $ make -j8
+
+Setup and compile a boot script as needed. Depending on the boot-mode select
+``sd-aa1.cmd`` for SD/eMMC, or ``qspi-aa1.cmd`` for QSPI flash.
+
+.. code-block:: bash
+
+ $ ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "U-boot mmc startscript" -d board/enclustra/bootscripts/sd-aa1.cmd boot.scr
+
+Device-Tree setup
+-----------------
+
+The basic u-boot device-tree fragments are provided here. The handoff tools
+will generate further u-boot device-tree fragments. The various .dtsi files
+then need to be included in a top-level .dts file.
+
+Flash the U-Boot Binary to a Micro SD Card
+------------------------------------------
+
+The following example describes the full approach. Prepare a micro SD card with
+three partitions as follows e.g. on /dev/sda (check before):
+
+* ``type=c, start=2048, size=409600``
+* ``type=a2, start=411648, size=14336``
+* ``type=83, start=425984, size=1619968``
+
+.. code-block:: bash
+
+ $ cat ./partitionmap.txt
+ start= 2048, size= 102400, type=b, bootable
+ start= 104448, size= 4096, type=a2
+ start= 108544, size= 819200, type=83
+
+ $ sudo sfdisk /dev/sde < ./partitionmap.txt
+
+Note: The ``fpga.itb`` is needed to start the bootloader. A kernel
+``system.dtb`` is needed to boot into the system. Both are not part of
+u-boot, but are be provided through OpenEmbedded using Enclustra's meta-layer.
+
+Generally the bitstream files depend on the logic design, but the meta-layer
+provides a demo design. Copy the ``bitstream.periph.rbf`` and
+``bitstream.core.rbf`` from your design or OpenEmbedded's deploy directory. The
+``fpga.its`` in board/enclustra then is used to bundle them.
+
+ .. code-block:: bash
+
+ $ cp <from quartus design>/bitstream.periph.rbf ./
+ $ cp <from quartus design>/bitstream.core.rbf ./
+ $ ./tools/mkimage -E -f ./board/enclustra/mercury_aa1/fpga.its fpga.itb
+
+Format the SD card, and copy the following artifacts to the mounted boot
+partition, e.g. on /dev/sda.
+
+ .. code-block:: bash
+
+ $ mkfs.vfat -n boot /dev/sda1
+ $ mount /dev/sda1 /media/boot
+ $ cp ./{boot.scr,u-boot.img,fpga.itb,Image,system.dtb} /media/boot/
+ $ umount /dev/sda1
+
+Flash the SPL directly.
+
+ .. code-block:: bash
+
+ $ sudo dd if=./spl/u-boot-splx4.sfp of=/dev/sda2 conv=fdatasync bs=4k status=progress
+
+Format and flash a rootfs from image or files to the third partition.
+
+ .. code-block:: bash
+
+ $ mkfs.ext4 -L rootfs /dev/sda3
+ $ mount /dev/sda3 /media/rootfs
+ $ tar xf ./rootfs.tar -C /media/rootfs
+ $ umount /dev/sda3
+
+Boot Media
+----------
+
+Alternative boot media are possible as officially documented by Enclustra.
+
+* Micro-SD card
+* eMMC
+* QSPI
+
+Note: eMMC and QSPI can be flashed from off the u-boot shell. Usually after
+flashing, the correct boot mode needs to be set by a BSEL switch.
+
+Before turning on the setup, make sure to have the correct voltage configured
+at the carrier board, using the jumpers on the voltage pin header. Also make
+sure to have switched to the correct boot media using typically some dip
+switches to be found on the carrier board.
+
+Boot Log
+--------
+
+The demo shows booting a AA1 + ST1 setup and stopping at the u-boot shell.
+
+Here is the console output::
+
+ U-Boot SPL 2024.10
+ FPGA: Checking FPGA configuration setting ...
+ FPGA: Start to program peripheral/full bitstream ...
+ FPGA: Early Release Succeeded.
+ FPGA: Checking FPGA configuration setting ...
+ FPGA: Start to program peripheral/full bitstream ...
+ FPGA: Early Release Succeeded.
+
+ U-Boot SPL 2024.10
+ DDRCAL: Success
+ DDRCAL: Scrubbing ECC RAM (2048 MiB).
+ DDRCAL: Scrubbing ECC RAM done.
+ FPGA: Checking FPGA configuration setting ...
+ FPGA: Start to program core bitstream ...
+ Full Configuration Succeeded.
+ FPGA: Enter user mode.
+ Trying to boot from MMC1
+
+
+ U-Boot 2024.10
+
+ CPU: Altera SoCFPGA Arria 10
+ BOOT: SD/MMC External Transceiver (1.8V)
+ Model: Enclustra Mercury+ AA1
+ DRAM: 2 GiB
+ Core: 80 devices, 20 uclasses, devicetree: separate
+ MMC: dwmmc0@ff808000: 0
+ Loading Environment from FAT... OK
+ In: serial
+ Out: serial
+ Err: serial
+ Model: Enclustra Mercury+ AA1
+ ethaddr set to 20:B0:F7:06:0D:BE
+ eth1addr set to 20:B0:F7:06:0D:BF
+ Net: eth0: ethernet@ff800000
+ =>
+
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 3fb7c84f10..26feff48cd 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -25,6 +25,7 @@ Board-specific doc
congatec/index
coreboot/index
emulation/index
+ enclustra/index
gateworks/index
google/index
highbank/index
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 v5 02/10] ARM: socfpga: add Mercury+ AA1 SoM support
2024-11-19 22:46 [PATCH v4 v5 00/10] add support for Enclustra Mercury AA1 SoMs Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 01/10] doc: board: enclustra: add Enclustra Mercury+ AA1 Lothar Rubusch
@ 2024-11-19 22:46 ` Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 03/10] ARM: dts: socfpga: add Mercury+ AA1 for u-boot dts Lothar Rubusch
` (7 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Lothar Rubusch @ 2024-11-19 22:46 UTC (permalink / raw)
To: u-boot, trini, marex, simon.k.r.goldschmidt, tien.fong.chee,
sumit.garg
Cc: sjg, xypron.glpk, michal.simek, jit.loon.lim, barnas, l.rubusch
Introduce support for the Enclustra SoMs: Mercury+ AA1 (Intel/Arria10)
Cover general board files for SD/MMC and QSPI boot modes. Integrate the
boards to kconfig. All build variants will depend on Quartus handoff
files, thus they depend on the particular Quartus design. The approach is
covered in the according documentation part.
Additionally add configuration for SD/MMC boot and QSPI bootmodes. Register
additional targets in kconfig.
Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
arch/arm/mach-socfpga/Kconfig | 9 ++
board/enclustra/common/Makefile | 4 +
board/enclustra/mercury_aa1/Kconfig | 15 ++++
board/enclustra/mercury_aa1/MAINTAINERS | 10 +++
board/enclustra/mercury_aa1/fpga.its | 32 +++++++
.../socfpga_enclustra_mercury_aa1_defconfig | 85 +++++++++++++++++++
include/configs/socfpga_mercury_aa1.h | 23 +++++
7 files changed, 178 insertions(+)
create mode 100644 board/enclustra/common/Makefile
create mode 100644 board/enclustra/mercury_aa1/Kconfig
create mode 100644 board/enclustra/mercury_aa1/MAINTAINERS
create mode 100644 board/enclustra/mercury_aa1/fpga.its
create mode 100644 configs/socfpga_enclustra_mercury_aa1_defconfig
create mode 100644 include/configs/socfpga_mercury_aa1.h
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6b6a162f56..b7de86e934 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -184,6 +184,10 @@ config TARGET_SOCFPGA_EBV_SOCRATES
bool "EBV SoCrates (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
+ bool "Enclustra Mercury+ AA1"
+ select TARGET_SOCFPGA_ARRIA10
+
config TARGET_SOCFPGA_IS1
bool "IS1 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -237,6 +241,7 @@ config SYS_BOARD
default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "mercury_aa1" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
@@ -256,6 +261,7 @@ config SYS_VENDOR
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "enclustra" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
default "google" if TARGET_SOCFPGA_CHAMELEONV3
default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
@@ -283,6 +289,7 @@ config SYS_CONFIG_NAME
default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "socfpga_mercury_aa1" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -290,4 +297,6 @@ config SYS_CONFIG_NAME
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+source "board/enclustra/mercury_aa1/Kconfig"
+
endif
diff --git a/board/enclustra/common/Makefile b/board/enclustra/common/Makefile
new file mode 100644
index 0000000000..16c8531d74
--- /dev/null
+++ b/board/enclustra/common/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2024 Enclustra GmbH
+
+# Common for several Enclustra modules
diff --git a/board/enclustra/mercury_aa1/Kconfig b/board/enclustra/mercury_aa1/Kconfig
new file mode 100644
index 0000000000..40c7cb2687
--- /dev/null
+++ b/board/enclustra/mercury_aa1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
+
+config SYS_CPU
+ default "armv7"
+
+config SYS_BOARD
+ default "mercury_aa1"
+
+config SYS_VENDOR
+ default "enclustra"
+
+config SYS_CONFIG_NAME
+ default "socfpga_mercury_aa1"
+
+endif
diff --git a/board/enclustra/mercury_aa1/MAINTAINERS b/board/enclustra/mercury_aa1/MAINTAINERS
new file mode 100644
index 0000000000..13baf949ab
--- /dev/null
+++ b/board/enclustra/mercury_aa1/MAINTAINERS
@@ -0,0 +1,10 @@
+Enclustra Mercury+ AA1
+M: Lothar Rubusch <l.rubusch@gmail.com>
+S: Maintained
+N: board/enclustra/mercury_aa1/
+N: board/enclustra/common/
+N: configs/socfpga_enclustra_mercury_aa1_defconfig
+N: doc/board/enclustra/mercury-aa1.rst
+N: include/configs/socfpga_mercury_aa1.h
+N: enclustra
+N: mercury_aa1
diff --git a/board/enclustra/mercury_aa1/fpga.its b/board/enclustra/mercury_aa1/fpga.its
new file mode 100644
index 0000000000..cb42d61fbd
--- /dev/null
+++ b/board/enclustra/mercury_aa1/fpga.its
@@ -0,0 +1,32 @@
+/dts-v1/;
+
+/ {
+ description = "FIT image with FPGA bistream";
+ #address-cells = <1>;
+
+ images {
+ fpga-periph-1 {
+ description = "FPGA peripheral bitstream";
+ data = /incbin/("../../../bitstream.periph.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+
+ fpga-core-1 {
+ description = "FPGA core bitstream";
+ data = /incbin/("../../../bitstream.core.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "Boot with FPGA early IO release config";
+ fpga = "fpga-periph-1", "fpga-core-1";
+ };
+ };
+};
diff --git a/configs/socfpga_enclustra_mercury_aa1_defconfig b/configs/socfpga_enclustra_mercury_aa1_defconfig
new file mode 100644
index 0000000000..6a2434fe5a
--- /dev/null
+++ b/configs/socfpga_enclustra_mercury_aa1_defconfig
@@ -0,0 +1,85 @@
+CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000
+CONFIG_SF_DEFAULT_SPEED=10000000
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_ENV_SIZE=0x80000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_enclustra_mercury_aa1"
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0xffe2b000
+CONFIG_TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1=y
+CONFIG_IDENT_STRING="socfpga_arria10"
+CONFIG_SPL_FS_FAT=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 rw rootwait root=/dev/mmcblk0p3"
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="system.dtb"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CLOCKS=y
+CONFIG_SPL_PAD_TO=0x40000
+CONFIG_SPL_NO_BSS_LIMIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x15000
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+# CONFIG_CMD_BOOTDEV is not set
+# CONFIG_CMD_BOOTMETH is not set
+# CONFIG_CMD_VBE is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="boot.scr"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_MMC_DW=y
+CONFIG_BOOTDEV_SPI_FLASH=y
+# CONFIG_SPI_FLASH_LOCK is not set
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_USB=y
diff --git a/include/configs/socfpga_mercury_aa1.h b/include/configs/socfpga_mercury_aa1.h
new file mode 100644
index 0000000000..d9d169f6dd
--- /dev/null
+++ b/include/configs/socfpga_mercury_aa1.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 Enclustra GmbH
+ * <info@enclustra.com>
+ */
+
+#ifndef __CONFIG_SOCFGPA_MERCURY_AA1_H__
+#define __CONFIG_SOCFGPA_MERCURY_AA1_H__
+
+#include <asm/arch/base_addr_a10.h>
+
+/*
+ * U-Boot general configurations
+ */
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x80000000
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+#include <config_distro_bootcmd.h>
+
+#endif /* __CONFIG_SOCFGPA_MERCURY_AA1_H__ */
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 v5 03/10] ARM: dts: socfpga: add Mercury+ AA1 for u-boot dts
2024-11-19 22:46 [PATCH v4 v5 00/10] add support for Enclustra Mercury AA1 SoMs Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 01/10] doc: board: enclustra: add Enclustra Mercury+ AA1 Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 02/10] ARM: socfpga: add Mercury+ AA1 SoM support Lothar Rubusch
@ 2024-11-19 22:46 ` Lothar Rubusch
2025-01-22 4:35 ` Chee, Tien Fong
2024-11-19 22:46 ` [PATCH v4 v5 04/10] ARM: socfpga: add Enclustra storage switch Lothar Rubusch
` (6 subsequent siblings)
9 siblings, 1 reply; 13+ messages in thread
From: Lothar Rubusch @ 2024-11-19 22:46 UTC (permalink / raw)
To: u-boot, trini, marex, simon.k.r.goldschmidt, tien.fong.chee,
sumit.garg
Cc: sjg, xypron.glpk, michal.simek, jit.loon.lim, barnas, l.rubusch
Introduce u-boot specific device-tree files for Enclustra Mercury+ AA1
SoMs (Intel/arria10).
Generic device-tree fragments for linux and U-boot shall be provided in
dts/upstream. The selection of the generic device-tree fragments depends
on a selected boot-mode and a selected carrier board.
On Intel/Arria10 a handoff setup is needed for initialization of
various clock / pinmux / DRAM settings only used by U-Boot provided by
the current patch.
Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
..._arria10_enclustra_mercury_aa1-u-boot.dtsi | 45 +++
.../socfpga_arria10_enclustra_mercury_aa1.dts | 45 +++
.../socfpga_arria10_mercury_aa1-u-boot.dtsi | 19 ++
.../dts/socfpga_arria10_mercury_aa1_handoff.h | 305 ++++++++++++++++++
board/enclustra/mercury_aa1/Kconfig | 37 +++
board/enclustra/mercury_aa1/MAINTAINERS | 2 +
6 files changed, 453 insertions(+)
create mode 100644 arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts
create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
diff --git a/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-boot.dtsi
new file mode 100644
index 0000000000..6e38286572
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-boot.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Lothar Rubusch <l.rubusch@gmail.com>
+ */
+
+/* Arria10 handoff (u-boot) */
+#include "socfpga_arria10_mercury_aa1_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+/* Specific boot-mode (u-boot) */
+#if IS_ENABLED(CONFIG_ENCLUSTRA_SDMMC) || IS_ENABLED(CONFIG_ENCLUSTRA_EMMC)
+
+/ {
+ fs_loader0: fs-loader {
+ bootph-all;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&mmc 1>;
+ };
+};
+
+&fpga_mgr {
+ bootph-all;
+ firmware-loader = <&fs_loader0>;
+ altr,bitstream = "fpga.itb";
+};
+
+#elif IS_ENABLED(CONFIG_ENCLUSTRA_QSPI)
+
+/ {
+ fs_loader0: fs-loader {
+ bootph-all;
+ compatible = "u-boot,fs-loader";
+ sfconfig = <0 0 50000000 3>;
+ };
+};
+
+&fpga_mgr {
+ bootph-all;
+ firmware-loader = <&fs_loader0>;
+ altr,bitstream = "300000";
+};
+
+#endif
diff --git a/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts
new file mode 100644
index 0000000000..e8cc51a7b8
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Lothar Rubusch <l.rubusch@gmail.com>
+ */
+
+/dts-v1/;
+
+/* The arria10 family */
+#include "socfpga/socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &gmac0;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ i2c0 = &i2c1;
+ i2c1 = &i2c0;
+ spi0 = &qspi;
+ };
+};
+
+&qspi {
+ bootph-all;
+ status = "okay";
+ flash0: s25fl512s@0 {
+ bootph-all;
+
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+
+ cdns,tshsl-ns = <200>;
+ cdns,tsd2d-ns = <255>;
+ cdns,tchsh-ns = <20>;
+ cdns,tslch-ns = <20>;
+ };
+};
+
+/* Carrier board support */
+#if IS_ENABLED(CONFIG_ENCLUSTRA_PE1)
+# include "socfpga/socfpga_enclustra_mercury_pe1.dtsi"
+#elif IS_ENABLED(CONFIG_ENCLUSTRA_PE3)
+# include "socfpga/socfpga_enclustra_mercury_pe3.dtsi"
+#elif IS_ENABLED(CONFIG_ENCLUSTRA_ST1)
+# include "socfpga/socfpga_enclustra_mercury_st1.dtsi"
+#endif
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
index 8866df3ddd..ad5b5a87e0 100644
--- a/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
@@ -33,6 +33,21 @@
bootph-all;
};
+&l4_main_clk {
+ bootph-all;
+};
+
+&qspi_clk {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+ flash0: s25fl512s@0 {
+ bootph-all;
+ };
+};
+
&mmc {
bootph-all;
};
@@ -52,3 +67,7 @@
&uart1 {
bootph-all;
};
+
+&watchdog1 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h b/arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
new file mode 100644
index 0000000000..b7cdb74792
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Intel Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 60000000
+#define EMAC0_CLK_HZ 250000000
+#define EMAC1_CLK_HZ 250000000
+#define EMAC2_CLK_HZ 250000000
+#define EOSC1_CLK_HZ 33333000
+#define F2H_FREE_CLK_HZ 200000000
+#define H2F_USER0_CLK_HZ 100000000
+#define H2F_USER1_CLK_HZ 50000000
+#define L3_MAIN_FREE_CLK_HZ 400000000
+#define SDMMC_CLK_HZ 200000000
+#define TPIU_CLK_HZ 100000000
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 9
+#define MAINPLLGRP_CNTR7CLK_CNT 19
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 39
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 1
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 32
+#define MAINPLLGRP_VCO1_NUMER 1980
+#define PERPLLGRP_CNTR2CLK_CNT 7
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 19
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 499
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 0
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 32
+#define PERPLLGRP_VCO1_NUMER 1980
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 4
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+ (ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+ (ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CONFIG_IO_10_INPUT_BUF_EN 1
+#define CONFIG_IO_10_PD_DRV_STRG 10
+#define CONFIG_IO_10_PD_SLW_RT 1
+#define CONFIG_IO_10_PU_DRV_STRG 8
+#define CONFIG_IO_10_PU_SLW_RT 1
+#define CONFIG_IO_10_RTRIM 1
+#define CONFIG_IO_10_WK_PU_EN 0
+#define CONFIG_IO_11_INPUT_BUF_EN 1
+#define CONFIG_IO_11_PD_DRV_STRG 10
+#define CONFIG_IO_11_PD_SLW_RT 1
+#define CONFIG_IO_11_PU_DRV_STRG 8
+#define CONFIG_IO_11_PU_SLW_RT 1
+#define CONFIG_IO_11_RTRIM 1
+#define CONFIG_IO_11_WK_PU_EN 0
+#define CONFIG_IO_12_INPUT_BUF_EN 1
+#define CONFIG_IO_12_PD_DRV_STRG 10
+#define CONFIG_IO_12_PD_SLW_RT 1
+#define CONFIG_IO_12_PU_DRV_STRG 8
+#define CONFIG_IO_12_PU_SLW_RT 1
+#define CONFIG_IO_12_RTRIM 1
+#define CONFIG_IO_12_WK_PU_EN 0
+#define CONFIG_IO_13_INPUT_BUF_EN 1
+#define CONFIG_IO_13_PD_DRV_STRG 10
+#define CONFIG_IO_13_PD_SLW_RT 1
+#define CONFIG_IO_13_PU_DRV_STRG 8
+#define CONFIG_IO_13_PU_SLW_RT 1
+#define CONFIG_IO_13_RTRIM 1
+#define CONFIG_IO_13_WK_PU_EN 0
+#define CONFIG_IO_14_INPUT_BUF_EN 1
+#define CONFIG_IO_14_PD_DRV_STRG 10
+#define CONFIG_IO_14_PD_SLW_RT 1
+#define CONFIG_IO_14_PU_DRV_STRG 8
+#define CONFIG_IO_14_PU_SLW_RT 1
+#define CONFIG_IO_14_RTRIM 1
+#define CONFIG_IO_14_WK_PU_EN 0
+#define CONFIG_IO_15_INPUT_BUF_EN 1
+#define CONFIG_IO_15_PD_DRV_STRG 10
+#define CONFIG_IO_15_PD_SLW_RT 1
+#define CONFIG_IO_15_PU_DRV_STRG 8
+#define CONFIG_IO_15_PU_SLW_RT 1
+#define CONFIG_IO_15_RTRIM 1
+#define CONFIG_IO_15_WK_PU_EN 0
+#define CONFIG_IO_16_INPUT_BUF_EN 0
+#define CONFIG_IO_16_PD_DRV_STRG 10
+#define CONFIG_IO_16_PD_SLW_RT 1
+#define CONFIG_IO_16_PU_DRV_STRG 8
+#define CONFIG_IO_16_PU_SLW_RT 1
+#define CONFIG_IO_16_RTRIM 1
+#define CONFIG_IO_16_WK_PU_EN 0
+#define CONFIG_IO_17_INPUT_BUF_EN 1
+#define CONFIG_IO_17_PD_DRV_STRG 10
+#define CONFIG_IO_17_PD_SLW_RT 1
+#define CONFIG_IO_17_PU_DRV_STRG 8
+#define CONFIG_IO_17_PU_SLW_RT 1
+#define CONFIG_IO_17_RTRIM 1
+#define CONFIG_IO_17_WK_PU_EN 0
+#define CONFIG_IO_1_INPUT_BUF_EN 1
+#define CONFIG_IO_1_PD_DRV_STRG 10
+#define CONFIG_IO_1_PD_SLW_RT 0
+#define CONFIG_IO_1_PU_DRV_STRG 8
+#define CONFIG_IO_1_PU_SLW_RT 0
+#define CONFIG_IO_1_RTRIM 1
+#define CONFIG_IO_1_WK_PU_EN 1
+#define CONFIG_IO_2_INPUT_BUF_EN 1
+#define CONFIG_IO_2_PD_DRV_STRG 10
+#define CONFIG_IO_2_PD_SLW_RT 0
+#define CONFIG_IO_2_PU_DRV_STRG 8
+#define CONFIG_IO_2_PU_SLW_RT 0
+#define CONFIG_IO_2_RTRIM 1
+#define CONFIG_IO_2_WK_PU_EN 1
+#define CONFIG_IO_3_INPUT_BUF_EN 1
+#define CONFIG_IO_3_PD_DRV_STRG 10
+#define CONFIG_IO_3_PD_SLW_RT 0
+#define CONFIG_IO_3_PU_DRV_STRG 8
+#define CONFIG_IO_3_PU_SLW_RT 0
+#define CONFIG_IO_3_RTRIM 1
+#define CONFIG_IO_3_WK_PU_EN 1
+#define CONFIG_IO_4_INPUT_BUF_EN 1
+#define CONFIG_IO_4_PD_DRV_STRG 10
+#define CONFIG_IO_4_PD_SLW_RT 1
+#define CONFIG_IO_4_PU_DRV_STRG 8
+#define CONFIG_IO_4_PU_SLW_RT 1
+#define CONFIG_IO_4_RTRIM 1
+#define CONFIG_IO_4_WK_PU_EN 0
+#define CONFIG_IO_5_INPUT_BUF_EN 1
+#define CONFIG_IO_5_PD_DRV_STRG 10
+#define CONFIG_IO_5_PD_SLW_RT 1
+#define CONFIG_IO_5_PU_DRV_STRG 8
+#define CONFIG_IO_5_PU_SLW_RT 1
+#define CONFIG_IO_5_RTRIM 1
+#define CONFIG_IO_5_WK_PU_EN 0
+#define CONFIG_IO_6_INPUT_BUF_EN 0
+#define CONFIG_IO_6_PD_DRV_STRG 10
+#define CONFIG_IO_6_PD_SLW_RT 1
+#define CONFIG_IO_6_PU_DRV_STRG 8
+#define CONFIG_IO_6_PU_SLW_RT 1
+#define CONFIG_IO_6_RTRIM 1
+#define CONFIG_IO_6_WK_PU_EN 0
+#define CONFIG_IO_7_INPUT_BUF_EN 1
+#define CONFIG_IO_7_PD_DRV_STRG 10
+#define CONFIG_IO_7_PD_SLW_RT 1
+#define CONFIG_IO_7_PU_DRV_STRG 8
+#define CONFIG_IO_7_PU_SLW_RT 1
+#define CONFIG_IO_7_RTRIM 1
+#define CONFIG_IO_7_WK_PU_EN 0
+#define CONFIG_IO_8_INPUT_BUF_EN 1
+#define CONFIG_IO_8_PD_DRV_STRG 10
+#define CONFIG_IO_8_PD_SLW_RT 1
+#define CONFIG_IO_8_PU_DRV_STRG 8
+#define CONFIG_IO_8_PU_SLW_RT 1
+#define CONFIG_IO_8_RTRIM 1
+#define CONFIG_IO_8_WK_PU_EN 0
+#define CONFIG_IO_9_INPUT_BUF_EN 1
+#define CONFIG_IO_9_PD_DRV_STRG 10
+#define CONFIG_IO_9_PD_SLW_RT 1
+#define CONFIG_IO_9_PU_DRV_STRG 8
+#define CONFIG_IO_9_PU_SLW_RT 1
+#define CONFIG_IO_9_RTRIM 1
+#define CONFIG_IO_9_WK_PU_EN 0
+#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define PINMUX_DEDICATED_IO_10_SEL 15
+#define PINMUX_DEDICATED_IO_11_SEL 15
+#define PINMUX_DEDICATED_IO_12_SEL 15
+#define PINMUX_DEDICATED_IO_13_SEL 15
+#define PINMUX_DEDICATED_IO_14_SEL 15
+#define PINMUX_DEDICATED_IO_15_SEL 15
+#define PINMUX_DEDICATED_IO_16_SEL 13
+#define PINMUX_DEDICATED_IO_17_SEL 13
+#define PINMUX_DEDICATED_IO_4_SEL 8
+#define PINMUX_DEDICATED_IO_5_SEL 8
+#define PINMUX_DEDICATED_IO_6_SEL 8
+#define PINMUX_DEDICATED_IO_7_SEL 8
+#define PINMUX_DEDICATED_IO_8_SEL 8
+#define PINMUX_DEDICATED_IO_9_SEL 8
+#define PINMUX_I2C0_USEFPGA_SEL 0
+#define PINMUX_I2C1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
+#define PINMUX_NAND_USEFPGA_SEL 0
+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
+#define PINMUX_QSPI_USEFPGA_SEL 0
+#define PINMUX_RGMII0_USEFPGA_SEL 0
+#define PINMUX_RGMII1_USEFPGA_SEL 0
+#define PINMUX_RGMII2_USEFPGA_SEL 0
+#define PINMUX_SDMMC_USEFPGA_SEL 0
+#define PINMUX_SHARED_IO_Q1_10_SEL 8
+#define PINMUX_SHARED_IO_Q1_11_SEL 8
+#define PINMUX_SHARED_IO_Q1_12_SEL 8
+#define PINMUX_SHARED_IO_Q1_1_SEL 8
+#define PINMUX_SHARED_IO_Q1_2_SEL 8
+#define PINMUX_SHARED_IO_Q1_3_SEL 8
+#define PINMUX_SHARED_IO_Q1_4_SEL 8
+#define PINMUX_SHARED_IO_Q1_5_SEL 8
+#define PINMUX_SHARED_IO_Q1_6_SEL 8
+#define PINMUX_SHARED_IO_Q1_7_SEL 8
+#define PINMUX_SHARED_IO_Q1_8_SEL 8
+#define PINMUX_SHARED_IO_Q1_9_SEL 8
+#define PINMUX_SHARED_IO_Q2_10_SEL 4
+#define PINMUX_SHARED_IO_Q2_11_SEL 4
+#define PINMUX_SHARED_IO_Q2_12_SEL 4
+#define PINMUX_SHARED_IO_Q2_1_SEL 4
+#define PINMUX_SHARED_IO_Q2_2_SEL 4
+#define PINMUX_SHARED_IO_Q2_3_SEL 4
+#define PINMUX_SHARED_IO_Q2_4_SEL 4
+#define PINMUX_SHARED_IO_Q2_5_SEL 4
+#define PINMUX_SHARED_IO_Q2_6_SEL 4
+#define PINMUX_SHARED_IO_Q2_7_SEL 4
+#define PINMUX_SHARED_IO_Q2_8_SEL 4
+#define PINMUX_SHARED_IO_Q2_9_SEL 4
+#define PINMUX_SHARED_IO_Q3_10_SEL 15
+#define PINMUX_SHARED_IO_Q3_11_SEL 1
+#define PINMUX_SHARED_IO_Q3_12_SEL 1
+#define PINMUX_SHARED_IO_Q3_1_SEL 15
+#define PINMUX_SHARED_IO_Q3_2_SEL 15
+#define PINMUX_SHARED_IO_Q3_3_SEL 15
+#define PINMUX_SHARED_IO_Q3_4_SEL 15
+#define PINMUX_SHARED_IO_Q3_5_SEL 15
+#define PINMUX_SHARED_IO_Q3_6_SEL 15
+#define PINMUX_SHARED_IO_Q3_7_SEL 0
+#define PINMUX_SHARED_IO_Q3_8_SEL 0
+#define PINMUX_SHARED_IO_Q3_9_SEL 15
+#define PINMUX_SHARED_IO_Q4_10_SEL 15
+#define PINMUX_SHARED_IO_Q4_11_SEL 15
+#define PINMUX_SHARED_IO_Q4_12_SEL 15
+#define PINMUX_SHARED_IO_Q4_1_SEL 10
+#define PINMUX_SHARED_IO_Q4_2_SEL 10
+#define PINMUX_SHARED_IO_Q4_3_SEL 10
+#define PINMUX_SHARED_IO_Q4_4_SEL 10
+#define PINMUX_SHARED_IO_Q4_5_SEL 10
+#define PINMUX_SHARED_IO_Q4_6_SEL 10
+#define PINMUX_SHARED_IO_Q4_7_SEL 15
+#define PINMUX_SHARED_IO_Q4_8_SEL 15
+#define PINMUX_SHARED_IO_Q4_9_SEL 15
+#define PINMUX_SPIM0_USEFPGA_SEL 0
+#define PINMUX_SPIM1_USEFPGA_SEL 0
+#define PINMUX_SPIS0_USEFPGA_SEL 0
+#define PINMUX_SPIS1_USEFPGA_SEL 0
+#define PINMUX_UART0_USEFPGA_SEL 0
+#define PINMUX_UART1_USEFPGA_SEL 0
+#define PINMUX_USB0_USEFPGA_SEL 0
+#define PINMUX_USB1_USEFPGA_SEL 0
+
+/* Bridge Configuration */
+#define F2H_AXI_SLAVE 0
+#define F2SDRAM0_AXI_SLAVE 0
+#define F2SDRAM1_AXI_SLAVE 0
+#define F2SDRAM2_AXI_SLAVE 0
+#define H2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 1
+
+/* Voltage Select for Config IO */
+#define CONFIG_IO_BANK_VSEL \
+ (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+
+/* Macro for Config IO bit mapping */
+#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0x7) << 19) | \
+ ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
+ ((NAME ## _WK_PU_EN & 0x1) << 16) | \
+ ((NAME ## _PU_SLW_RT & 0x1) << 13) | \
+ ((NAME ## _PU_DRV_STRG & 0x1f) << 8) | \
+ ((NAME ## _PD_SLW_RT & 0x1) << 5) | \
+ (NAME ## _PD_DRV_STRG & 0x1f))
+
+#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
diff --git a/board/enclustra/mercury_aa1/Kconfig b/board/enclustra/mercury_aa1/Kconfig
index 40c7cb2687..a5f3c2a051 100644
--- a/board/enclustra/mercury_aa1/Kconfig
+++ b/board/enclustra/mercury_aa1/Kconfig
@@ -12,4 +12,41 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "socfpga_mercury_aa1"
+choice
+ prompt "Mercury+ AA1 base-board"
+ default ENCLUSTRA_PE1
+ help
+ Select the base-board for Mercury+ AA1.
+
+config ENCLUSTRA_PE1
+ bool "Mercury+ PE1"
+
+config ENCLUSTRA_PE3
+ bool "Mercury+ PE3"
+
+config ENCLUSTRA_ST1
+ bool "Mercury+ ST1"
+
+config ENCLUSTRA_CUSTOM_BASE
+ bool "Customized base-board"
+
+endchoice
+
+choice
+ prompt "Mercury+ AA1 boot-mode"
+ default ENCLUSTRA_SDMMC
+ help
+ Select the boot-mode for the Mercury+ AA1 setup.
+
+config ENCLUSTRA_SDMMC
+ bool "SD card"
+
+config ENCLUSTRA_EMMC
+ bool "eMMC"
+
+config ENCLUSTRA_QSPI
+ bool "QSPI flash"
+
+endchoice
+
endif
diff --git a/board/enclustra/mercury_aa1/MAINTAINERS b/board/enclustra/mercury_aa1/MAINTAINERS
index 13baf949ab..f765530770 100644
--- a/board/enclustra/mercury_aa1/MAINTAINERS
+++ b/board/enclustra/mercury_aa1/MAINTAINERS
@@ -1,6 +1,8 @@
Enclustra Mercury+ AA1
M: Lothar Rubusch <l.rubusch@gmail.com>
S: Maintained
+N: arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts
+N: arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
N: board/enclustra/mercury_aa1/
N: board/enclustra/common/
N: configs/socfpga_enclustra_mercury_aa1_defconfig
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* RE: [PATCH v4 v5 03/10] ARM: dts: socfpga: add Mercury+ AA1 for u-boot dts
2024-11-19 22:46 ` [PATCH v4 v5 03/10] ARM: dts: socfpga: add Mercury+ AA1 for u-boot dts Lothar Rubusch
@ 2025-01-22 4:35 ` Chee, Tien Fong
2025-01-27 10:30 ` Lothar Rubusch
0 siblings, 1 reply; 13+ messages in thread
From: Chee, Tien Fong @ 2025-01-22 4:35 UTC (permalink / raw)
To: Lothar Rubusch, u-boot@lists.denx.de, trini@konsulko.com,
marex@denx.de, simon.k.r.goldschmidt@gmail.com,
sumit.garg@linaro.org
Cc: sjg@chromium.org, xypron.glpk@gmx.de, michal.simek@amd.com,
Lim, Jit Loon, barnas@google.com, l.rubusch@gmail.com
Hi,
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Lothar Rubusch
> <l.rubusch@gmail.com>
> Sent: Wednesday, November 20, 2024 6:47 AM
> To: u-boot@lists.denx.de; trini@konsulko.com; marex@denx.de;
> simon.k.r.goldschmidt@gmail.com; tien.fong.chee@intel.com;
> sumit.garg@linaro.org
> Cc: sjg@chromium.org; xypron.glpk@gmx.de; michal.simek@amd.com;
> jit.loon.lim@intel.com; barnas@google.com; l.rubusch@gmail.com
> Subject: [PATCH v4 v5 03/10] ARM: dts: socfpga: add Mercury+ AA1 for u-
> boot dts
>
> Introduce u-boot specific device-tree files for Enclustra Mercury+ AA1 SoMs
> (Intel/arria10).
>
> Generic device-tree fragments for linux and U-boot shall be provided in
> dts/upstream. The selection of the generic device-tree fragments depends
> on a selected boot-mode and a selected carrier board.
>
> On Intel/Arria10 a handoff setup is needed for initialization of various clock /
> pinmux / DRAM settings only used by U-Boot provided by the current patch.
>
> Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
> Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> ---
> ..._arria10_enclustra_mercury_aa1-u-boot.dtsi | 45
> +++ .../socfpga_arria10_enclustra_mercury_aa1.dts | 45 +++
> .../socfpga_arria10_mercury_aa1-u-boot.dtsi | 19 ++
> .../dts/socfpga_arria10_mercury_aa1_handoff.h | 305
> ++++++++++++++++++
> board/enclustra/mercury_aa1/Kconfig | 37 +++
> board/enclustra/mercury_aa1/MAINTAINERS | 2 +
> 6 files changed, 453 insertions(+)
> create mode 100644 arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-
> u-boot.dtsi
> create mode 100644
> arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts
> create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
>
> diff --git a/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-
> boot.dtsi b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-
> boot.dtsi
> new file mode 100644
> index 0000000000..6e38286572
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-boot.dtsi
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +/*
> + * Copyright (C) 2024 Lothar Rubusch <l.rubusch@gmail.com> */
> +
> +/* Arria10 handoff (u-boot) */
> +#include "socfpga_arria10_mercury_aa1_handoff.h"
> +#include "socfpga_arria10-handoff.dtsi"
> +#include "socfpga_arria10_handoff_u-boot.dtsi"
> +#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
> +
> +/* Specific boot-mode (u-boot) */
> +#if IS_ENABLED(CONFIG_ENCLUSTRA_SDMMC) ||
> +IS_ENABLED(CONFIG_ENCLUSTRA_EMMC)
> +
> +/ {
> + fs_loader0: fs-loader {
> + bootph-all;
> + compatible = "u-boot,fs-loader";
> + phandlepart = <&mmc 1>;
> + };
> +};
> +
> +&fpga_mgr {
> + bootph-all;
> + firmware-loader = <&fs_loader0>;
> + altr,bitstream = "fpga.itb";
> +};
> +
> +#elif IS_ENABLED(CONFIG_ENCLUSTRA_QSPI)
> +
> +/ {
> + fs_loader0: fs-loader {
> + bootph-all;
> + compatible = "u-boot,fs-loader";
> + sfconfig = <0 0 50000000 3>;
The RAW read implementation for fs_loader is not upstream yet, I afraid this might not working, you want help to upstream?
[...]
Best regards,
TF
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v4 v5 03/10] ARM: dts: socfpga: add Mercury+ AA1 for u-boot dts
2025-01-22 4:35 ` Chee, Tien Fong
@ 2025-01-27 10:30 ` Lothar Rubusch
0 siblings, 0 replies; 13+ messages in thread
From: Lothar Rubusch @ 2025-01-27 10:30 UTC (permalink / raw)
To: Chee, Tien Fong
Cc: u-boot@lists.denx.de, trini@konsulko.com, marex@denx.de,
simon.k.r.goldschmidt@gmail.com, sumit.garg@linaro.org,
sjg@chromium.org, xypron.glpk@gmx.de, michal.simek@amd.com,
Lim, Jit Loon, barnas@google.com
On Wed, Jan 22, 2025 at 5:35 AM Chee, Tien Fong
<tien.fong.chee@intel.com> wrote:
>
> Hi,
>
> > -----Original Message-----
> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Lothar Rubusch
> > <l.rubusch@gmail.com>
> > Sent: Wednesday, November 20, 2024 6:47 AM
> > To: u-boot@lists.denx.de; trini@konsulko.com; marex@denx.de;
> > simon.k.r.goldschmidt@gmail.com; tien.fong.chee@intel.com;
> > sumit.garg@linaro.org
> > Cc: sjg@chromium.org; xypron.glpk@gmx.de; michal.simek@amd.com;
> > jit.loon.lim@intel.com; barnas@google.com; l.rubusch@gmail.com
> > Subject: [PATCH v4 v5 03/10] ARM: dts: socfpga: add Mercury+ AA1 for u-
> > boot dts
> >
> > Introduce u-boot specific device-tree files for Enclustra Mercury+ AA1 SoMs
> > (Intel/arria10).
> >
> > Generic device-tree fragments for linux and U-boot shall be provided in
> > dts/upstream. The selection of the generic device-tree fragments depends
> > on a selected boot-mode and a selected carrier board.
> >
> > On Intel/Arria10 a handoff setup is needed for initialization of various clock /
> > pinmux / DRAM settings only used by U-Boot provided by the current patch.
> >
> > Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
> > Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> > ---
> > ..._arria10_enclustra_mercury_aa1-u-boot.dtsi | 45
> > +++ .../socfpga_arria10_enclustra_mercury_aa1.dts | 45 +++
> > .../socfpga_arria10_mercury_aa1-u-boot.dtsi | 19 ++
> > .../dts/socfpga_arria10_mercury_aa1_handoff.h | 305
> > ++++++++++++++++++
> > board/enclustra/mercury_aa1/Kconfig | 37 +++
> > board/enclustra/mercury_aa1/MAINTAINERS | 2 +
> > 6 files changed, 453 insertions(+)
> > create mode 100644 arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-
> > u-boot.dtsi
> > create mode 100644
> > arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts
> > create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h
> >
> > diff --git a/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-
> > boot.dtsi b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-
> > boot.dtsi
> > new file mode 100644
> > index 0000000000..6e38286572
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-boot.dtsi
> > @@ -0,0 +1,45 @@
> > +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> > +/*
> > + * Copyright (C) 2024 Lothar Rubusch <l.rubusch@gmail.com> */
> > +
> > +/* Arria10 handoff (u-boot) */
> > +#include "socfpga_arria10_mercury_aa1_handoff.h"
> > +#include "socfpga_arria10-handoff.dtsi"
> > +#include "socfpga_arria10_handoff_u-boot.dtsi"
> > +#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
> > +
> > +/* Specific boot-mode (u-boot) */
> > +#if IS_ENABLED(CONFIG_ENCLUSTRA_SDMMC) ||
> > +IS_ENABLED(CONFIG_ENCLUSTRA_EMMC)
> > +
> > +/ {
> > + fs_loader0: fs-loader {
> > + bootph-all;
> > + compatible = "u-boot,fs-loader";
> > + phandlepart = <&mmc 1>;
> > + };
> > +};
> > +
> > +&fpga_mgr {
> > + bootph-all;
> > + firmware-loader = <&fs_loader0>;
> > + altr,bitstream = "fpga.itb";
> > +};
> > +
> > +#elif IS_ENABLED(CONFIG_ENCLUSTRA_QSPI)
> > +
> > +/ {
> > + fs_loader0: fs-loader {
> > + bootph-all;
> > + compatible = "u-boot,fs-loader";
> > + sfconfig = <0 0 50000000 3>;
>
> The RAW read implementation for fs_loader is not upstream yet, I afraid this might not working, you want help to upstream?
>
Same answer here, as in my other reply. I appreciate your answer and
bringing it up again. If this continues, for sure there will be
technical issues. In this case I'll keep you in the loop. Thanx
> [...]
>
> Best regards,
> TF
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v4 v5 04/10] ARM: socfpga: add Enclustra storage switch
2024-11-19 22:46 [PATCH v4 v5 00/10] add support for Enclustra Mercury AA1 SoMs Lothar Rubusch
` (2 preceding siblings ...)
2024-11-19 22:46 ` [PATCH v4 v5 03/10] ARM: dts: socfpga: add Mercury+ AA1 for u-boot dts Lothar Rubusch
@ 2024-11-19 22:46 ` Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 05/10] ARM: socfpga: add Mercury+ AA1 boot scripts Lothar Rubusch
` (5 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Lothar Rubusch @ 2024-11-19 22:46 UTC (permalink / raw)
To: u-boot, trini, marex, simon.k.r.goldschmidt, tien.fong.chee,
sumit.garg
Cc: sjg, xypron.glpk, michal.simek, jit.loon.lim, barnas, l.rubusch
Some of Enclustra's Intel SoMs need gpio muxing for setting up
the boot media. This can be done by switching dip switches and also in
software. The image in this case can be loaded from SD card, and flashed
to the eMMC or QSPI. After, the dip switches can set the boot select
accordingly. With altera_set_storage MMC|EMMC|QSPI from off the u-boot
shell, the media is usually switched.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
.../socfpga_arria10_enclustra_mercury_aa1.dts | 17 ++
board/enclustra/mercury_aa1/Makefile | 8 +
.../mercury_aa1/aa1_set_storage_cmd.c | 190 ++++++++++++++++++
doc/board/enclustra/mercury-aa1.rst | 25 +++
4 files changed, 240 insertions(+)
create mode 100644 board/enclustra/mercury_aa1/Makefile
create mode 100644 board/enclustra/mercury_aa1/aa1_set_storage_cmd.c
diff --git a/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts
index e8cc51a7b8..c038b2352e 100644
--- a/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts
+++ b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1.dts
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+
/* The arria10 family */
#include "socfpga/socfpga_arria10_mercury_aa1.dtsi"
@@ -17,6 +19,13 @@
i2c1 = &i2c0;
spi0 = &qspi;
};
+
+ altera_set_storage {
+ compatible = "enclustra,altera_set_storage";
+ status = "okay";
+ oe-gpios = <&portb 5 GPIO_ACTIVE_HIGH>;
+ sel-gpios = <&portc 6 GPIO_ACTIVE_HIGH>;
+ };
};
&qspi {
@@ -35,6 +44,14 @@
};
};
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
/* Carrier board support */
#if IS_ENABLED(CONFIG_ENCLUSTRA_PE1)
# include "socfpga/socfpga_enclustra_mercury_pe1.dtsi"
diff --git a/board/enclustra/mercury_aa1/Makefile b/board/enclustra/mercury_aa1/Makefile
new file mode 100644
index 0000000000..53c84d8156
--- /dev/null
+++ b/board/enclustra/mercury_aa1/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2024 Enclustra GmbH
+
+ifeq ($(CONFIG_SPL_BUILD),)
+
+obj-y += aa1_set_storage_cmd.o
+
+endif
diff --git a/board/enclustra/mercury_aa1/aa1_set_storage_cmd.c b/board/enclustra/mercury_aa1/aa1_set_storage_cmd.c
new file mode 100644
index 0000000000..31c5ddb23b
--- /dev/null
+++ b/board/enclustra/mercury_aa1/aa1_set_storage_cmd.c
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Enclustra GmbH
+ * <info@enclustra.com>
+ */
+
+#include <command.h>
+#include <env.h>
+#include <init.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <asm-generic/gpio.h>
+#include <asm/io.h>
+
+/* Pin muxing */
+#define ALTERA_NONE 0
+#define ALTERA_MMC 1
+#define ALTERA_QSPI 2
+#define ALTERA_EMMC 3
+#define MMC_CLK_DIV 0x9
+#define QSPI_CLK_DIV 0x384
+#define ALTERA_PINMUX_OFFS 0xffd07200
+#define ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE 0xFFD04078
+
+static int altera_current_storage = ALTERA_NONE;
+
+static const struct udevice_id altera_set_storage_match[] = {
+ { .compatible = "enclustra,altera_set_storage" },
+ { }
+};
+
+U_BOOT_DRIVER(altera_set_storage) = {
+ .name = "altera_set_storage",
+ .id = UCLASS_MISC,
+ .of_match = altera_set_storage_match,
+};
+
+static void enclustra_mercury_aa1_write(const u32 *pinmux_arr, int len)
+{
+ u32 i, offset, value;
+
+ for (i = 0; i < len; i += 2) {
+ offset = pinmux_arr[i];
+ value = pinmux_arr[i + 1];
+ writel(value, ALTERA_PINMUX_OFFS + offset);
+ }
+}
+
+static void enclustra_mercury_aa1_set_mux_mmc(void)
+{
+ static const u32 pinmux_arr[] = {0x0c, 0x8, // IO4 connected to SDMMC
+ 0x10, 0x8, // IO5
+ 0x14, 0x8, // IO6
+ 0x18, 0x8, // IO7
+ 0x1c, 0x8, // IO8
+ 0x20, 0x8, // IO9
+ 0x24, 0xf, // IO10 connected to GPIO
+ 0x28, 0xf, // IO11
+ 0x2c, 0xf, // IO12
+ 0x30, 0xf, // IO13
+ 0x34, 0xf, // IO14
+ 0x38, 0xf}; // IO15
+ enclustra_mercury_aa1_write(pinmux_arr, ARRAY_SIZE(pinmux_arr));
+}
+
+static void enclustra_mercury_aa1_set_mux_emmc(void)
+{
+ static const u32 pinmux_arr[] = {0x0c, 0x8, // IO4
+ 0x10, 0x8, // IO5
+ 0x14, 0x8, // IO6
+ 0x18, 0x8, // IO7
+ 0x1c, 0x8, // IO8
+ 0x20, 0x8, // IO9
+ 0x24, 0xf, // IO10
+ 0x28, 0xf, // IO11
+ 0x2c, 0x8, // IO12
+ 0x30, 0x8, // IO13
+ 0x34, 0x8, // IO14
+ 0x38, 0x8}; // IO15
+ enclustra_mercury_aa1_write(pinmux_arr, ARRAY_SIZE(pinmux_arr));
+}
+
+static void enclustra_mercury_aa1_set_mux_qspi(void)
+{
+ static const u32 pinmux_arr[] = {0x0c, 0x4, // IO4 connected to QSPI
+ 0x10, 0x4, // IO5
+ 0x14, 0x4, // IO6
+ 0x18, 0x4, // IO7
+ 0x1c, 0x4, // IO8
+ 0x20, 0x4, // IO9
+ 0x24, 0xf, // IO10
+ 0x28, 0xf, // IO11
+ 0x2c, 0xf, // IO12
+ 0x30, 0xf, // IO13
+ 0x34, 0xf, // IO14
+ 0x38, 0xf}; // IO15
+ enclustra_mercury_aa1_write(pinmux_arr, ARRAY_SIZE(pinmux_arr));
+}
+
+static int altera_set_storage(struct udevice *dev, int store)
+{
+ struct gpio_desc gpio_flash_sel;
+ struct gpio_desc gpio_flash_oe;
+ int ret;
+
+ if (store == altera_current_storage)
+ return CMD_RET_FAILURE;
+
+ /* oe: portb 5 */
+ ret = gpio_request_by_name(dev, "oe-gpios", 0,
+ &gpio_flash_oe, GPIOD_IS_OUT);
+
+ if (ret) {
+ printf("ERROR: GPIO oe not found\n");
+ return log_msg_ret("gpio", ret);
+ }
+
+ /* sel: portc 6 */
+ ret = gpio_request_by_name(dev, "sel-gpios", 0,
+ &gpio_flash_sel, GPIOD_IS_OUT);
+ if (ret) {
+ printf("ERROR: GPIO sel not found\n");
+ ret = CMD_RET_FAILURE;
+ goto err;
+ }
+
+ switch (store) {
+ case ALTERA_MMC:
+ enclustra_mercury_aa1_set_mux_mmc();
+ dm_gpio_set_value(&gpio_flash_sel, 0);
+ dm_gpio_set_value(&gpio_flash_oe, 0);
+ altera_current_storage = ALTERA_MMC;
+ writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
+ break;
+ case ALTERA_EMMC:
+ enclustra_mercury_aa1_set_mux_emmc();
+ dm_gpio_set_value(&gpio_flash_sel, 1);
+ dm_gpio_set_value(&gpio_flash_oe, 1);
+ altera_current_storage = ALTERA_EMMC;
+ writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
+ break;
+ case ALTERA_QSPI:
+ enclustra_mercury_aa1_set_mux_qspi();
+ dm_gpio_set_value(&gpio_flash_sel, 1);
+ dm_gpio_set_value(&gpio_flash_oe, 0);
+ altera_current_storage = ALTERA_QSPI;
+ writel(QSPI_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE);
+ break;
+ default:
+ altera_current_storage = ALTERA_NONE;
+ break;
+ }
+
+ ret = CMD_RET_SUCCESS;
+ dm_gpio_free(dev, &gpio_flash_sel);
+err:
+ dm_gpio_free(dev, &gpio_flash_oe);
+
+ return ret;
+}
+
+static int altera_set_storage_cmd(struct cmd_tbl *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(altera_set_storage), &dev);
+ if (ret)
+ return ret;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ if (!strcasecmp(argv[1], "mmc"))
+ return altera_set_storage(dev, ALTERA_MMC);
+ else if (!strcasecmp(argv[1], "qspi"))
+ return altera_set_storage(dev, ALTERA_QSPI);
+ else if (!strcasecmp(argv[1], "emmc"))
+ return altera_set_storage(dev, ALTERA_EMMC);
+ else
+ return CMD_RET_USAGE;
+
+ return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMD(altera_set_storage, 2, 0, altera_set_storage_cmd,
+ "Set non volatile memory access",
+ "<MMC|QSPI|EMMC> - Set access for the selected memory device");
diff --git a/doc/board/enclustra/mercury-aa1.rst b/doc/board/enclustra/mercury-aa1.rst
index dec7cc3bdd..cba36aae2e 100644
--- a/doc/board/enclustra/mercury-aa1.rst
+++ b/doc/board/enclustra/mercury-aa1.rst
@@ -151,6 +151,31 @@ Alternative boot media are possible as officially documented by Enclustra.
Note: eMMC and QSPI can be flashed from off the u-boot shell. Usually after
flashing, the correct boot mode needs to be set by a BSEL switch.
+In the u-boot shell use the following command to switch between the boot media.
+This can be used to flash e.g. eMMC or QSPI with an image file stored on the SD
+card. Approaches are described in detail in the official Enclustra
+documentation according to their releases mentioned as links.
+
+ .. code-block:: bash
+
+ Hit any key to stop autoboot: 0
+ => altera_set_storage
+ altera_set_storage - Set non volatile memory access
+ Usage:
+ altera_set_storage <MMC|QSPI|EMMC> - Set access for the selected memory device
+ => altera_set_storage QSPI
+ => sf probe
+ SF: Detected s25fl512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB
+ => altera_set_storage MMC
+ => mmc rescan
+ => mmc list
+ mmc@ff808000: 0 (SD)
+ => altera_set_storage EMMC
+ => mmc rescan
+ => mmc list
+ mmc@ff808000: 0 (eMMC)
+ =>
+
Before turning on the setup, make sure to have the correct voltage configured
at the carrier board, using the jumpers on the voltage pin header. Also make
sure to have switched to the correct boot media using typically some dip
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 v5 05/10] ARM: socfpga: add Mercury+ AA1 boot scripts
2024-11-19 22:46 [PATCH v4 v5 00/10] add support for Enclustra Mercury AA1 SoMs Lothar Rubusch
` (3 preceding siblings ...)
2024-11-19 22:46 ` [PATCH v4 v5 04/10] ARM: socfpga: add Enclustra storage switch Lothar Rubusch
@ 2024-11-19 22:46 ` Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 06/10] ARM: socfpga: AA1: support MAC from secure eeprom Lothar Rubusch
` (4 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Lothar Rubusch @ 2024-11-19 22:46 UTC (permalink / raw)
To: u-boot, trini, marex, simon.k.r.goldschmidt, tien.fong.chee,
sumit.garg
Cc: sjg, xypron.glpk, michal.simek, jit.loon.lim, barnas, l.rubusch
Add bootscripts to boot Enclustra SoMs from MicroSD card or QSPI flash.
MicroSD card as bood device here covers the cases of sdmmc or emmc as
such boot media.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
board/enclustra/bootscripts/qspi-aa1.cmd | 12 ++++++++++++
board/enclustra/bootscripts/sd-aa1.cmd | 9 +++++++++
2 files changed, 21 insertions(+)
create mode 100644 board/enclustra/bootscripts/qspi-aa1.cmd
create mode 100644 board/enclustra/bootscripts/sd-aa1.cmd
diff --git a/board/enclustra/bootscripts/qspi-aa1.cmd b/board/enclustra/bootscripts/qspi-aa1.cmd
new file mode 100644
index 0000000000..9633754491
--- /dev/null
+++ b/board/enclustra/bootscripts/qspi-aa1.cmd
@@ -0,0 +1,12 @@
+# This is an example input file for boot.scr generation.
+# Generate boot.scr
+# ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d board/enclustra/bootscripts/qspi-aa1.cmd boot.scr
+#
+# Note: The needed variables need to be set in the environment.
+bridge enable
+sf probe
+sf read $kernel_addr_r $qspi_offset_addr_kernel $kernel_size
+sf read $fdt_addr_r $qspi_offset_addr_devicetree $fdt_size
+sf read $rootfs_addr_r $qspi_offset_addr_rootfs $rootfs_size
+run fdtload_qspi
+bootm $kernel_addr_r $rootfs_addr_r $fdt_addr_r
diff --git a/board/enclustra/bootscripts/sd-aa1.cmd b/board/enclustra/bootscripts/sd-aa1.cmd
new file mode 100644
index 0000000000..604ae0760a
--- /dev/null
+++ b/board/enclustra/bootscripts/sd-aa1.cmd
@@ -0,0 +1,9 @@
+# This is an example input file for boot.scr generation.
+# Generate boot.scr
+# ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "U-boot mmc start script" -d board/enclustra/bootscripts/sd-aa1.cmd boot.scr
+#
+# Note: The needed variables need to be set in the environment.
+bridge enable
+load mmc $devnum:$distro_bootpart $kernel_addr_r Image
+load mmc $devnum:$distro_bootpart $fdt_addr_r $fdtfile
+booti $kernel_addr_r - $fdt_addr_r
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 v5 06/10] ARM: socfpga: AA1: support MAC from secure eeprom
2024-11-19 22:46 [PATCH v4 v5 00/10] add support for Enclustra Mercury AA1 SoMs Lothar Rubusch
` (4 preceding siblings ...)
2024-11-19 22:46 ` [PATCH v4 v5 05/10] ARM: socfpga: add Mercury+ AA1 boot scripts Lothar Rubusch
@ 2024-11-19 22:46 ` Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 07/10] misc: atsha204a: update kconfig description Lothar Rubusch
` (3 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Lothar Rubusch @ 2024-11-19 22:46 UTC (permalink / raw)
To: u-boot, trini, marex, simon.k.r.goldschmidt, tien.fong.chee,
sumit.garg
Cc: sjg, xypron.glpk, michal.simek, jit.loon.lim, barnas, l.rubusch
Several Enclustra devices store MAC address in a secure eeprom device. In
most cases this is the atsha204a (alternatively DS28). The atsha204a device
is preconfigured accordingly. Reading then is based on u-boot's atsha204a
driver. Add such support for Enclustra's AA1 SoMs.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
arch/arm/mach-socfpga/Kconfig | 2 +-
board/enclustra/common/Kconfig | 25 +++++
board/enclustra/common/Makefile | 3 +
board/enclustra/common/enclustra_mac.h | 48 +++++++++
board/enclustra/common/mac_atsha204.c | 102 ++++++++++++++++++
board/enclustra/common/mac_common.c | 52 +++++++++
board/enclustra/common/mac_ds28.c | 93 ++++++++++++++++
board/enclustra/mercury_aa1/Makefile | 2 +
.../mercury_aa1/aa1_board_late_init.c | 17 +++
.../socfpga_enclustra_mercury_aa1_defconfig | 1 +
10 files changed, 344 insertions(+), 1 deletion(-)
create mode 100644 board/enclustra/common/Kconfig
create mode 100644 board/enclustra/common/enclustra_mac.h
create mode 100644 board/enclustra/common/mac_atsha204.c
create mode 100644 board/enclustra/common/mac_common.c
create mode 100644 board/enclustra/common/mac_ds28.c
create mode 100644 board/enclustra/mercury_aa1/aa1_board_late_init.c
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index b7de86e934..60d8c889dc 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -297,6 +297,6 @@ config SYS_CONFIG_NAME
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
-source "board/enclustra/mercury_aa1/Kconfig"
+source "board/enclustra/common/Kconfig"
endif
diff --git a/board/enclustra/common/Kconfig b/board/enclustra/common/Kconfig
new file mode 100644
index 0000000000..4ba082e5e7
--- /dev/null
+++ b/board/enclustra/common/Kconfig
@@ -0,0 +1,25 @@
+config ENCLUSTRA_EEPROM_MAC
+ bool "Enclustra MAC address"
+ select ATSHA204A
+ depends on TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
+ default y
+ help
+ Reads the MAC address out of the EEPROM and configures the MAC
+ addresses in the environment.
+
+choice
+ prompt "Enclustra EEPROM device"
+ depends on ENCLUSTRA_EEPROM_MAC
+ default ENCLUSTRA_EEPROM_MAC_ATSHA204 if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
+ help
+ Specify the device where the MAC is stored.
+
+config ENCLUSTRA_EEPROM_MAC_ATSHA204
+ bool "MAC stored in 'ATSHA204'"
+
+config ENCLUSTRA_EEPROM_MAC_DS28
+ bool "MAC stored in 'DS28'"
+
+endchoice
+
+source "board/enclustra/mercury_aa1/Kconfig"
diff --git a/board/enclustra/common/Makefile b/board/enclustra/common/Makefile
index 16c8531d74..c83743abe7 100644
--- a/board/enclustra/common/Makefile
+++ b/board/enclustra/common/Makefile
@@ -2,3 +2,6 @@
# Copyright (c) 2024 Enclustra GmbH
# Common for several Enclustra modules
+obj-$(CONFIG_ENCLUSTRA_EEPROM_MAC) += mac_common.o
+obj-$(CONFIG_ENCLUSTRA_EEPROM_MAC_ATSHA204) += mac_atsha204.o
+obj-$(CONFIG_ENCLUSTRA_EEPROM_MAC_DS28) += mac_ds28.o
diff --git a/board/enclustra/common/enclustra_mac.h b/board/enclustra/common/enclustra_mac.h
new file mode 100644
index 0000000000..9631e9d458
--- /dev/null
+++ b/board/enclustra/common/enclustra_mac.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2024 Enclustra GmbH, <info@enclustra.com>
+ */
+
+#ifndef ENCLUSTRA_MAC
+# define ENCLUSTRA_MAC 0xF7B020
+#endif
+
+/*
+ * enclustra_mac_is_in_env - Check if MAC address is already set
+ *
+ * @env: name of the environment variable
+ * Return: true if MAC is set, false otherwise
+ */
+bool enclustra_mac_is_in_env(const char *env);
+
+/*
+ * enclustra_get_mac_is_enabled - Test if ethernet MAC is enabled in DT
+ *
+ * @alias: alias for ethernet MAC device tree node
+ * Return: 0 if OK, other value on error
+ */
+int enclustra_get_mac_is_enabled(const char *alias);
+
+/*
+ * enclustra_get_mac_from_eeprom - Get MAC address from eeprom and write it to enetaddr
+ *
+ * @enetaddr: buffer where address is to be stored
+ * @alias: alias for EEPROM device tree node
+ * Return: 0 if OK, other value on error
+ */
+int enclustra_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias);
+
+/*
+ * enclustra_get_mac1_from_mac - Get MAC1 address from MAC and write it to enetaddr
+ *
+ * @enetaddr: buffer where MAC is passed, MAC will be modified to MAC1
+ * Return: 0 if OK, else error value
+ */
+int enclustra_get_mac1_from_mac(unsigned char *enetaddr);
+
+/*
+ * enclustra_setup_mac_address - Try to get MAC address from various locations and write it to env
+ *
+ * Return: 0 if OK, other value on error
+ */
+int enclustra_setup_mac_address(void);
diff --git a/board/enclustra/common/mac_atsha204.c b/board/enclustra/common/mac_atsha204.c
new file mode 100644
index 0000000000..d582bfde0a
--- /dev/null
+++ b/board/enclustra/common/mac_atsha204.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Enclustra GmbH
+ */
+
+#include <dm.h>
+#include <atsha204a-i2c.h>
+#include <net.h>
+
+#include "enclustra_mac.h"
+
+int enclustra_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
+{
+ struct udevice *dev;
+ u32 hwaddr_h;
+ u8 data[4];
+ int i, j, eeprom_addr, mac_len, ret;
+
+ ret = uclass_get_device_by_name(UCLASS_MISC, alias, &dev);
+ if (ret) {
+ printf("%s: Failed, cannot find EEPROM! ret = %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* Make sure atsha204a is in a defined state (part of protocol) */
+ ret = atsha204a_sleep(dev);
+ if (ret) {
+ printf("%s(): Failed to bring EEPROM in defined state\n", __func__);
+ return ret;
+ }
+
+ ret = atsha204a_wakeup(dev);
+ if (ret) {
+ printf("%s(): Failed to wakeup EEPROM\n", __func__);
+ return ret;
+ }
+
+ /*
+ * Read twice portions of 4 bytes (atsha204 protocol). One from address
+ * 4 the other from address 5 of the OTP zone. Then convert the data to
+ * the 6 elements of the MAC address.
+ */
+ eeprom_addr = 4;
+ mac_len = 6;
+ for (i = 0; i < 2; i++) {
+ eeprom_addr += i;
+ if (atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, eeprom_addr, data)) {
+ printf("%s(): Failed to parse ATSHA204A_ZONE_OTP of EEPROM\n",
+ __func__);
+ return -EFAULT;
+ }
+
+ for (j = 0; j < 4 && j + i * 4 < mac_len; j++)
+ enetaddr[j + i * 4] = data[j];
+ }
+
+ /*
+ * Check if the value is a valid mac registered for
+ * Enclustra GmbH
+ */
+ hwaddr_h = enetaddr[0] | (enetaddr[1] << 8) | (enetaddr[2] << 16);
+ if ((hwaddr_h & 0xFFFFFF) != ENCLUSTRA_MAC) {
+ printf("%s(): Failed, parsed MAC is no Enclustra MAC\n", __func__);
+ return -ENOENT;
+ }
+
+ if (!is_valid_ethaddr(enetaddr)) {
+ printf("%s(): Failed, address read from EEPROM is invalid!\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ printf("ethaddr set to %pM\n", enetaddr);
+
+ return 0;
+}
+
+int enclustra_setup_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ int ret;
+
+ if (enclustra_mac_is_in_env("ethaddr"))
+ return 0;
+
+ if (enclustra_get_mac_is_enabled("ethernet0"))
+ return 0;
+
+ ret = enclustra_get_mac_from_eeprom(enetaddr, "atsha204a@64");
+ if (ret)
+ return ret;
+
+ ret = eth_env_set_enetaddr("ethaddr", enetaddr);
+ if (ret)
+ return ret;
+
+ if (!enclustra_get_mac1_from_mac(enetaddr))
+ return eth_env_set_enetaddr("eth1addr", enetaddr);
+
+ printf("%s(): Failed, unable to set MAC address!\n", __func__);
+ return -ENXIO;
+}
diff --git a/board/enclustra/common/mac_common.c b/board/enclustra/common/mac_common.c
new file mode 100644
index 0000000000..3304a8987c
--- /dev/null
+++ b/board/enclustra/common/mac_common.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Enclustra GmbH
+ */
+
+#include <dm.h>
+#include <atsha204a-i2c.h>
+#include <net.h>
+
+#include "enclustra_mac.h"
+
+bool enclustra_mac_is_in_env(const char *env)
+{
+ unsigned char enetaddr[6];
+
+ return eth_env_get_enetaddr(env, enetaddr);
+}
+
+int enclustra_get_mac_is_enabled(const char *alias)
+{
+ ofnode node = ofnode_path(alias);
+
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ if (!ofnode_is_enabled(node))
+ return -EINVAL;
+
+ return 0;
+}
+
+int enclustra_get_mac1_from_mac(unsigned char *enetaddr)
+{
+ u32 hwaddr_h;
+
+ /* Increment MAC addr */
+ hwaddr_h = (enetaddr[3] << 16) | (enetaddr[4] << 8) | enetaddr[5];
+ hwaddr_h = (hwaddr_h + 1) & 0xFFFFFF;
+ enetaddr[3] = (hwaddr_h >> 16) & 0xFF;
+ enetaddr[4] = (hwaddr_h >> 8) & 0xFF;
+ enetaddr[5] = hwaddr_h & 0xFF;
+
+ if (!is_valid_ethaddr(enetaddr)) {
+ printf("%s(): Failed, address computed from enetaddr is invalid!\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ printf("eth1addr set to %pM\n", enetaddr);
+
+ return 0;
+}
diff --git a/board/enclustra/common/mac_ds28.c b/board/enclustra/common/mac_ds28.c
new file mode 100644
index 0000000000..49c3a05317
--- /dev/null
+++ b/board/enclustra/common/mac_ds28.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Enclustra GmbH
+ */
+
+#include <linux/compat.h>
+#include <dm.h>
+#include <i2c.h>
+#include <net.h>
+
+#include "enclustra_mac.h"
+
+#define DS28_I2C_ADDR 0x5C
+#define DS28_SYS_I2C_EEPROM_BUS 0
+
+int enclustra_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
+{
+ struct udevice *dev;
+ u32 hwaddr_h;
+ struct dm_i2c_chip *chip;
+ uint chip_addr = DS28_I2C_ADDR;
+ int alen = 1;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(DS28_SYS_I2C_EEPROM_BUS, chip_addr,
+ alen, &dev);
+ if (ret)
+ return ret;
+
+ chip = dev_get_parent_plat(dev);
+ if (chip->offset_len != alen) {
+ debug("I2C chip %x: alen %d does not match offset_len %d\n",
+ chip_addr, alen, chip->offset_len);
+ return -EADDRNOTAVAIL;
+ }
+
+ ret = dm_i2c_read(dev, 0x10, enetaddr, 6);
+ if (ret) {
+ printf("%s(): Failed reading EEPROM! ret = %d\n", __func__, ret);
+ return ret;
+ }
+
+ /*
+ * Check if the value is a valid mac registered for
+ * Enclustra GmbH
+ */
+ hwaddr_h = enetaddr[0] | (enetaddr[1] << 8) | (enetaddr[2] << 16);
+ if ((hwaddr_h & 0xFFFFFF) != ENCLUSTRA_MAC) {
+ printf("%s(): Failed, parsed MAC is no Enclustra MAC\n", __func__);
+ return -ENOENT;
+ }
+
+ if (!is_valid_ethaddr(enetaddr)) {
+ printf("%s(): Failed, address read from EEPROM is invalid!\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ printf("ethaddr set to %pM\n", enetaddr);
+
+ return 0;
+}
+
+int enclustra_setup_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ int ret;
+
+ if (enclustra_mac_is_in_env("ethaddr"))
+ return 0;
+
+ if (enclustra_get_mac_is_enabled("ethernet0"))
+ return 0;
+
+ /*
+ * Note: DS28 is still not available in official DT, so referencing
+ * here by i2c busnumber and address directly
+ * preparation for DT access here, though
+ */
+ ret = enclustra_get_mac_from_eeprom(enetaddr, "");
+ if (ret)
+ return ret;
+
+ ret = eth_env_set_enetaddr("ethaddr", enetaddr);
+ if (ret)
+ return ret;
+
+ if (!enclustra_get_mac1_from_mac(enetaddr))
+ return eth_env_set_enetaddr("eth1addr", enetaddr);
+
+ printf("%s(): Failed, unable to set MAC address!\n", __func__);
+ return -ENXIO;
+}
diff --git a/board/enclustra/mercury_aa1/Makefile b/board/enclustra/mercury_aa1/Makefile
index 53c84d8156..b145254466 100644
--- a/board/enclustra/mercury_aa1/Makefile
+++ b/board/enclustra/mercury_aa1/Makefile
@@ -6,3 +6,5 @@ ifeq ($(CONFIG_SPL_BUILD),)
obj-y += aa1_set_storage_cmd.o
endif
+
+obj-y += aa1_board_late_init.o
diff --git a/board/enclustra/mercury_aa1/aa1_board_late_init.c b/board/enclustra/mercury_aa1/aa1_board_late_init.c
new file mode 100644
index 0000000000..2e8f8459e3
--- /dev/null
+++ b/board/enclustra/mercury_aa1/aa1_board_late_init.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Enclustra GmbH
+ * <info@enclustra.com>
+ */
+
+#include <env.h>
+#include <init.h>
+#include <dm/uclass.h>
+#include <dm.h>
+
+#include "../common/enclustra_mac.h"
+
+int board_late_init(void)
+{
+ return enclustra_setup_mac_address();
+}
diff --git a/configs/socfpga_enclustra_mercury_aa1_defconfig b/configs/socfpga_enclustra_mercury_aa1_defconfig
index 6a2434fe5a..5f52a30e9d 100644
--- a/configs/socfpga_enclustra_mercury_aa1_defconfig
+++ b/configs/socfpga_enclustra_mercury_aa1_defconfig
@@ -28,6 +28,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_CLOCKS=y
CONFIG_SPL_PAD_TO=0x40000
CONFIG_SPL_NO_BSS_LIMIT=y
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 v5 07/10] misc: atsha204a: update kconfig description
2024-11-19 22:46 [PATCH v4 v5 00/10] add support for Enclustra Mercury AA1 SoMs Lothar Rubusch
` (5 preceding siblings ...)
2024-11-19 22:46 ` [PATCH v4 v5 06/10] ARM: socfpga: AA1: support MAC from secure eeprom Lothar Rubusch
@ 2024-11-19 22:46 ` Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 08/10] ARM: dts: arria10: update according to DTSpec Lothar Rubusch
` (2 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Lothar Rubusch @ 2024-11-19 22:46 UTC (permalink / raw)
To: u-boot, trini, marex, simon.k.r.goldschmidt, tien.fong.chee,
sumit.garg
Cc: sjg, xypron.glpk, michal.simek, jit.loon.lim, barnas, l.rubusch
The atsha204a crypto chip is not only on the Turris Omnia board. Extend
the description of the atsha204a kconfig to cover also other boards. As
an example the Enclustra Mercury+ AA1 SoM.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
drivers/misc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6009d55f40..90fa8c9eae 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -73,7 +73,7 @@ config ATSHA204A
help
Enable support for I2C connected Atmel's ATSHA204A
CryptoAuthentication module found for example on the Turris Omnia
- board.
+ board and Enclustra SoC FPGA boards.
config GATEWORKS_SC
bool "Gateworks System Controller Support"
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 v5 08/10] ARM: dts: arria10: update according to DTSpec
2024-11-19 22:46 [PATCH v4 v5 00/10] add support for Enclustra Mercury AA1 SoMs Lothar Rubusch
` (6 preceding siblings ...)
2024-11-19 22:46 ` [PATCH v4 v5 07/10] misc: atsha204a: update kconfig description Lothar Rubusch
@ 2024-11-19 22:46 ` Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 09/10] ARM: socfpga: update function call to modern API Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 10/10] ARM: socfpga: apply binman approach to fpga parts Lothar Rubusch
9 siblings, 0 replies; 13+ messages in thread
From: Lothar Rubusch @ 2024-11-19 22:46 UTC (permalink / raw)
To: u-boot, trini, marex, simon.k.r.goldschmidt, tien.fong.chee,
sumit.garg
Cc: sjg, xypron.glpk, michal.simek, jit.loon.lim, barnas, l.rubusch
Update node-names according to DTspec. Add labels for compatibility
and/or add missing nodes in order to make the file compatible with the
corresponding counterpart in dts/upstream. Eventually the u-boot local
file then can be replaced by the dts/upstream, and eventually removed.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
arch/arm/dts/socfpga_arria10.dtsi | 42 ++++++++++++++++++++++++-------
1 file changed, 33 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index bab34ab56c..5826268823 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -15,13 +15,13 @@
#size-cells = <0>;
enable-method = "altr,socfpga-a10-smp";
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
@@ -29,7 +29,16 @@
};
};
- intc: intc@ffffd000 {
+ pmu: pmu@ff111000 {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&intc>;
+ interrupts = <0 124 4>, <0 125 4>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ reg = <0xff111000 0x1000>,
+ <0xff113000 0x1000>;
+ };
+
+ intc: interrupt-controller@ffffd000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
@@ -73,7 +82,7 @@
};
};
- base_fpga_region {
+ fpga-region {
#address-cells = <0x1>;
#size-cells = <0x1>;
@@ -638,7 +647,7 @@
reg = <0xffcfb100 0x80>;
};
- L2: l2-cache@fffff000 {
+ L2: cache-controller@fffff000 {
compatible = "arm,pl310-cache";
reg = <0xfffff000 0x1000>;
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -649,7 +658,7 @@
arm,shared-override;
};
- mmc: dwmmc0@ff808000 {
+ mmc: mmc@ff808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-dw-mshc";
@@ -662,7 +671,7 @@
status = "disabled";
};
- nand: nand@ffb90000 {
+ nand: nand-controller@ffb90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-denali-nand";
@@ -729,6 +738,16 @@
<37 IRQ_TYPE_LEVEL_HIGH>;
};
+ sdmmca-ecc@ff8c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
@@ -760,6 +779,11 @@
resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
reset-names = "qspi", "qspi-ocp";
status = "disabled";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ };
};
rst: rstmgr@ffd05000 {
@@ -828,7 +852,7 @@
reset-names = "timer";
};
- uart0: serial0@ffc02000 {
+ uart0: serial@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x100>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
@@ -839,7 +863,7 @@
status = "disabled";
};
- uart1: serial1@ffc02100 {
+ uart1: serial@ffc02100 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02100 0x100>;
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 v5 09/10] ARM: socfpga: update function call to modern API
2024-11-19 22:46 [PATCH v4 v5 00/10] add support for Enclustra Mercury AA1 SoMs Lothar Rubusch
` (7 preceding siblings ...)
2024-11-19 22:46 ` [PATCH v4 v5 08/10] ARM: dts: arria10: update according to DTSpec Lothar Rubusch
@ 2024-11-19 22:46 ` Lothar Rubusch
2024-11-19 22:46 ` [PATCH v4 v5 10/10] ARM: socfpga: apply binman approach to fpga parts Lothar Rubusch
9 siblings, 0 replies; 13+ messages in thread
From: Lothar Rubusch @ 2024-11-19 22:46 UTC (permalink / raw)
To: u-boot, trini, marex, simon.k.r.goldschmidt, tien.fong.chee,
sumit.garg
Cc: sjg, xypron.glpk, michal.simek, jit.loon.lim, barnas, l.rubusch
Remove arguments in the function call. The call's argument list differs
from its definition, which breaks compilation. The removed arguments are
obtained from device-tree declaration.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
arch/arm/mach-socfpga/misc_arria10.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index c442af0288..1e20f77773 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -214,8 +214,6 @@ int qspi_flash_software_reset(void)
/* Get the flash info */
ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,
CONFIG_SF_DEFAULT_CS,
- CONFIG_SF_DEFAULT_SPEED,
- CONFIG_SF_DEFAULT_MODE,
&flash);
if (ret) {
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 v5 10/10] ARM: socfpga: apply binman approach to fpga parts
2024-11-19 22:46 [PATCH v4 v5 00/10] add support for Enclustra Mercury AA1 SoMs Lothar Rubusch
` (8 preceding siblings ...)
2024-11-19 22:46 ` [PATCH v4 v5 09/10] ARM: socfpga: update function call to modern API Lothar Rubusch
@ 2024-11-19 22:46 ` Lothar Rubusch
9 siblings, 0 replies; 13+ messages in thread
From: Lothar Rubusch @ 2024-11-19 22:46 UTC (permalink / raw)
To: u-boot, trini, marex, simon.k.r.goldschmidt, tien.fong.chee,
sumit.garg
Cc: sjg, xypron.glpk, michal.simek, jit.loon.lim, barnas, l.rubusch
Convert the .its based approach to binman instruction covered in the
device tree generation. This reduces additional instructions and
integrates the former separate build step into building the u-boot.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
..._arria10_enclustra_mercury_aa1-u-boot.dtsi | 44 +++++++++++++++++++
arch/arm/mach-socfpga/Kconfig | 1 +
board/enclustra/mercury_aa1/fpga.its | 32 --------------
doc/board/enclustra/mercury-aa1.rst | 3 ++
4 files changed, 48 insertions(+), 32 deletions(-)
delete mode 100644 board/enclustra/mercury_aa1/fpga.its
diff --git a/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-boot.dtsi
index 6e38286572..9587d2dddb 100644
--- a/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_enclustra_mercury_aa1-u-boot.dtsi
@@ -18,6 +18,10 @@
compatible = "u-boot,fs-loader";
phandlepart = <&mmc 1>;
};
+
+ binman: binman {
+ multiple-images;
+ };
};
&fpga_mgr {
@@ -43,3 +47,43 @@
};
#endif
+
+&binman {
+ u-boot {
+ filename = "fpga.itb";
+
+ fit {
+ description = "FIT image with FPGA bistream";
+ fit,external-offset = <0>;
+ #address-cells = <1>;
+
+ images {
+ fpga-periph-1 {
+ description = "FPGA peripheral bitstream";
+ type = "fpga";
+ compression = "none";
+ blob-ext {
+ filename = "bitstream.periph.rbf";
+ };
+ };
+
+ fpga-core-1 {
+ description = "FPGA core bitstream";
+ type = "fpga";
+ compression = "none";
+ blob-ext {
+ filename = "bitstream.core.rbf";
+ };
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "Boot with FPGA early IO release config";
+ fpga = "fpga-periph-1", "fpga-core-1";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 60d8c889dc..e7236a56f7 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -186,6 +186,7 @@ config TARGET_SOCFPGA_EBV_SOCRATES
config TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1
bool "Enclustra Mercury+ AA1"
+ select BINMAN
select TARGET_SOCFPGA_ARRIA10
config TARGET_SOCFPGA_IS1
diff --git a/board/enclustra/mercury_aa1/fpga.its b/board/enclustra/mercury_aa1/fpga.its
deleted file mode 100644
index cb42d61fbd..0000000000
--- a/board/enclustra/mercury_aa1/fpga.its
+++ /dev/null
@@ -1,32 +0,0 @@
-/dts-v1/;
-
-/ {
- description = "FIT image with FPGA bistream";
- #address-cells = <1>;
-
- images {
- fpga-periph-1 {
- description = "FPGA peripheral bitstream";
- data = /incbin/("../../../bitstream.periph.rbf");
- type = "fpga";
- arch = "arm";
- compression = "none";
- };
-
- fpga-core-1 {
- description = "FPGA core bitstream";
- data = /incbin/("../../../bitstream.core.rbf");
- type = "fpga";
- arch = "arm";
- compression = "none";
- };
- };
-
- configurations {
- default = "config-1";
- config-1 {
- description = "Boot with FPGA early IO release config";
- fpga = "fpga-periph-1", "fpga-core-1";
- };
- };
-};
diff --git a/doc/board/enclustra/mercury-aa1.rst b/doc/board/enclustra/mercury-aa1.rst
index cba36aae2e..f3c629d42e 100644
--- a/doc/board/enclustra/mercury-aa1.rst
+++ b/doc/board/enclustra/mercury-aa1.rst
@@ -66,6 +66,9 @@ Build u-boot. Source your favorite toolchain for ARM first.
$ make socfpga_enclustra_mercury_aa1_defconfig
$ make -j8
+Note: Call ``make`` with ``NO_PYTHON=1`` where python tools unnecessarily falls
+back into additional python setup.
+
Setup and compile a boot script as needed. Depending on the boot-mode select
``sd-aa1.cmd`` for SD/eMMC, or ``qspi-aa1.cmd`` for QSPI flash.
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread