* [PATCH v5 1/4] arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
2025-01-04 1:57 [PATCH v5 0/4] rockchip: Add support for Radxa ROCK 5C FUKAUMI Naoki
@ 2025-01-04 1:57 ` FUKAUMI Naoki
2025-01-08 6:56 ` Kever Yang
2025-01-04 1:57 ` [PATCH v5 2/4] arm64: dts: rockchip: Add HDMI0 node to rk3588 FUKAUMI Naoki
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: FUKAUMI Naoki @ 2025-01-04 1:57 UTC (permalink / raw)
To: u-boot
Cc: sjg, philipp.tomsich, kever.yang, trini, sumit.garg, jonas,
eugen.hristev, quentin.schulz, michal.simek, seb-dev,
liujianfeng1994, heiko, zhangzj, macromorgan, dsimic, pbrobinson,
cfsworks, sebastian.reichel, alchark, didi.debian, cassel,
boris.brezillon, cristian.ciocaltea, jing, Sam Edwards
From: Sam Edwards <cfsworks@gmail.com>
These pinctrls manage the low-speed PCIe signals:
- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
request that external clock-generation circuitry provide a clock.
- PERST#: An input on the RK3588 in EP mode, used to detect a reset
signal from the RC. In RC mode, the hardware does not use this signal:
Linux itself generates it by putting the pin in GPIO mode.
- WAKE#: In EP mode, this is an output; in RC mode, this is an input.
Each of these signals serves a distinct purpose, and more importantly,
PERST# should not be muxed when the RK3588 is in the RC role. Bundling
them together in pinctrl groups prevents proper use: indeed, almost none
of the current board-specific .dts files make any use of them.
(Exception: Rock 5A recently had a patch land that misuses _pins; this
patch corrects that.)
However, on some RK3588 boards, the PCIe 3 controller will indefinitely
stall the boot if CLKREQ# is not muxed (details in the next patch).
This patch unbundles the signals to allow them to be used.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 4294e32111781b3de4d73b944cbd1bc1662a9a7a ]
(cherry picked from commit 8713425fa162b61bcf5f7a6dcd171fddfb12be36)
---
.../arm64/rockchip/rk3588-base-pinctrl.dtsi | 271 ++++++++++++++----
.../src/arm64/rockchip/rk3588s-rock-5a.dts | 6 +-
2 files changed, 228 insertions(+), 49 deletions(-)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi
index d1368418502a..7f874c77410c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi
@@ -1612,23 +1612,43 @@
pcie20x1 {
/omit-if-no-ref/
- pcie20x1m0_pins: pcie20x1m0-pins {
+ pcie20x1m0_clkreqn: pcie20x1m0-clkreqn {
rockchip,pins =
/* pcie20x1_2_clkreqn_m0 */
- <3 RK_PC7 4 &pcfg_pull_none>,
+ <3 RK_PC7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m0_perstn: pcie20x1m0-perstn {
+ rockchip,pins =
/* pcie20x1_2_perstn_m0 */
- <3 RK_PD1 4 &pcfg_pull_none>,
+ <3 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m0_waken: pcie20x1m0-waken {
+ rockchip,pins =
/* pcie20x1_2_waken_m0 */
<3 RK_PD0 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie20x1m1_pins: pcie20x1m1-pins {
+ pcie20x1m1_clkreqn: pcie20x1m1-clkreqn {
rockchip,pins =
/* pcie20x1_2_clkreqn_m1 */
- <4 RK_PB7 4 &pcfg_pull_none>,
+ <4 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m1_perstn: pcie20x1m1-perstn {
+ rockchip,pins =
/* pcie20x1_2_perstn_m1 */
- <4 RK_PC1 4 &pcfg_pull_none>,
+ <4 RK_PC1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m1_waken: pcie20x1m1-waken {
+ rockchip,pins =
/* pcie20x1_2_waken_m1 */
<4 RK_PC0 4 &pcfg_pull_none>;
};
@@ -1654,52 +1674,127 @@
pcie30x1 {
/omit-if-no-ref/
- pcie30x1m0_pins: pcie30x1m0-pins {
+ pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn {
rockchip,pins =
/* pcie30x1_0_clkreqn_m0 */
- <0 RK_PC0 12 &pcfg_pull_none>,
+ <0 RK_PC0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_0_perstn: pcie30x1m0-0-perstn {
+ rockchip,pins =
/* pcie30x1_0_perstn_m0 */
- <0 RK_PC5 12 &pcfg_pull_none>,
+ <0 RK_PC5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_0_waken: pcie30x1m0-0-waken {
+ rockchip,pins =
/* pcie30x1_0_waken_m0 */
- <0 RK_PC4 12 &pcfg_pull_none>,
+ <0 RK_PC4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn {
+ rockchip,pins =
/* pcie30x1_1_clkreqn_m0 */
- <0 RK_PB5 12 &pcfg_pull_none>,
+ <0 RK_PB5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_1_perstn: pcie30x1m0-1-perstn {
+ rockchip,pins =
/* pcie30x1_1_perstn_m0 */
- <0 RK_PB7 12 &pcfg_pull_none>,
+ <0 RK_PB7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_1_waken: pcie30x1m0-1-waken {
+ rockchip,pins =
/* pcie30x1_1_waken_m0 */
<0 RK_PB6 12 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x1m1_pins: pcie30x1m1-pins {
+ pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn {
rockchip,pins =
/* pcie30x1_0_clkreqn_m1 */
- <4 RK_PA3 4 &pcfg_pull_none>,
+ <4 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_0_perstn: pcie30x1m1-0-perstn {
+ rockchip,pins =
/* pcie30x1_0_perstn_m1 */
- <4 RK_PA5 4 &pcfg_pull_none>,
+ <4 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_0_waken: pcie30x1m1-0-waken {
+ rockchip,pins =
/* pcie30x1_0_waken_m1 */
- <4 RK_PA4 4 &pcfg_pull_none>,
+ <4 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn {
+ rockchip,pins =
/* pcie30x1_1_clkreqn_m1 */
- <4 RK_PA0 4 &pcfg_pull_none>,
+ <4 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_1_perstn: pcie30x1m1-1-perstn {
+ rockchip,pins =
/* pcie30x1_1_perstn_m1 */
- <4 RK_PA2 4 &pcfg_pull_none>,
+ <4 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_1_waken: pcie30x1m1-1-waken {
+ rockchip,pins =
/* pcie30x1_1_waken_m1 */
<4 RK_PA1 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x1m2_pins: pcie30x1m2-pins {
+ pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn {
rockchip,pins =
/* pcie30x1_0_clkreqn_m2 */
- <1 RK_PB5 4 &pcfg_pull_none>,
+ <1 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_0_perstn: pcie30x1m2-0-perstn {
+ rockchip,pins =
/* pcie30x1_0_perstn_m2 */
- <1 RK_PB4 4 &pcfg_pull_none>,
+ <1 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_0_waken: pcie30x1m2-0-waken {
+ rockchip,pins =
/* pcie30x1_0_waken_m2 */
- <1 RK_PB3 4 &pcfg_pull_none>,
+ <1 RK_PB3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn {
+ rockchip,pins =
/* pcie30x1_1_clkreqn_m2 */
- <1 RK_PA0 4 &pcfg_pull_none>,
+ <1 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_1_perstn: pcie30x1m2-1-perstn {
+ rockchip,pins =
/* pcie30x1_1_perstn_m2 */
- <1 RK_PA7 4 &pcfg_pull_none>,
+ <1 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_1_waken: pcie30x1m2-1-waken {
+ rockchip,pins =
/* pcie30x1_1_waken_m2 */
<1 RK_PA1 4 &pcfg_pull_none>;
};
@@ -1721,45 +1816,85 @@
pcie30x2 {
/omit-if-no-ref/
- pcie30x2m0_pins: pcie30x2m0-pins {
+ pcie30x2m0_clkreqn: pcie30x2m0-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m0 */
- <0 RK_PD1 12 &pcfg_pull_none>,
+ <0 RK_PD1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m0_perstn: pcie30x2m0-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m0 */
- <0 RK_PD4 12 &pcfg_pull_none>,
+ <0 RK_PD4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m0_waken: pcie30x2m0-waken {
+ rockchip,pins =
/* pcie30x2_waken_m0 */
<0 RK_PD2 12 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x2m1_pins: pcie30x2m1-pins {
+ pcie30x2m1_clkreqn: pcie30x2m1-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m1 */
- <4 RK_PA6 4 &pcfg_pull_none>,
+ <4 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m1_perstn: pcie30x2m1-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m1 */
- <4 RK_PB0 4 &pcfg_pull_none>,
+ <4 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m1_waken: pcie30x2m1-waken {
+ rockchip,pins =
/* pcie30x2_waken_m1 */
<4 RK_PA7 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x2m2_pins: pcie30x2m2-pins {
+ pcie30x2m2_clkreqn: pcie30x2m2-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m2 */
- <3 RK_PD2 4 &pcfg_pull_none>,
+ <3 RK_PD2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m2_perstn: pcie30x2m2-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m2 */
- <3 RK_PD4 4 &pcfg_pull_none>,
+ <3 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m2_waken: pcie30x2m2-waken {
+ rockchip,pins =
/* pcie30x2_waken_m2 */
<3 RK_PD3 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x2m3_pins: pcie30x2m3-pins {
+ pcie30x2m3_clkreqn: pcie30x2m3-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m3 */
- <1 RK_PD7 4 &pcfg_pull_none>,
+ <1 RK_PD7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m3_perstn: pcie30x2m3-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m3 */
- <1 RK_PB7 4 &pcfg_pull_none>,
+ <1 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m3_waken: pcie30x2m3-waken {
+ rockchip,pins =
/* pcie30x2_waken_m3 */
<1 RK_PB6 4 &pcfg_pull_none>;
};
@@ -1774,45 +1909,85 @@
pcie30x4 {
/omit-if-no-ref/
- pcie30x4m0_pins: pcie30x4m0-pins {
+ pcie30x4m0_clkreqn: pcie30x4m0-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m0 */
- <0 RK_PC6 12 &pcfg_pull_none>,
+ <0 RK_PC6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m0_perstn: pcie30x4m0-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m0 */
- <0 RK_PD0 12 &pcfg_pull_none>,
+ <0 RK_PD0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m0_waken: pcie30x4m0-waken {
+ rockchip,pins =
/* pcie30x4_waken_m0 */
<0 RK_PC7 12 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x4m1_pins: pcie30x4m1-pins {
+ pcie30x4m1_clkreqn: pcie30x4m1-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m1 */
- <4 RK_PB4 4 &pcfg_pull_none>,
+ <4 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m1_perstn: pcie30x4m1-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m1 */
- <4 RK_PB6 4 &pcfg_pull_none>,
+ <4 RK_PB6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m1_waken: pcie30x4m1-waken {
+ rockchip,pins =
/* pcie30x4_waken_m1 */
<4 RK_PB5 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x4m2_pins: pcie30x4m2-pins {
+ pcie30x4m2_clkreqn: pcie30x4m2-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m2 */
- <3 RK_PC4 4 &pcfg_pull_none>,
+ <3 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m2_perstn: pcie30x4m2-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m2 */
- <3 RK_PC6 4 &pcfg_pull_none>,
+ <3 RK_PC6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m2_waken: pcie30x4m2-waken {
+ rockchip,pins =
/* pcie30x4_waken_m2 */
<3 RK_PC5 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x4m3_pins: pcie30x4m3-pins {
+ pcie30x4m3_clkreqn: pcie30x4m3-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m3 */
- <1 RK_PB0 4 &pcfg_pull_none>,
+ <1 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m3_perstn: pcie30x4m3-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m3 */
- <1 RK_PB2 4 &pcfg_pull_none>,
+ <1 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m3_waken: pcie30x4m3-waken {
+ rockchip,pins =
/* pcie30x4_waken_m3 */
<1 RK_PB1 4 &pcfg_pull_none>;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
index 294b99dd50da..87fce8d9a964 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
@@ -310,7 +310,7 @@
};
&pcie2x1l2 {
- pinctrl-0 = <&pcie20x1m0_pins>;
+ pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>;
pinctrl-names = "default";
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_wf>;
@@ -328,6 +328,10 @@
pow_en: pow-en {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
+
+ pcie2_reset: pcie2-reset {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
power {
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v5 1/4] arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
2025-01-04 1:57 ` [PATCH v5 1/4] arm64: dts: rockchip: Split up RK3588's PCIe pinctrls FUKAUMI Naoki
@ 2025-01-08 6:56 ` Kever Yang
0 siblings, 0 replies; 10+ messages in thread
From: Kever Yang @ 2025-01-08 6:56 UTC (permalink / raw)
To: FUKAUMI Naoki, u-boot
Cc: sjg, philipp.tomsich, trini, sumit.garg, jonas, eugen.hristev,
quentin.schulz, michal.simek, seb-dev, liujianfeng1994, heiko,
zhangzj, macromorgan, dsimic, pbrobinson, cfsworks,
sebastian.reichel, alchark, didi.debian, cassel, boris.brezillon,
cristian.ciocaltea, jing
On 2025/1/4 09:57, FUKAUMI Naoki wrote:
> From: Sam Edwards <cfsworks@gmail.com>
>
> These pinctrls manage the low-speed PCIe signals:
> - CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
> request that external clock-generation circuitry provide a clock.
> - PERST#: An input on the RK3588 in EP mode, used to detect a reset
> signal from the RC. In RC mode, the hardware does not use this signal:
> Linux itself generates it by putting the pin in GPIO mode.
> - WAKE#: In EP mode, this is an output; in RC mode, this is an input.
>
> Each of these signals serves a distinct purpose, and more importantly,
> PERST# should not be muxed when the RK3588 is in the RC role. Bundling
> them together in pinctrl groups prevents proper use: indeed, almost none
> of the current board-specific .dts files make any use of them.
> (Exception: Rock 5A recently had a patch land that misuses _pins; this
> patch corrects that.)
>
> However, on some RK3588 boards, the PCIe 3 controller will indefinitely
> stall the boot if CLKREQ# is not muxed (details in the next patch).
> This patch unbundles the signals to allow them to be used.
>
> Signed-off-by: Sam Edwards <CFSworks@gmail.com>
> Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 4294e32111781b3de4d73b944cbd1bc1662a9a7a ]
>
> (cherry picked from commit 8713425fa162b61bcf5f7a6dcd171fddfb12be36)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../arm64/rockchip/rk3588-base-pinctrl.dtsi | 271 ++++++++++++++----
> .../src/arm64/rockchip/rk3588s-rock-5a.dts | 6 +-
> 2 files changed, 228 insertions(+), 49 deletions(-)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi
> index d1368418502a..7f874c77410c 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi
> @@ -1612,23 +1612,43 @@
>
> pcie20x1 {
> /omit-if-no-ref/
> - pcie20x1m0_pins: pcie20x1m0-pins {
> + pcie20x1m0_clkreqn: pcie20x1m0-clkreqn {
> rockchip,pins =
> /* pcie20x1_2_clkreqn_m0 */
> - <3 RK_PC7 4 &pcfg_pull_none>,
> + <3 RK_PC7 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie20x1m0_perstn: pcie20x1m0-perstn {
> + rockchip,pins =
> /* pcie20x1_2_perstn_m0 */
> - <3 RK_PD1 4 &pcfg_pull_none>,
> + <3 RK_PD1 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie20x1m0_waken: pcie20x1m0-waken {
> + rockchip,pins =
> /* pcie20x1_2_waken_m0 */
> <3 RK_PD0 4 &pcfg_pull_none>;
> };
>
> /omit-if-no-ref/
> - pcie20x1m1_pins: pcie20x1m1-pins {
> + pcie20x1m1_clkreqn: pcie20x1m1-clkreqn {
> rockchip,pins =
> /* pcie20x1_2_clkreqn_m1 */
> - <4 RK_PB7 4 &pcfg_pull_none>,
> + <4 RK_PB7 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie20x1m1_perstn: pcie20x1m1-perstn {
> + rockchip,pins =
> /* pcie20x1_2_perstn_m1 */
> - <4 RK_PC1 4 &pcfg_pull_none>,
> + <4 RK_PC1 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie20x1m1_waken: pcie20x1m1-waken {
> + rockchip,pins =
> /* pcie20x1_2_waken_m1 */
> <4 RK_PC0 4 &pcfg_pull_none>;
> };
> @@ -1654,52 +1674,127 @@
>
> pcie30x1 {
> /omit-if-no-ref/
> - pcie30x1m0_pins: pcie30x1m0-pins {
> + pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn {
> rockchip,pins =
> /* pcie30x1_0_clkreqn_m0 */
> - <0 RK_PC0 12 &pcfg_pull_none>,
> + <0 RK_PC0 12 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m0_0_perstn: pcie30x1m0-0-perstn {
> + rockchip,pins =
> /* pcie30x1_0_perstn_m0 */
> - <0 RK_PC5 12 &pcfg_pull_none>,
> + <0 RK_PC5 12 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m0_0_waken: pcie30x1m0-0-waken {
> + rockchip,pins =
> /* pcie30x1_0_waken_m0 */
> - <0 RK_PC4 12 &pcfg_pull_none>,
> + <0 RK_PC4 12 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn {
> + rockchip,pins =
> /* pcie30x1_1_clkreqn_m0 */
> - <0 RK_PB5 12 &pcfg_pull_none>,
> + <0 RK_PB5 12 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m0_1_perstn: pcie30x1m0-1-perstn {
> + rockchip,pins =
> /* pcie30x1_1_perstn_m0 */
> - <0 RK_PB7 12 &pcfg_pull_none>,
> + <0 RK_PB7 12 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m0_1_waken: pcie30x1m0-1-waken {
> + rockchip,pins =
> /* pcie30x1_1_waken_m0 */
> <0 RK_PB6 12 &pcfg_pull_none>;
> };
>
> /omit-if-no-ref/
> - pcie30x1m1_pins: pcie30x1m1-pins {
> + pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn {
> rockchip,pins =
> /* pcie30x1_0_clkreqn_m1 */
> - <4 RK_PA3 4 &pcfg_pull_none>,
> + <4 RK_PA3 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m1_0_perstn: pcie30x1m1-0-perstn {
> + rockchip,pins =
> /* pcie30x1_0_perstn_m1 */
> - <4 RK_PA5 4 &pcfg_pull_none>,
> + <4 RK_PA5 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m1_0_waken: pcie30x1m1-0-waken {
> + rockchip,pins =
> /* pcie30x1_0_waken_m1 */
> - <4 RK_PA4 4 &pcfg_pull_none>,
> + <4 RK_PA4 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn {
> + rockchip,pins =
> /* pcie30x1_1_clkreqn_m1 */
> - <4 RK_PA0 4 &pcfg_pull_none>,
> + <4 RK_PA0 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m1_1_perstn: pcie30x1m1-1-perstn {
> + rockchip,pins =
> /* pcie30x1_1_perstn_m1 */
> - <4 RK_PA2 4 &pcfg_pull_none>,
> + <4 RK_PA2 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m1_1_waken: pcie30x1m1-1-waken {
> + rockchip,pins =
> /* pcie30x1_1_waken_m1 */
> <4 RK_PA1 4 &pcfg_pull_none>;
> };
>
> /omit-if-no-ref/
> - pcie30x1m2_pins: pcie30x1m2-pins {
> + pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn {
> rockchip,pins =
> /* pcie30x1_0_clkreqn_m2 */
> - <1 RK_PB5 4 &pcfg_pull_none>,
> + <1 RK_PB5 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m2_0_perstn: pcie30x1m2-0-perstn {
> + rockchip,pins =
> /* pcie30x1_0_perstn_m2 */
> - <1 RK_PB4 4 &pcfg_pull_none>,
> + <1 RK_PB4 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m2_0_waken: pcie30x1m2-0-waken {
> + rockchip,pins =
> /* pcie30x1_0_waken_m2 */
> - <1 RK_PB3 4 &pcfg_pull_none>,
> + <1 RK_PB3 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn {
> + rockchip,pins =
> /* pcie30x1_1_clkreqn_m2 */
> - <1 RK_PA0 4 &pcfg_pull_none>,
> + <1 RK_PA0 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m2_1_perstn: pcie30x1m2-1-perstn {
> + rockchip,pins =
> /* pcie30x1_1_perstn_m2 */
> - <1 RK_PA7 4 &pcfg_pull_none>,
> + <1 RK_PA7 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x1m2_1_waken: pcie30x1m2-1-waken {
> + rockchip,pins =
> /* pcie30x1_1_waken_m2 */
> <1 RK_PA1 4 &pcfg_pull_none>;
> };
> @@ -1721,45 +1816,85 @@
>
> pcie30x2 {
> /omit-if-no-ref/
> - pcie30x2m0_pins: pcie30x2m0-pins {
> + pcie30x2m0_clkreqn: pcie30x2m0-clkreqn {
> rockchip,pins =
> /* pcie30x2_clkreqn_m0 */
> - <0 RK_PD1 12 &pcfg_pull_none>,
> + <0 RK_PD1 12 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x2m0_perstn: pcie30x2m0-perstn {
> + rockchip,pins =
> /* pcie30x2_perstn_m0 */
> - <0 RK_PD4 12 &pcfg_pull_none>,
> + <0 RK_PD4 12 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x2m0_waken: pcie30x2m0-waken {
> + rockchip,pins =
> /* pcie30x2_waken_m0 */
> <0 RK_PD2 12 &pcfg_pull_none>;
> };
>
> /omit-if-no-ref/
> - pcie30x2m1_pins: pcie30x2m1-pins {
> + pcie30x2m1_clkreqn: pcie30x2m1-clkreqn {
> rockchip,pins =
> /* pcie30x2_clkreqn_m1 */
> - <4 RK_PA6 4 &pcfg_pull_none>,
> + <4 RK_PA6 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x2m1_perstn: pcie30x2m1-perstn {
> + rockchip,pins =
> /* pcie30x2_perstn_m1 */
> - <4 RK_PB0 4 &pcfg_pull_none>,
> + <4 RK_PB0 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x2m1_waken: pcie30x2m1-waken {
> + rockchip,pins =
> /* pcie30x2_waken_m1 */
> <4 RK_PA7 4 &pcfg_pull_none>;
> };
>
> /omit-if-no-ref/
> - pcie30x2m2_pins: pcie30x2m2-pins {
> + pcie30x2m2_clkreqn: pcie30x2m2-clkreqn {
> rockchip,pins =
> /* pcie30x2_clkreqn_m2 */
> - <3 RK_PD2 4 &pcfg_pull_none>,
> + <3 RK_PD2 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x2m2_perstn: pcie30x2m2-perstn {
> + rockchip,pins =
> /* pcie30x2_perstn_m2 */
> - <3 RK_PD4 4 &pcfg_pull_none>,
> + <3 RK_PD4 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x2m2_waken: pcie30x2m2-waken {
> + rockchip,pins =
> /* pcie30x2_waken_m2 */
> <3 RK_PD3 4 &pcfg_pull_none>;
> };
>
> /omit-if-no-ref/
> - pcie30x2m3_pins: pcie30x2m3-pins {
> + pcie30x2m3_clkreqn: pcie30x2m3-clkreqn {
> rockchip,pins =
> /* pcie30x2_clkreqn_m3 */
> - <1 RK_PD7 4 &pcfg_pull_none>,
> + <1 RK_PD7 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x2m3_perstn: pcie30x2m3-perstn {
> + rockchip,pins =
> /* pcie30x2_perstn_m3 */
> - <1 RK_PB7 4 &pcfg_pull_none>,
> + <1 RK_PB7 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x2m3_waken: pcie30x2m3-waken {
> + rockchip,pins =
> /* pcie30x2_waken_m3 */
> <1 RK_PB6 4 &pcfg_pull_none>;
> };
> @@ -1774,45 +1909,85 @@
>
> pcie30x4 {
> /omit-if-no-ref/
> - pcie30x4m0_pins: pcie30x4m0-pins {
> + pcie30x4m0_clkreqn: pcie30x4m0-clkreqn {
> rockchip,pins =
> /* pcie30x4_clkreqn_m0 */
> - <0 RK_PC6 12 &pcfg_pull_none>,
> + <0 RK_PC6 12 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x4m0_perstn: pcie30x4m0-perstn {
> + rockchip,pins =
> /* pcie30x4_perstn_m0 */
> - <0 RK_PD0 12 &pcfg_pull_none>,
> + <0 RK_PD0 12 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x4m0_waken: pcie30x4m0-waken {
> + rockchip,pins =
> /* pcie30x4_waken_m0 */
> <0 RK_PC7 12 &pcfg_pull_none>;
> };
>
> /omit-if-no-ref/
> - pcie30x4m1_pins: pcie30x4m1-pins {
> + pcie30x4m1_clkreqn: pcie30x4m1-clkreqn {
> rockchip,pins =
> /* pcie30x4_clkreqn_m1 */
> - <4 RK_PB4 4 &pcfg_pull_none>,
> + <4 RK_PB4 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x4m1_perstn: pcie30x4m1-perstn {
> + rockchip,pins =
> /* pcie30x4_perstn_m1 */
> - <4 RK_PB6 4 &pcfg_pull_none>,
> + <4 RK_PB6 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x4m1_waken: pcie30x4m1-waken {
> + rockchip,pins =
> /* pcie30x4_waken_m1 */
> <4 RK_PB5 4 &pcfg_pull_none>;
> };
>
> /omit-if-no-ref/
> - pcie30x4m2_pins: pcie30x4m2-pins {
> + pcie30x4m2_clkreqn: pcie30x4m2-clkreqn {
> rockchip,pins =
> /* pcie30x4_clkreqn_m2 */
> - <3 RK_PC4 4 &pcfg_pull_none>,
> + <3 RK_PC4 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x4m2_perstn: pcie30x4m2-perstn {
> + rockchip,pins =
> /* pcie30x4_perstn_m2 */
> - <3 RK_PC6 4 &pcfg_pull_none>,
> + <3 RK_PC6 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x4m2_waken: pcie30x4m2-waken {
> + rockchip,pins =
> /* pcie30x4_waken_m2 */
> <3 RK_PC5 4 &pcfg_pull_none>;
> };
>
> /omit-if-no-ref/
> - pcie30x4m3_pins: pcie30x4m3-pins {
> + pcie30x4m3_clkreqn: pcie30x4m3-clkreqn {
> rockchip,pins =
> /* pcie30x4_clkreqn_m3 */
> - <1 RK_PB0 4 &pcfg_pull_none>,
> + <1 RK_PB0 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x4m3_perstn: pcie30x4m3-perstn {
> + rockchip,pins =
> /* pcie30x4_perstn_m3 */
> - <1 RK_PB2 4 &pcfg_pull_none>,
> + <1 RK_PB2 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pcie30x4m3_waken: pcie30x4m3-waken {
> + rockchip,pins =
> /* pcie30x4_waken_m3 */
> <1 RK_PB1 4 &pcfg_pull_none>;
> };
> diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
> index 294b99dd50da..87fce8d9a964 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
> @@ -310,7 +310,7 @@
> };
>
> &pcie2x1l2 {
> - pinctrl-0 = <&pcie20x1m0_pins>;
> + pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>;
> pinctrl-names = "default";
> reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
> vpcie3v3-supply = <&vcc3v3_wf>;
> @@ -328,6 +328,10 @@
> pow_en: pow-en {
> rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> +
> + pcie2_reset: pcie2-reset {
> + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> };
>
> power {
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v5 2/4] arm64: dts: rockchip: Add HDMI0 node to rk3588
2025-01-04 1:57 [PATCH v5 0/4] rockchip: Add support for Radxa ROCK 5C FUKAUMI Naoki
2025-01-04 1:57 ` [PATCH v5 1/4] arm64: dts: rockchip: Split up RK3588's PCIe pinctrls FUKAUMI Naoki
@ 2025-01-04 1:57 ` FUKAUMI Naoki
2025-01-08 6:56 ` Kever Yang
2025-01-04 1:57 ` [PATCH v5 3/4] arm64: dts: rockchip: add Radxa ROCK 5C FUKAUMI Naoki
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: FUKAUMI Naoki @ 2025-01-04 1:57 UTC (permalink / raw)
To: u-boot
Cc: sjg, philipp.tomsich, kever.yang, trini, sumit.garg, jonas,
eugen.hristev, quentin.schulz, michal.simek, seb-dev,
liujianfeng1994, heiko, zhangzj, macromorgan, dsimic, pbrobinson,
cfsworks, sebastian.reichel, alchark, didi.debian, cassel,
boris.brezillon, cristian.ciocaltea, jing
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Add support for the HDMI0 output port found on RK3588 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: d7bb71e69f58c1b3665a9f926bf8d3855111bf8e ]
(cherry picked from commit a839348380c2072e00a26bbdb80744982fe04c56)
---
.../src/arm64/rockchip/rk3588-base.dtsi | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
index fc67585b64b7..a337f3fb8377 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
@@ -1370,6 +1370,47 @@
status = "disabled";
};
+ hdmi0: hdmi@fde80000 {
+ compatible = "rockchip,rk3588-dw-hdmi-qp";
+ reg = <0x0 0xfde80000 0x0 0x20000>;
+ clocks = <&cru PCLK_HDMITX0>,
+ <&cru CLK_HDMITX0_EARC>,
+ <&cru CLK_HDMITX0_REF>,
+ <&cru MCLK_I2S5_8CH_TX>,
+ <&cru CLK_HDMIHDP0>,
+ <&cru HCLK_VO1>;
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
+ phys = <&hdptxphy_hdmi0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda>;
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
+ reset-names = "ref", "hdp";
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo-grf = <&vo1_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi0_in: port@0 {
+ reg = <0>;
+ };
+
+ hdmi0_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
qos_gpu_m0: qos@fdf35000 {
compatible = "rockchip,rk3588-qos", "syscon";
reg = <0x0 0xfdf35000 0x0 0x20>;
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v5 2/4] arm64: dts: rockchip: Add HDMI0 node to rk3588
2025-01-04 1:57 ` [PATCH v5 2/4] arm64: dts: rockchip: Add HDMI0 node to rk3588 FUKAUMI Naoki
@ 2025-01-08 6:56 ` Kever Yang
0 siblings, 0 replies; 10+ messages in thread
From: Kever Yang @ 2025-01-08 6:56 UTC (permalink / raw)
To: FUKAUMI Naoki, u-boot
Cc: sjg, philipp.tomsich, trini, sumit.garg, jonas, eugen.hristev,
quentin.schulz, michal.simek, seb-dev, liujianfeng1994, heiko,
zhangzj, macromorgan, dsimic, pbrobinson, cfsworks,
sebastian.reichel, alchark, didi.debian, cassel, boris.brezillon,
cristian.ciocaltea, jing
On 2025/1/4 09:57, FUKAUMI Naoki wrote:
> From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
>
> Add support for the HDMI0 output port found on RK3588 SoC.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: d7bb71e69f58c1b3665a9f926bf8d3855111bf8e ]
>
> (cherry picked from commit a839348380c2072e00a26bbdb80744982fe04c56)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../src/arm64/rockchip/rk3588-base.dtsi | 41 +++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
> index fc67585b64b7..a337f3fb8377 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
> @@ -1370,6 +1370,47 @@
> status = "disabled";
> };
>
> + hdmi0: hdmi@fde80000 {
> + compatible = "rockchip,rk3588-dw-hdmi-qp";
> + reg = <0x0 0xfde80000 0x0 0x20000>;
> + clocks = <&cru PCLK_HDMITX0>,
> + <&cru CLK_HDMITX0_EARC>,
> + <&cru CLK_HDMITX0_REF>,
> + <&cru MCLK_I2S5_8CH_TX>,
> + <&cru CLK_HDMIHDP0>,
> + <&cru HCLK_VO1>;
> + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
> + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "avp", "cec", "earc", "main", "hpd";
> + phys = <&hdptxphy_hdmi0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
> + &hdmim0_tx0_scl &hdmim0_tx0_sda>;
> + power-domains = <&power RK3588_PD_VO1>;
> + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
> + reset-names = "ref", "hdp";
> + rockchip,grf = <&sys_grf>;
> + rockchip,vo-grf = <&vo1_grf>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hdmi0_in: port@0 {
> + reg = <0>;
> + };
> +
> + hdmi0_out: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> qos_gpu_m0: qos@fdf35000 {
> compatible = "rockchip,rk3588-qos", "syscon";
> reg = <0x0 0xfdf35000 0x0 0x20>;
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v5 3/4] arm64: dts: rockchip: add Radxa ROCK 5C
2025-01-04 1:57 [PATCH v5 0/4] rockchip: Add support for Radxa ROCK 5C FUKAUMI Naoki
2025-01-04 1:57 ` [PATCH v5 1/4] arm64: dts: rockchip: Split up RK3588's PCIe pinctrls FUKAUMI Naoki
2025-01-04 1:57 ` [PATCH v5 2/4] arm64: dts: rockchip: Add HDMI0 node to rk3588 FUKAUMI Naoki
@ 2025-01-04 1:57 ` FUKAUMI Naoki
2025-01-08 6:58 ` Kever Yang
2025-01-04 1:57 ` [PATCH v5 4/4] rockchip: Add support for " FUKAUMI Naoki
2025-01-08 7:50 ` [PATCH v5 0/4] " Sumit Garg
4 siblings, 1 reply; 10+ messages in thread
From: FUKAUMI Naoki @ 2025-01-04 1:57 UTC (permalink / raw)
To: u-boot
Cc: sjg, philipp.tomsich, kever.yang, trini, sumit.garg, jonas,
eugen.hristev, quentin.schulz, michal.simek, seb-dev,
liujianfeng1994, heiko, zhangzj, macromorgan, dsimic, pbrobinson,
cfsworks, sebastian.reichel, alchark, didi.debian, cassel,
boris.brezillon, cristian.ciocaltea, jing, FUKAUMI Naoki
Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip
RK3588S2 chip:
- Rockchip RK3588S2
- Quad A76 and Quad A55 CPU
- 6 TOPS NPU
- up to 32GB LPDDR4x RAM
- eMMC / SPI flash connector
- Micro SD Card slot
- Gigabit ethernet port (supports PoE with add-on PoE HAT)
- WiFi6 / BT5.4
- 1x USB 3.0 Type-A HOST port
- 1x USB 3.0 Type-A OTG port
- 2x USB 2.0 Type-A HOST port
- 1x USB Type-C 5V power port
[1] https://radxa.com/products/rock5/5c
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20241021090548.1052-2-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 3ddf5cdb77e6efd6fe9b70f36dec935e324a3cd2 ]
(cherry picked from commit f80689fcef4b9b07a97b629b4075cc1a4c21a68e)
---
.../src/arm64/rockchip/rk3588s-rock-5c.dts | 920 ++++++++++++++++++
1 file changed, 920 insertions(+)
create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts
new file mode 100644
index 000000000000..9b14d5383cdc
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts
@@ -0,0 +1,920 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Radxa ROCK 5C";
+ compatible = "radxa,rock-5c", "rockchip,rk3588s";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ label = "rk3588-es8316";
+ dais = <&i2s0_8ch_p0>;
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ hdmi0-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi0_con_in: endpoint {
+ remote-endpoint = <&hdmi0_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-levels = <0 64 128 192 255>;
+ fan-supply = <&vcc_5v0>;
+ pwms = <&pwm3 0 10000 0>;
+ };
+
+ pcie2x1l2_3v3: regulator-pcie2x1l2-3v3 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pow_en>;
+ regulator-name = "pcie2x1l2_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc5v_dcin: regulator-vcc5v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_usb_host: regulator-vcc5v0-usb-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren_h>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_otg_pwren_h>;
+ regulator-name = "vcc5v0_usb_otg0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc_3v3_pmu: regulator-vcc-3v3-pmu {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc_3v3_s0: regulator-vcc-3v3-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_1v8_s0>;
+ };
+
+ vcc_5v0: regulator-vcc-5v0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_5v0_pwren_h>;
+ regulator-name = "vcc_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc_sysin: regulator-vcc-sysin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sysin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_dcin>;
+ };
+
+ vcca: regulator-vcca {
+ compatible = "regulator-fixed";
+ regulator-name = "vcca";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vdd_3v3: regulator-vdd-3v3 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_wifi_pwr>;
+ regulator-name = "vdd_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac1 {
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3_s0>;
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus
+ &gmac1_clkinout>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
+&hdmi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim0_tx0_cec
+ &hdmim1_tx0_hpd
+ &hdmim0_tx0_scl
+ &hdmim0_tx0_sda>;
+ status = "okay";
+};
+
+&hdmi0_in {
+ hdmi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi0>;
+ };
+};
+
+&hdmi0_out {
+ hdmi0_out_con: endpoint {
+ remote-endpoint = <&hdmi0_con_in>;
+ };
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sysin>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sysin>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ vcc-supply = <&vcc_3v3_pmu>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sysin>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m2_xfer>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "rtcic_32kout";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int_l>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ audio-codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_rstn>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie2x1l2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20x1_2_perstn_m0>;
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&pcie2x1l2_3v3>;
+ status = "okay";
+};
+
+&pinctrl {
+ leds {
+ led_pins: led-pins {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ mdio {
+ gmac1_rstn: gmac1-rstn {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pow_en: pow-en {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rtc {
+ rtc_int_l: rtc-int-l {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_host_pwren_h: usb-host-pwren-h {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_otg_pwren_h: usb-otg-pwren-h {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_wifi_pwr: usb-wifi-pwr {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc_5v0_pwren_h: vcc-5v0-pwren-h {
+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3m1_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sdio;
+ no-sd;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&sfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim0_pins>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ system-power-controller;
+
+ vcc1-supply = <&vcc_sysin>;
+ vcc2-supply = <&vcc_sysin>;
+ vcc3-supply = <&vcc_sysin>;
+ vcc4-supply = <&vcc_sysin>;
+ vcc5-supply = <&vcc_sysin>;
+ vcc6-supply = <&vcc_sysin>;
+ vcc7-supply = <&vcc_sysin>;
+ vcc8-supply = <&vcc_sysin>;
+ vcc9-supply = <&vcc_sysin>;
+ vcc10-supply = <&vcc_sysin>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc_sysin>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcca>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_logic_s0: dcdc-reg3 {
+ regulator-name = "vdd_logic_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu_ddr_s3: dcdc-reg10 {
+ regulator-name = "vcc1v8_pmu_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg1 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg2 {
+ regulator-name = "vcca_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-name = "vdda_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-name = "vcca_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdda_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdda_0v75_s0: nldo-reg3 {
+ regulator-name = "vdda_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg4 {
+ regulator-name = "vdda_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg0>;
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ /* connected to USB hub, which is powered by vcc_5v0 */
+ phy-supply = <&vcc_5v0>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host2_xhci {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v5 3/4] arm64: dts: rockchip: add Radxa ROCK 5C
2025-01-04 1:57 ` [PATCH v5 3/4] arm64: dts: rockchip: add Radxa ROCK 5C FUKAUMI Naoki
@ 2025-01-08 6:58 ` Kever Yang
0 siblings, 0 replies; 10+ messages in thread
From: Kever Yang @ 2025-01-08 6:58 UTC (permalink / raw)
To: FUKAUMI Naoki, u-boot
Cc: sjg, philipp.tomsich, trini, sumit.garg, jonas, eugen.hristev,
quentin.schulz, michal.simek, seb-dev, liujianfeng1994, heiko,
zhangzj, macromorgan, dsimic, pbrobinson, cfsworks,
sebastian.reichel, alchark, didi.debian, cassel, boris.brezillon,
cristian.ciocaltea, jing
On 2025/1/4 09:57, FUKAUMI Naoki wrote:
> Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip
> RK3588S2 chip:
>
> - Rockchip RK3588S2
> - Quad A76 and Quad A55 CPU
> - 6 TOPS NPU
> - up to 32GB LPDDR4x RAM
> - eMMC / SPI flash connector
> - Micro SD Card slot
> - Gigabit ethernet port (supports PoE with add-on PoE HAT)
> - WiFi6 / BT5.4
> - 1x USB 3.0 Type-A HOST port
> - 1x USB 3.0 Type-A OTG port
> - 2x USB 2.0 Type-A HOST port
> - 1x USB Type-C 5V power port
>
> [1] https://radxa.com/products/rock5/5c
>
> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
> Link: https://lore.kernel.org/r/20241021090548.1052-2-naoki@radxa.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 3ddf5cdb77e6efd6fe9b70f36dec935e324a3cd2 ]
>
> (cherry picked from commit f80689fcef4b9b07a97b629b4075cc1a4c21a68e)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../src/arm64/rockchip/rk3588s-rock-5c.dts | 920 ++++++++++++++++++
> 1 file changed, 920 insertions(+)
> create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts
> new file mode 100644
> index 000000000000..9b14d5383cdc
> --- /dev/null
> +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts
> @@ -0,0 +1,920 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/soc/rockchip,vop2.h>
> +#include "rk3588s.dtsi"
> +
> +/ {
> + model = "Radxa ROCK 5C";
> + compatible = "radxa,rock-5c", "rockchip,rk3588s";
> +
> + aliases {
> + ethernet0 = &gmac1;
> + mmc0 = &sdhci;
> + mmc1 = &sdmmc;
> + };
> +
> + chosen {
> + stdout-path = "serial2:1500000n8";
> + };
> +
> + analog-sound {
> + compatible = "audio-graph-card";
> + label = "rk3588-es8316";
> + dais = <&i2s0_8ch_p0>;
> + routing = "MIC2", "Mic Jack",
> + "Headphones", "HPOL",
> + "Headphones", "HPOR";
> + widgets = "Microphone", "Mic Jack",
> + "Headphone", "Headphones";
> + };
> +
> + hdmi0-con {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi0_con_in: endpoint {
> + remote-endpoint = <&hdmi0_out_con>;
> + };
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&led_pins>;
> +
> + led-0 {
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "on";
> + function = LED_FUNCTION_POWER;
> + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
> + };
> +
> + led-1 {
> + color = <LED_COLOR_ID_BLUE>;
> + default-state = "on";
> + function = LED_FUNCTION_HEARTBEAT;
> + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +
> + fan {
> + compatible = "pwm-fan";
> + #cooling-cells = <2>;
> + cooling-levels = <0 64 128 192 255>;
> + fan-supply = <&vcc_5v0>;
> + pwms = <&pwm3 0 10000 0>;
> + };
> +
> + pcie2x1l2_3v3: regulator-pcie2x1l2-3v3 {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pow_en>;
> + regulator-name = "pcie2x1l2_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&vcc_sysin>;
> + };
> +
> + vcc5v_dcin: regulator-vcc5v-dcin {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v_dcin";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + vcc5v0_usb_host: regulator-vcc5v0-usb-host {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&usb_host_pwren_h>;
> + regulator-name = "vcc5v0_usb_host";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc_sysin>;
> + };
> +
> + vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&usb_otg_pwren_h>;
> + regulator-name = "vcc5v0_usb_otg0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc_sysin>;
> + };
> +
> + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_1v1_nldo_s3";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + vin-supply = <&vcc_sysin>;
> + };
> +
> + vcc_3v3_pmu: regulator-vcc-3v3-pmu {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_3v3_pmu";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&vcc_3v3_s3>;
> + };
> +
> + vcc_3v3_s0: regulator-vcc-3v3-s0 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_3v3_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&vcc_1v8_s0>;
> + };
> +
> + vcc_5v0: regulator-vcc-5v0 {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&vcc_5v0_pwren_h>;
> + regulator-name = "vcc_5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc_sysin>;
> + };
> +
> + vcc_sysin: regulator-vcc-sysin {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_sysin";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc5v_dcin>;
> + };
> +
> + vcca: regulator-vcca {
> + compatible = "regulator-fixed";
> + regulator-name = "vcca";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <4000000>;
> + regulator-max-microvolt = <4000000>;
> + vin-supply = <&vcc_sysin>;
> + };
> +
> + vdd_3v3: regulator-vdd-3v3 {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&usb_wifi_pwr>;
> + regulator-name = "vdd_3v3";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&vcc_3v3_s3>;
> + };
> +};
> +
> +&combphy0_ps {
> + status = "okay";
> +};
> +
> +&combphy2_psu {
> + status = "okay";
> +};
> +
> +&cpu_b0 {
> + cpu-supply = <&vdd_cpu_big0_s0>;
> +};
> +
> +&cpu_b1 {
> + cpu-supply = <&vdd_cpu_big0_s0>;
> +};
> +
> +&cpu_b2 {
> + cpu-supply = <&vdd_cpu_big1_s0>;
> +};
> +
> +&cpu_b3 {
> + cpu-supply = <&vdd_cpu_big1_s0>;
> +};
> +
> +&cpu_l0 {
> + cpu-supply = <&vdd_cpu_lit_s0>;
> +};
> +
> +&cpu_l1 {
> + cpu-supply = <&vdd_cpu_lit_s0>;
> +};
> +
> +&cpu_l2 {
> + cpu-supply = <&vdd_cpu_lit_s0>;
> +};
> +
> +&cpu_l3 {
> + cpu-supply = <&vdd_cpu_lit_s0>;
> +};
> +
> +&gmac1 {
> + phy-handle = <&rgmii_phy1>;
> + phy-mode = "rgmii-id";
> + phy-supply = <&vcc_3v3_s0>;
> + pinctrl-0 = <&gmac1_miim
> + &gmac1_tx_bus2
> + &gmac1_rx_bus2
> + &gmac1_rgmii_clk
> + &gmac1_rgmii_bus
> + &gmac1_clkinout>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&gpu {
> + mali-supply = <&vdd_gpu_s0>;
> + status = "okay";
> +};
> +
> +&hdmi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmim0_tx0_cec
> + &hdmim1_tx0_hpd
> + &hdmim0_tx0_scl
> + &hdmim0_tx0_sda>;
> + status = "okay";
> +};
> +
> +&hdmi0_in {
> + hdmi0_in_vp0: endpoint {
> + remote-endpoint = <&vp0_out_hdmi0>;
> + };
> +};
> +
> +&hdmi0_out {
> + hdmi0_out_con: endpoint {
> + remote-endpoint = <&hdmi0_con_in>;
> + };
> +};
> +
> +&hdptxphy_hdmi0 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0m2_xfer>;
> + status = "okay";
> +
> + vdd_cpu_big0_s0: regulator@42 {
> + compatible = "rockchip,rk8602";
> + reg = <0x42>;
> + fcs,suspend-voltage-selector = <1>;
> + regulator-name = "vdd_cpu_big0_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <1050000>;
> + regulator-ramp-delay = <2300>;
> + vin-supply = <&vcc_sysin>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd_cpu_big1_s0: regulator@43 {
> + compatible = "rockchip,rk8603", "rockchip,rk8602";
> + reg = <0x43>;
> + fcs,suspend-voltage-selector = <1>;
> + regulator-name = "vdd_cpu_big1_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <1050000>;
> + regulator-ramp-delay = <2300>;
> + vin-supply = <&vcc_sysin>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + eeprom@50 {
> + compatible = "belling,bl24c16a", "atmel,24c16";
> + reg = <0x50>;
> + pagesize = <16>;
> + vcc-supply = <&vcc_3v3_pmu>;
> + };
> +};
> +
> +&i2c2 {
> + status = "okay";
> +
> + vdd_npu_s0: regulator@42 {
> + compatible = "rockchip,rk8602";
> + reg = <0x42>;
> + fcs,suspend-voltage-selector = <1>;
> + regulator-name = "vdd_npu_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <950000>;
> + regulator-ramp-delay = <2300>;
> + vin-supply = <&vcc_sysin>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +};
> +
> +&i2c5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c5m2_xfer>;
> + status = "okay";
> +
> + rtc@51 {
> + compatible = "haoyu,hym8563";
> + reg = <0x51>;
> + #clock-cells = <0>;
> + clock-output-names = "rtcic_32kout";
> + interrupt-parent = <&gpio0>;
> + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&rtc_int_l>;
> + };
> +};
> +
> +&i2c7 {
> + status = "okay";
> +
> + audio-codec@11 {
> + compatible = "everest,es8316";
> + reg = <0x11>;
> + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
> + assigned-clock-rates = <12288000>;
> + clocks = <&cru I2S0_8CH_MCLKOUT>;
> + clock-names = "mclk";
> + #sound-dai-cells = <0>;
> +
> + port {
> + es8316_p0_0: endpoint {
> + remote-endpoint = <&i2s0_8ch_p0_0>;
> + };
> + };
> + };
> +};
> +
> +&i2s0_8ch {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s0_lrck
> + &i2s0_mclk
> + &i2s0_sclk
> + &i2s0_sdi0
> + &i2s0_sdo0>;
> + status = "okay";
> +
> + i2s0_8ch_p0: port {
> + i2s0_8ch_p0_0: endpoint {
> + dai-format = "i2s";
> + mclk-fs = <256>;
> + remote-endpoint = <&es8316_p0_0>;
> + };
> + };
> +};
> +
> +&mdio1 {
> + rgmii_phy1: ethernet-phy@1 {
> + compatible = "ethernet-phy-id001c.c916";
> + reg = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac1_rstn>;
> + reset-assert-us = <20000>;
> + reset-deassert-us = <100000>;
> + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&pcie2x1l2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie20x1_2_perstn_m0>;
> + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
> + vpcie3v3-supply = <&pcie2x1l2_3v3>;
> + status = "okay";
> +};
> +
> +&pinctrl {
> + leds {
> + led_pins: led-pins {
> + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
> + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + mdio {
> + gmac1_rstn: gmac1-rstn {
> + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + pcie {
> + pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 {
> + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + pow_en: pow-en {
> + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + rtc {
> + rtc_int_l: rtc-int-l {
> + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + usb {
> + usb_host_pwren_h: usb-host-pwren-h {
> + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + usb_otg_pwren_h: usb-otg-pwren-h {
> + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + usb_wifi_pwr: usb-wifi-pwr {
> + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + vcc_5v0_pwren_h: vcc-5v0-pwren-h {
> + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +};
> +
> +&pwm3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm3m1_pins>;
> + status = "okay";
> +};
> +
> +&saradc {
> + vref-supply = <&vcca_1v8_s0>;
> + status = "okay";
> +};
> +
> +&sdhci {
> + bus-width = <8>;
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
> + no-sdio;
> + no-sd;
> + non-removable;
> + status = "okay";
> +};
> +
> +&sdmmc {
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + disable-wp;
> + no-sdio;
> + no-mmc;
> + sd-uhs-sdr104;
> + vmmc-supply = <&vcc_3v3_s3>;
> + vqmmc-supply = <&vccio_sd_s0>;
> + status = "okay";
> +};
> +
> +&sfc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&fspim0_pins>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <104000000>;
> + spi-rx-bus-width = <4>;
> + spi-tx-bus-width = <1>;
> + };
> +};
> +
> +&spi2 {
> + status = "okay";
> + assigned-clocks = <&cru CLK_SPI2>;
> + assigned-clock-rates = <200000000>;
> + num-cs = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
> +
> + pmic@0 {
> + compatible = "rockchip,rk806";
> + reg = <0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
> + <&rk806_dvs2_null>, <&rk806_dvs3_null>;
> + spi-max-frequency = <1000000>;
> + system-power-controller;
> +
> + vcc1-supply = <&vcc_sysin>;
> + vcc2-supply = <&vcc_sysin>;
> + vcc3-supply = <&vcc_sysin>;
> + vcc4-supply = <&vcc_sysin>;
> + vcc5-supply = <&vcc_sysin>;
> + vcc6-supply = <&vcc_sysin>;
> + vcc7-supply = <&vcc_sysin>;
> + vcc8-supply = <&vcc_sysin>;
> + vcc9-supply = <&vcc_sysin>;
> + vcc10-supply = <&vcc_sysin>;
> + vcc11-supply = <&vcc_2v0_pldo_s3>;
> + vcc12-supply = <&vcc_sysin>;
> + vcc13-supply = <&vcc_1v1_nldo_s3>;
> + vcc14-supply = <&vcc_1v1_nldo_s3>;
> + vcca-supply = <&vcca>;
> +
> + rk806_dvs1_null: dvs1-null-pins {
> + pins = "gpio_pwrctrl1";
> + function = "pin_fun0";
> + };
> +
> + rk806_dvs2_null: dvs2-null-pins {
> + pins = "gpio_pwrctrl2";
> + function = "pin_fun0";
> + };
> +
> + rk806_dvs3_null: dvs3-null-pins {
> + pins = "gpio_pwrctrl3";
> + function = "pin_fun0";
> + };
> +
> + regulators {
> + vdd_gpu_s0: dcdc-reg1 {
> + regulator-name = "vdd_gpu_s0";
> + regulator-boot-on;
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <950000>;
> + regulator-ramp-delay = <12500>;
> + regulator-enable-ramp-delay = <400>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd_cpu_lit_s0: dcdc-reg2 {
> + regulator-name = "vdd_cpu_lit_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <950000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd_logic_s0: dcdc-reg3 {
> + regulator-name = "vdd_logic_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <675000>;
> + regulator-max-microvolt = <750000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <750000>;
> + };
> + };
> +
> + vdd_vdenc_s0: dcdc-reg4 {
> + regulator-name = "vdd_vdenc_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <950000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd_ddr_s0: dcdc-reg5 {
> + regulator-name = "vdd_ddr_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <675000>;
> + regulator-max-microvolt = <900000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + regulator-suspend-microvolt = <850000>;
> + };
> + };
> +
> + vdd2_ddr_s3: dcdc-reg6 {
> + regulator-name = "vdd2_ddr_s3";
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + vcc_2v0_pldo_s3: dcdc-reg7 {
> + regulator-name = "vdd_2v0_pldo_s3";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <2000000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <2000000>;
> + };
> + };
> +
> + vcc_3v3_s3: dcdc-reg8 {
> + regulator-name = "vcc_3v3_s3";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vddq_ddr_s0: dcdc-reg9 {
> + regulator-name = "vddq_ddr_s0";
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc1v8_pmu_ddr_s3: dcdc-reg10 {
> + regulator-name = "vcc1v8_pmu_ddr_s3";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> + };
> +
> + vcc_1v8_s0: pldo-reg1 {
> + regulator-name = "vcc_1v8_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> + };
> +
> + vcca_1v8_s0: pldo-reg2 {
> + regulator-name = "vcca_1v8_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> + };
> +
> + vdda_1v2_s0: pldo-reg3 {
> + regulator-name = "vdda_1v2_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcca_3v3_s0: pldo-reg4 {
> + regulator-name = "vcca_3v3_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vccio_sd_s0: pldo-reg5 {
> + regulator-name = "vccio_sd_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + pldo6_s3: pldo-reg6 {
> + regulator-name = "pldo6_s3";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> + };
> +
> + vdd_0v75_s3: nldo-reg1 {
> + regulator-name = "vdd_0v75_s3";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <750000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <750000>;
> + };
> + };
> +
> + vdda_ddr_pll_s0: nldo-reg2 {
> + regulator-name = "vdda_ddr_pll_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <850000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <850000>;
> + };
> + };
> +
> + vdda_0v75_s0: nldo-reg3 {
> + regulator-name = "vdda_0v75_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <750000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdda_0v85_s0: nldo-reg4 {
> + regulator-name = "vdda_0v85_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <850000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd_0v75_s0: nldo-reg5 {
> + regulator-name = "vdd_0v75_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <750000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> + };
> + };
> +};
> +
> +&tsadc {
> + status = "okay";
> +};
> +
> +&u2phy0 {
> + status = "okay";
> +};
> +
> +&u2phy0_otg {
> + phy-supply = <&vcc5v0_usb_otg0>;
> + status = "okay";
> +};
> +
> +&u2phy2 {
> + status = "okay";
> +};
> +
> +&u2phy2_host {
> + /* connected to USB hub, which is powered by vcc_5v0 */
> + phy-supply = <&vcc_5v0>;
> + status = "okay";
> +};
> +
> +&u2phy3 {
> + status = "okay";
> +};
> +
> +&u2phy3_host {
> + phy-supply = <&vcc5v0_usb_host>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-0 = <&uart2m0_xfer>;
> + status = "okay";
> +};
> +
> +&usbdp_phy0 {
> + status = "okay";
> +};
> +
> +&usb_host0_ehci {
> + status = "okay";
> +};
> +
> +&usb_host0_xhci {
> + dr_mode = "host";
> + status = "okay";
> +};
> +
> +&usb_host1_ehci {
> + status = "okay";
> +};
> +
> +&usb_host1_ohci {
> + status = "okay";
> +};
> +
> +&usb_host2_xhci {
> + status = "okay";
> +};
> +
> +&vop_mmu {
> + status = "okay";
> +};
> +
> +&vop {
> + status = "okay";
> +};
> +
> +&vp0 {
> + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
> + reg = <ROCKCHIP_VOP2_EP_HDMI0>;
> + remote-endpoint = <&hdmi0_in_vp0>;
> + };
> +};
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v5 4/4] rockchip: Add support for Radxa ROCK 5C
2025-01-04 1:57 [PATCH v5 0/4] rockchip: Add support for Radxa ROCK 5C FUKAUMI Naoki
` (2 preceding siblings ...)
2025-01-04 1:57 ` [PATCH v5 3/4] arm64: dts: rockchip: add Radxa ROCK 5C FUKAUMI Naoki
@ 2025-01-04 1:57 ` FUKAUMI Naoki
2025-01-08 6:58 ` Kever Yang
2025-01-08 7:50 ` [PATCH v5 0/4] " Sumit Garg
4 siblings, 1 reply; 10+ messages in thread
From: FUKAUMI Naoki @ 2025-01-04 1:57 UTC (permalink / raw)
To: u-boot
Cc: sjg, philipp.tomsich, kever.yang, trini, sumit.garg, jonas,
eugen.hristev, quentin.schulz, michal.simek, seb-dev,
liujianfeng1994, heiko, zhangzj, macromorgan, dsimic, pbrobinson,
cfsworks, sebastian.reichel, alchark, didi.debian, cassel,
boris.brezillon, cristian.ciocaltea, jing, FUKAUMI Naoki
Radxa ROCK 5C[1] is a Rockchip RK3588S2 based single board computer.
[1] https://radxa.com/products/rock5/5c
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
---
Changes in v5:
- None
Changes in v4:
- ROCK 5A section was removed and most of it rewritten for ROCK 5C
- Trivial changes
Changes in v3:
- Fix compile error
Changes in v2:
- arch/arm/dts/rk3588s-rock-5-u-boot.dtsi: remove unused node
- include/configs/rock-5-rk3588s.h: fix include order
---
arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi | 11 ++++
arch/arm/mach-rockchip/rk3588/Kconfig | 21 ++++++
board/radxa/rock-5c-rk3588s/Kconfig | 12 ++++
board/radxa/rock-5c-rk3588s/MAINTAINERS | 7 ++
configs/rock-5c-rk3588s_defconfig | 84 ++++++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
include/configs/rock-5c-rk3588s.h | 15 +++++
7 files changed, 151 insertions(+)
create mode 100644 arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
create mode 100644 board/radxa/rock-5c-rk3588s/Kconfig
create mode 100644 board/radxa/rock-5c-rk3588s/MAINTAINERS
create mode 100644 configs/rock-5c-rk3588s_defconfig
create mode 100644 include/configs/rock-5c-rk3588s.h
diff --git a/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
new file mode 100644
index 000000000000..1dc574c2f219
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024-2025 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+#include "rk3588s-u-boot.dtsi"
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index b5a0e624a532..448cfaf0d60d 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -260,6 +260,26 @@ config TARGET_ROCK_5_ITX_RK3588
Front-panel connectors for audio and case-power, -leds
Powered by either 12V, ATX power-supply or PoE
+config TARGET_ROCK_5C_RK3588S
+ bool "Radxa ROCK 5C RK3588S2 board"
+ select BOARD_LATE_INIT
+ help
+ Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer.
+
+ Specification:
+
+ Quad A76 and Quad A55 CPU
+ 6 TOPS NPU
+ up to 32GB LPDDR4x RAM
+ eMMC / SPI flash connector
+ Micro SD Card slot
+ Gigabit ethernet port (supports PoE with add-on PoE HAT)
+ WiFi6 / BT5.4
+ 1x USB 3.0 Type-A HOST port
+ 1x USB 3.0 Type-A OTG port
+ 2x USB 2.0 Type-A HOST port
+ 1x USB Type-C 5V power port
+
config TARGET_SIGE7_RK3588
bool "ArmSoM Sige7 RK3588 board"
select BOARD_LATE_INIT
@@ -398,6 +418,7 @@ source "board/turing/turing-rk1-rk3588/Kconfig"
source "board/radxa/rock5a-rk3588s/Kconfig"
source "board/radxa/rock5b-rk3588/Kconfig"
source "board/radxa/rock-5-itx-rk3588/Kconfig"
+source "board/radxa/rock-5c-rk3588s/Kconfig"
source "board/rockchip/evb_rk3588/Kconfig"
source "board/rockchip/toybrick_rk3588/Kconfig"
source "board/theobroma-systems/jaguar_rk3588/Kconfig"
diff --git a/board/radxa/rock-5c-rk3588s/Kconfig b/board/radxa/rock-5c-rk3588s/Kconfig
new file mode 100644
index 000000000000..ec964bdcb934
--- /dev/null
+++ b/board/radxa/rock-5c-rk3588s/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ROCK_5C_RK3588S
+
+config SYS_BOARD
+ default "rock-5c-rk3588s"
+
+config SYS_VENDOR
+ default "radxa"
+
+config SYS_CONFIG_NAME
+ default "rock-5c-rk3588s"
+
+endif
diff --git a/board/radxa/rock-5c-rk3588s/MAINTAINERS b/board/radxa/rock-5c-rk3588s/MAINTAINERS
new file mode 100644
index 000000000000..17183c739d67
--- /dev/null
+++ b/board/radxa/rock-5c-rk3588s/MAINTAINERS
@@ -0,0 +1,7 @@
+ROCK-5C-RK3588S
+M: FUKAUMI Naoki <naoki@radxa.com>
+S: Maintained
+F: arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
+F: board/radxa/rock-5c-rk3588s/
+F: configs/rock-5c-rk3588s_defconfig
+F: include/configs/rock-5c-rk3588s.h
diff --git a/configs/rock-5c-rk3588s_defconfig b/configs/rock-5c-rk3588s_defconfig
new file mode 100644
index 000000000000..59f9f25edcb8
--- /dev/null
+++ b/configs/rock-5c-rk3588s_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-rock-5c"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_ROCK_5C_RK3588S=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 9bab86d23479..dbe199a13c46 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -141,6 +141,7 @@ List of mainline supported Rockchip boards:
- Radxa ROCK 5 ITX (rock-5-itx-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- Radxa ROCK 5B (rock5b-rk3588)
+ - Radxa ROCK 5C (rock-5c-rk3588s)
- Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
- Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
- Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588)
diff --git a/include/configs/rock-5c-rk3588s.h b/include/configs/rock-5c-rk3588s.h
new file mode 100644
index 000000000000..0fd76c96f0ca
--- /dev/null
+++ b/include/configs/rock-5c-rk3588s.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024-2025 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+#ifndef __ROCK_5C_RK3588S_H
+#define __ROCK_5C_RK3588S_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __ROCK_5C_RK3588S_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v5 4/4] rockchip: Add support for Radxa ROCK 5C
2025-01-04 1:57 ` [PATCH v5 4/4] rockchip: Add support for " FUKAUMI Naoki
@ 2025-01-08 6:58 ` Kever Yang
0 siblings, 0 replies; 10+ messages in thread
From: Kever Yang @ 2025-01-08 6:58 UTC (permalink / raw)
To: FUKAUMI Naoki, u-boot
Cc: sjg, philipp.tomsich, trini, sumit.garg, jonas, eugen.hristev,
quentin.schulz, michal.simek, seb-dev, liujianfeng1994, heiko,
zhangzj, macromorgan, dsimic, pbrobinson, cfsworks,
sebastian.reichel, alchark, didi.debian, cassel, boris.brezillon,
cristian.ciocaltea, jing
On 2025/1/4 09:57, FUKAUMI Naoki wrote:
> Radxa ROCK 5C[1] is a Rockchip RK3588S2 based single board computer.
>
> [1] https://radxa.com/products/rock5/5c
>
> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> Changes in v5:
> - None
> Changes in v4:
> - ROCK 5A section was removed and most of it rewritten for ROCK 5C
> - Trivial changes
> Changes in v3:
> - Fix compile error
> Changes in v2:
> - arch/arm/dts/rk3588s-rock-5-u-boot.dtsi: remove unused node
> - include/configs/rock-5-rk3588s.h: fix include order
> ---
> arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi | 11 ++++
> arch/arm/mach-rockchip/rk3588/Kconfig | 21 ++++++
> board/radxa/rock-5c-rk3588s/Kconfig | 12 ++++
> board/radxa/rock-5c-rk3588s/MAINTAINERS | 7 ++
> configs/rock-5c-rk3588s_defconfig | 84 ++++++++++++++++++++++++
> doc/board/rockchip/rockchip.rst | 1 +
> include/configs/rock-5c-rk3588s.h | 15 +++++
> 7 files changed, 151 insertions(+)
> create mode 100644 arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
> create mode 100644 board/radxa/rock-5c-rk3588s/Kconfig
> create mode 100644 board/radxa/rock-5c-rk3588s/MAINTAINERS
> create mode 100644 configs/rock-5c-rk3588s_defconfig
> create mode 100644 include/configs/rock-5c-rk3588s.h
>
> diff --git a/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
> new file mode 100644
> index 000000000000..1dc574c2f219
> --- /dev/null
> +++ b/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
> @@ -0,0 +1,11 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2024-2025 Radxa Computer (Shenzhen) Co., Ltd.
> + */
> +
> +#include "rk3588s-u-boot.dtsi"
> +
> +&sdhci {
> + cap-mmc-highspeed;
> + mmc-hs200-1_8v;
> +};
> diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
> index b5a0e624a532..448cfaf0d60d 100644
> --- a/arch/arm/mach-rockchip/rk3588/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3588/Kconfig
> @@ -260,6 +260,26 @@ config TARGET_ROCK_5_ITX_RK3588
> Front-panel connectors for audio and case-power, -leds
> Powered by either 12V, ATX power-supply or PoE
>
> +config TARGET_ROCK_5C_RK3588S
> + bool "Radxa ROCK 5C RK3588S2 board"
> + select BOARD_LATE_INIT
> + help
> + Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer.
> +
> + Specification:
> +
> + Quad A76 and Quad A55 CPU
> + 6 TOPS NPU
> + up to 32GB LPDDR4x RAM
> + eMMC / SPI flash connector
> + Micro SD Card slot
> + Gigabit ethernet port (supports PoE with add-on PoE HAT)
> + WiFi6 / BT5.4
> + 1x USB 3.0 Type-A HOST port
> + 1x USB 3.0 Type-A OTG port
> + 2x USB 2.0 Type-A HOST port
> + 1x USB Type-C 5V power port
> +
> config TARGET_SIGE7_RK3588
> bool "ArmSoM Sige7 RK3588 board"
> select BOARD_LATE_INIT
> @@ -398,6 +418,7 @@ source "board/turing/turing-rk1-rk3588/Kconfig"
> source "board/radxa/rock5a-rk3588s/Kconfig"
> source "board/radxa/rock5b-rk3588/Kconfig"
> source "board/radxa/rock-5-itx-rk3588/Kconfig"
> +source "board/radxa/rock-5c-rk3588s/Kconfig"
> source "board/rockchip/evb_rk3588/Kconfig"
> source "board/rockchip/toybrick_rk3588/Kconfig"
> source "board/theobroma-systems/jaguar_rk3588/Kconfig"
> diff --git a/board/radxa/rock-5c-rk3588s/Kconfig b/board/radxa/rock-5c-rk3588s/Kconfig
> new file mode 100644
> index 000000000000..ec964bdcb934
> --- /dev/null
> +++ b/board/radxa/rock-5c-rk3588s/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_ROCK_5C_RK3588S
> +
> +config SYS_BOARD
> + default "rock-5c-rk3588s"
> +
> +config SYS_VENDOR
> + default "radxa"
> +
> +config SYS_CONFIG_NAME
> + default "rock-5c-rk3588s"
> +
> +endif
> diff --git a/board/radxa/rock-5c-rk3588s/MAINTAINERS b/board/radxa/rock-5c-rk3588s/MAINTAINERS
> new file mode 100644
> index 000000000000..17183c739d67
> --- /dev/null
> +++ b/board/radxa/rock-5c-rk3588s/MAINTAINERS
> @@ -0,0 +1,7 @@
> +ROCK-5C-RK3588S
> +M: FUKAUMI Naoki <naoki@radxa.com>
> +S: Maintained
> +F: arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
> +F: board/radxa/rock-5c-rk3588s/
> +F: configs/rock-5c-rk3588s_defconfig
> +F: include/configs/rock-5c-rk3588s.h
> diff --git a/configs/rock-5c-rk3588s_defconfig b/configs/rock-5c-rk3588s_defconfig
> new file mode 100644
> index 000000000000..59f9f25edcb8
> --- /dev/null
> +++ b/configs/rock-5c-rk3588s_defconfig
> @@ -0,0 +1,84 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
> +CONFIG_COUNTER_FREQUENCY=24000000
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-rock-5c"
> +CONFIG_ROCKCHIP_RK3588=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_TARGET_ROCK_5C_RK3588S=y
> +CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_DEBUG_UART_BASE=0xFEB50000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_PCI=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_AHCI=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_FIT_SIGNATURE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_LEGACY_IMAGE_FORMAT=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5c.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_SPL_MAX_SIZE=0x40000
> +CONFIG_SPL_PAD_TO=0x7f8000
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_ATF=y
> +CONFIG_CMD_ADC=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_REGULATOR=y
> +# CONFIG_SPL_DOS_PARTITION is not set
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_LIVE=y
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_SCSI_AHCI=y
> +CONFIG_AHCI_PCI=y
> +CONFIG_SPL_CLK=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_LED=y
> +CONFIG_LED_GPIO=y
> +CONFIG_MISC=y
> +CONFIG_SUPPORT_EMMC_RPMB=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_SDMA=y
> +CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_PHY_REALTEK=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y
> +CONFIG_RTL8169=y
> +CONFIG_NVME_PCI=y
> +CONFIG_PCIE_DW_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
> +CONFIG_PHY_ROCKCHIP_USBDP=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_DM_PMIC=y
> +CONFIG_PMIC_RK8XX=y
> +CONFIG_REGULATOR_RK8XX=y
> +CONFIG_SPL_RAM=y
> +CONFIG_SCSI=y
> +CONFIG_BAUDRATE=1500000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550_MEM32=y
> +CONFIG_ROCKCHIP_SPI=y
> +CONFIG_SYSRESET=y
> +CONFIG_SYSRESET_PSCI=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_OHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
> +CONFIG_ERRNO_STR=y
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index 9bab86d23479..dbe199a13c46 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -141,6 +141,7 @@ List of mainline supported Rockchip boards:
> - Radxa ROCK 5 ITX (rock-5-itx-rk3588)
> - Radxa ROCK 5A (rock5a-rk3588s)
> - Radxa ROCK 5B (rock5b-rk3588)
> + - Radxa ROCK 5C (rock-5c-rk3588s)
> - Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
> - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
> - Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588)
> diff --git a/include/configs/rock-5c-rk3588s.h b/include/configs/rock-5c-rk3588s.h
> new file mode 100644
> index 000000000000..0fd76c96f0ca
> --- /dev/null
> +++ b/include/configs/rock-5c-rk3588s.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2024-2025 Radxa Computer (Shenzhen) Co., Ltd.
> + */
> +
> +#ifndef __ROCK_5C_RK3588S_H
> +#define __ROCK_5C_RK3588S_H
> +
> +#define ROCKCHIP_DEVICE_SETTINGS \
> + "stdout=serial,vidconsole\0" \
> + "stderr=serial,vidconsole\0"
> +
> +#include <configs/rk3588_common.h>
> +
> +#endif /* __ROCK_5C_RK3588S_H */
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v5 0/4] rockchip: Add support for Radxa ROCK 5C
2025-01-04 1:57 [PATCH v5 0/4] rockchip: Add support for Radxa ROCK 5C FUKAUMI Naoki
` (3 preceding siblings ...)
2025-01-04 1:57 ` [PATCH v5 4/4] rockchip: Add support for " FUKAUMI Naoki
@ 2025-01-08 7:50 ` Sumit Garg
4 siblings, 0 replies; 10+ messages in thread
From: Sumit Garg @ 2025-01-08 7:50 UTC (permalink / raw)
To: FUKAUMI Naoki
Cc: u-boot, sjg, philipp.tomsich, kever.yang, trini, jonas,
eugen.hristev, quentin.schulz, michal.simek, seb-dev,
liujianfeng1994, heiko, zhangzj, macromorgan, dsimic, pbrobinson,
cfsworks, sebastian.reichel, alchark, didi.debian, cassel,
boris.brezillon, cristian.ciocaltea, jing
On Sat, 4 Jan 2025 at 07:28, FUKAUMI Naoki <naoki@radxa.com> wrote:
>
> Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer.
>
> Changes in v5:
> - Rebase on top of latest next branch
> - Drop PATCH 1/5
>
For the series:
Acked-by: Sumit Garg <sumit.garg@linaro.org>
-Sumit
> Cristian Ciocaltea (1):
> arm64: dts: rockchip: Add HDMI0 node to rk3588
>
> FUKAUMI Naoki (2):
> arm64: dts: rockchip: add Radxa ROCK 5C
> rockchip: Add support for Radxa ROCK 5C
>
> Sam Edwards (1):
> arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
>
> arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi | 11 +
> arch/arm/mach-rockchip/rk3588/Kconfig | 21 +
> board/radxa/rock-5c-rk3588s/Kconfig | 12 +
> board/radxa/rock-5c-rk3588s/MAINTAINERS | 7 +
> configs/rock-5c-rk3588s_defconfig | 84 ++
> doc/board/rockchip/rockchip.rst | 1 +
> .../arm64/rockchip/rk3588-base-pinctrl.dtsi | 271 +++++-
> .../src/arm64/rockchip/rk3588-base.dtsi | 41 +
> .../src/arm64/rockchip/rk3588s-rock-5a.dts | 6 +-
> .../src/arm64/rockchip/rk3588s-rock-5c.dts | 920 ++++++++++++++++++
> include/configs/rock-5c-rk3588s.h | 15 +
> 11 files changed, 1340 insertions(+), 49 deletions(-)
> create mode 100644 arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
> create mode 100644 board/radxa/rock-5c-rk3588s/Kconfig
> create mode 100644 board/radxa/rock-5c-rk3588s/MAINTAINERS
> create mode 100644 configs/rock-5c-rk3588s_defconfig
> create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts
> create mode 100644 include/configs/rock-5c-rk3588s.h
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 10+ messages in thread